JP4067470B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a capacitive insulating film using a ferroelectric film or a high dielectric film.

  In recent years, for example, a semiconductor device represented by a ferroelectric nonvolatile memory using a capacitor having a ferroelectric or high dielectric as a capacitive insulating film has been widely used. However, these capacitive insulating films are easily reduced in the presence of hydrogen and moisture, and their characteristics deteriorate.

  Conventionally, in order to prevent the influence of hydrogen and moisture on a capacitive insulating film made of a ferroelectric or high dielectric material (degradation of characteristics of the capacitive insulating film), an oxide film is formed on the capacitor in a hydrogen-free state. (For example, Patent Document 1).

  In the conventional example described in Patent Document 1, a protective film is formed as a two-layer film, a sputtering film or SOG film is formed as a lower layer, and then an ozone-oxidized TEOS film is formed as an upper layer at a substrate temperature of 350 to 500 ° C. It is a thing. Hereinafter, it explains in detail using a drawing.

FIG. 3 illustrates the manufacturing method described in Patent Document 1, wherein 1 is a p-type Si substrate, 2 is a LOCOS isolation insulating film, 3a and 3b are n + source / drain diffusion layers, and 4 is Gate oxide Si, 5 is a gate polycrystalline Si electrode, 6 is an interlayer insulating film, 7 is a capacitor lower electrode (Pt / Ti), 8 is a ferroelectric (SrBi ₂ Ta ₂ O ₉ ), 9 is a capacitor upper electrode (Pt ) 10 is a capacity protection film (lower layer: sputtered oxidation Si or SOG), 11 is a capacity protection film (upper layer: ozone oxidation TEOS film), 12a and 12b are contact holes to the transistor source / drain diffusion layers 3a and 3b, 13a 13b are contact holes for the capacitor upper and lower electrodes 9 and 7, 14a and 14b are metal wirings to the transistor source / drain diffusion layers 3a and 3b, and 15a and 15b are metal wirings to the capacitor upper and lower electrodes 9 and 7. It is.

  In the prior art described in Patent Document 1 shown in FIG. 3, the protective films 10 and 11 which are in contact with and cover the ferroelectric 8 as shown in the figure have a two-layer structure, and the lower layer film 10 is formed by sputtering other than the CVD method. Or an SOG (Spin On Glass) film formation, and an Si oxide film using TEOS as a raw material is formed thereon as an upper layer film 11 at a substrate temperature of 350 to 500 ° C., and then the protective film is heat-treated at a high temperature. To do.

  By adopting such a two-layer structure, it is possible to prevent a short circuit failure of the metal wiring layer without causing the reaction product to directly affect the ferroelectric during CVD, and to reduce moisture in the film after film formation. The film formation rate can be reduced and the polarization characteristic can be prevented from being deteriorated. Further, the leakage current characteristic can be improved by further heat treatment after the film formation.

However, since the heat treatment time for crystallizing the ferroelectric 8 is long in the conventional device described in Patent Document 1 above, and depending on the type of the ferroelectric 8, the heat treatment temperature is high. There is a possibility that the moisture characteristics and the polarization characteristics of the ferroelectric 8 may deteriorate due to the presence of moisture and hydrogen. Furthermore, when an oxide conductive material is used for the electrode of the capacitor, the oxide conductive material is reduced by performing high-temperature heat treatment. For this reason, the oxygen barrier property is lost and the lower electrode 7 is peeled off.
JP-A-9-307074 (FIG. 1, paragraphs 0014 to 0021 of the specification)

  The present invention solves the above problems in the prior art, removes moisture in the oxide film and completely prevents moisture in the atmosphere from directly attaching to the ferroelectric after crystallization, It is another object of the present invention to provide a method for manufacturing a semiconductor device in which reduction of a conductive oxide used as a lower electrode is completely prevented.

In order to solve the above-described problems, the present invention provides a process of forming a capacitor by sequentially forming a lower electrode, a ferroelectric or high-dielectric capacitor insulating film, and an upper electrode on a semiconductor substrate, and covering the capacitor. Forming an oxide film serving as an interlayer insulating film on the substrate, and forming an oxide film serving as the interlayer insulating film, followed by rapid thermal processing in an oxygen atmosphere to crystallize the capacitive insulating film made of the ferroelectric or high dielectric. and a step of reduction, the oxide film serving as the interlayer insulating film is to be formed TEOS, thermal CVD method using _{O 3,} or _{O 3} and Al _{(CH 3)} ALCVD method using ₃ .

  According to the present invention, in the above, the lower electrode is preferably an electrode containing a conductive oxide.

According to the invention, in the above, the method further includes the step of forming an upper oxide film on the oxide film to be the interlayer insulating film after forming the oxide film to be the interlayer insulating film, It is preferable to carry out after forming the oxide film to be an insulating film and before forming the upper oxide film .
According to the invention, in the above, it is preferable that the thickness of the oxide film serving as the interlayer insulating film is 200 nm or less.

According to the present invention, in the above, after forming an oxide film as an interlayer insulating film, before performing the rapid heat treatment it is preferable to perform the planarization process to the oxide film serving as the interlayer insulating film is there.

  As described above, according to the present invention, after the oxide film covering the capacitor is formed, the heat treatment for expressing the ferroelectricity by the ferroelectric is performed, and then the ferroelectric is developed. Therefore, it is possible to prevent moisture in the oxide film from being directly contacted with moisture in the atmosphere and to completely prevent moisture in the atmosphere from directly adhering to the ferroelectric after crystallization. Can be prevented.

  In addition, according to the present invention, the oxide film is an insulating film that does not reduce the conductive oxide contained in the lower electrode, and the oxide film thickness during the heat treatment can be controlled to prevent a defect such as electrode peeling. it can.

  Examples of the present invention will be described below.

Embodiments of the present invention will be described below with reference to the drawings.
1A and 1B, an embodiment of a method of manufacturing a semiconductor memory device using a ferroelectric and a high dielectric according to the present invention will be described.

  As shown in FIG. 1- (a), a trench having a depth of about 300 nm is formed on a semiconductor substrate 100 using a dry etching method, and then a silicon oxide film is deposited by a CVD method. Then, the device isolation region 101 is formed by planarization. Next, after forming a gate insulating film having a thickness of about 10 nm, a polysilicon film having a thickness of about 200 nm is deposited, and the gate electrode 102 is formed by using a dry etching method. Next, a diffusion layer 103 is formed by ion implantation in a region adjacent to the gate electrode 102 in the semiconductor substrate 100 and a peripheral region thereof to form a MOS transistor.

  Next, as shown in FIG. 1-A (b), a first silicon oxide film 104 is formed on the MOS transistor formed as described above and its peripheral region, and the film thickness is increased on the gate electrode 102. It planarizes so that it may become about 200 nm. Next, after forming a contact hole 120 reaching the diffusion layer 103 in the first silicon oxide film 104, about 10 nm of titanium, about 20 nm of titanium nitride, and 300 nm of tungsten are sequentially deposited by the CVD method to form the contact hole 120. A tungsten plug 105 is formed by embedding and planarizing the surface by CMP. Next, titanium having a film thickness of about 10 nm, titanium nitride having a film thickness of about 20 nm, and tungsten having a film thickness of about 100 nm are sequentially deposited by a sputtering method, and dried on a predetermined region including the top of the tungsten plug 105 on the first silicon 104. Bit line 106 is formed by an etching method.

  Next, after depositing a second silicon oxide film 107 on the first silicon oxide film 104 using the CVD method so as to cover the bit line 106, as shown in FIG. Planarization is performed by CMP so that the thickness on the bit line 106 becomes 100 nm. Next, an insulating lower hydrogen barrier made of the silicon nitride film 108 having a thickness of about 100 nm is formed on the second silicon oxide film 107 by the CVD method. Next, a contact hole 121 that reaches the diffusion layer 103 through the silicon nitride film 108, the second silicon oxide film 107, and the first silicon oxide film 104 is formed by dry etching. Next, about 10 nm of titanium, about 20 nm of titanium nitride, and 300 nm of tungsten are sequentially deposited by the CVD method to fill the contact hole 121, and then the surface is planarized by the CMP method to form the tungsten plug 109.

  Next, as shown in FIG. 1A (d), on the silicon nitride film 108 and the tungsten plug 109, titanium aluminum nitride (TiAlN) with a film thickness of about 50 nm, iridium (Ir) with a film thickness of about 50 nm, conductive An iridium oxide (IrOx) film having a film thickness of about 50 nm and platinum (Pt) film having a film thickness of about 100 nm are sequentially deposited by sputtering, and patterned to cover the surface of the tungsten plug 109 by dry etching, A lower electrode 110 made of a conductive oxide is formed.

  Next, as shown in FIG. 1-B (e), a third silicon oxide film 111 is deposited on the silicon nitride film 108 using the CVD method so as to cover the lower electrode 110, and the surface of the lower electrode 110 is formed. Planarization is performed by CMP so as to be exposed. Next, a ferroelectric substance having a film thickness of about 100 nm and made of a bismuth layered perovskite oxide containing strontium, bismuth, tantalum, and niobium as a component is deposited using a coating method. Thereafter, preliminary sintering is performed in an oxygen atmosphere at 650 ° C. Next, Pt with a film thickness of about 100 nm is deposited by sputtering. Next, the ferroelectric and Pt are patterned in a region including the lower electrode 110 using dry etching, thereby forming a capacitive insulating film 112 made of ferroelectric and an upper electrode 113 made of Pt. The capacitor structure is used.

Next, as shown in FIG. 1-B (f), the first electrode having a film thickness of about 150 nm is formed on the upper electrode 113 by using, for example, a thermal CVD method in which TEOS and O ₃ are main components of the source gas. An oxide film 114 is deposited. In this method, unlike the known plasma CVD method, generation of hydrogen for reducing oxides can be suppressed and the concentration of hydrogen contained in the film can be reduced. Next, a rapid heat treatment is performed under an rapid condition of 1 minute at 800 ° C. in an oxygen atmosphere to crystallize the ferroelectric of the capacitor insulating film 112. Thereafter, a second oxide film 115 is deposited by using the same method as that for the first oxide film 114, and planarization is performed. Alternatively, an ALCVD (Atomic Layer CVD) method using O ₃ and Al (CH ₃ ) ₃ as main components may be used as the first and second oxide films 114 and 115. This method can also reduce the hydrogen generated in the process and the hydrogen content in the film.

  As described above, the first oxide film 114 is deposited, the ferroelectric of the capacitor insulating film 112 is crystallized by rapid thermal processing, and then the second oxide film 115 is further deposited and planarized. As a result, it is possible to realize step relief that is a problem in the formation of wiring in a subsequent process without deteriorating the capacitor insulating film.

  Note that, as shown in FIG. 1B (g), the first oxide film 114 may be deposited thickly and planarized, and then a rapid thermal process for crystallizing the ferroelectric may be performed.

  By doing so, it is possible to remove moisture in the first oxide film 114 and completely prevent moisture in the atmosphere from directly attaching to the ferroelectric 112 after crystallization.

  Next, the thickness of the first oxide film 114 will be described. FIG. 2 shows the relationship between the thickness of the sample and the amount of polarization when the RTO treatment is performed after depositing the first oxide film 114 with a thickness of 50 nm to 450 nm on the upper electrode 113 formed of Pt. Show. As can be seen from FIG. 2, the polarization amount was hardly observed when the film thickness was 300 nm or more. Further, when the cross section of this sample was observed, peeling was observed at the interface between TiAlN and Ir of the lower electrode 110, and the film thickness of IrOx was reduced. From this result, it is considered that when oxygen does not reach the surface of IrOx to some extent during the RTO treatment, a reduction reaction of IrOx occurs, and the oxygen reacts with the TiAlN surface to form an oxide layer, which causes peeling. Therefore, by setting the thickness of the first oxide film 114 to 200 nm or less, it is possible to prevent a defect such as peeling of the lower electrode 110 and to suppress deterioration of the ferroelectric capacitance due to adhesion of moisture in the atmosphere. Guessed.

  The method for manufacturing a semiconductor device of the present invention can be used for manufacturing a semiconductor device having a capacitive insulating film using a ferroelectric film or a high dielectric film.

Sectional drawing which shows the Example of the manufacturing method of the semiconductor device of this invention Sectional drawing which shows the next process of FIG. 1-A The figure which shows the relationship between the film thickness of the oxide film on an upper electrode (platinum), and the amount of polarization in the Example of the manufacturing method of the semiconductor device of this invention Cross-sectional view of relevant parts showing a conventional method for manufacturing a semiconductor device

Explanation of symbols

100 Semiconductor substrate 110 Lower electrode (Pt / IrOx / Ir / TiAlN)
112 Capacitance insulation film (ferroelectric)
113 Upper electrode (Pt)
114 first oxide film 115 second oxide film

Claims (5)

Forming a capacitor by sequentially forming a lower electrode, a capacitor dielectric film made of a ferroelectric or a high dielectric, and an upper electrode on a semiconductor substrate; and
Forming an oxide film to be an interlayer insulating film so as to cover the capacitor;
A step of performing a rapid heat treatment in an oxygen atmosphere after forming the oxide film to be the interlayer insulating film, and crystallizing the capacitive insulating film made of the ferroelectric or high dielectric,
The oxide film to be the interlayer insulating film is formed by a thermal CVD method using TEOS, O ₃ or an ALCVD method using O ₃ and Al (CH ₃ ) _3. .   The method of manufacturing a semiconductor device according to claim 1, wherein the lower electrode is an electrode containing a conductive oxide. A step of forming an upper oxide film on the oxide film to be the interlayer insulating film after forming the oxide film to be the interlayer insulating film;
3. The method of manufacturing a semiconductor device according to claim 1 , wherein the rapid thermal processing is performed after forming an oxide film to be the interlayer insulating film and before forming the upper oxide film . 4. The method of manufacturing a semiconductor device according to claim 1, wherein a film thickness of the oxide film serving as the interlayer insulating film is set to 200 nm or less . 5. 5. The planarization process is performed on the oxide film to be the interlayer insulating film after the oxide film to be the interlayer insulating film is formed and before the rapid thermal processing is performed. A method for manufacturing a semiconductor device according to claim 1.

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