JP5832715B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment.

  In recent years, with the advancement of digital technology, there is an increasing demand for electronic devices such as mobile phones to process and store large volumes of data at high speed. Known nonvolatile memories for storing data include DRAM (Dynamic Random Access Memory) and FeRAM (Ferroelectric Random Access Memory).

  Among these, the FeRAM has a ferroelectric capacitor in which a ferroelectric film is formed as a capacitor dielectric film, and stores information by utilizing the spontaneous polarization of the ferroelectric film. This is advantageous in that the operating voltage is low compared to the above, and high-speed operation is possible.

In the FeRAM, an oxide ferroelectric such as PZT (Pb (Zr, Ti) O ₃ ) is often used as a material for the capacitor dielectric film.

  However, it is known that oxide ferroelectrics cause oxygen vacancies due to the reducing action of hydrogen in the external atmosphere, and thereby ferroelectric properties such as residual polarization charge amount easily deteriorate.

  In order to prevent such deterioration, an alumina film or a silicon nitride film is formed as a hydrogen barrier film above the ferroelectric capacitor to prevent hydrogen in the external atmosphere from reaching the ferroelectric capacitor. Proposed.

There has also been proposed a method for recovering ferroelectric characteristics by compensating for oxygen deficiency in the ferroelectric film by annealing the ferroelectric film in an oxygen-containing atmosphere.
JP 2005-268617 A JP 2002-289793 A JP 2004-22553 A JP 2001-15703 A JP 2003-197878 A JP 2006-165128 A JP 2003-332536 A JP 2005-183843 A JP 2002-176149 A JP-A-8-17760 JP 2006-344676 A JP 2001-250792 A JP 2002-324855 A JP 2003-133534 A JP-A-6-21391

The method of manufacturing a semiconductor equipment, and to prevent the deterioration of the capacitor having a ferroelectric film.

According to one aspect of the following disclosure, a capacitor having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film above a semiconductor substrate Forming an insulating film on the capacitor, forming a hole reaching the upper electrode in the insulating film, an inner surface of the hole, and the upper electrode exposed from the hole It has a conductivity to the surface, forming a first barrier film including a titanium nitride, the first barrier film, the process of exposing to the atmosphere, or, said in the mixed gas of nitrogen gas and oxygen gas by the heat treatment of the flow rate ratio of the oxygen gas in an atmosphere that is 1% or less, on the first barrier film, the high oxygen concentration than the first barrier film, have a conductivity, acid form a second barrier film including a titanium nitride A step of, on the second barrier layer, wherein the lower oxygen concentration than the second barrier film, have a conductivity, and forming a third barrier film containing titanium nitride, the third forming a conductive film on the barrier film, seen including a step of filling the hole, the first barrier layer, the second barrier film and the third barrier film, a barrier to hydrogen or fluorine A method of manufacturing a semiconductor device that is a film is provided.

  According to the disclosed semiconductor device and the manufacturing method thereof, the oxygen concentration of the second barrier film is made higher than that of the first barrier film. Oxygen in the film has a function of improving the barrier property of the second barrier film against hydrogen, halogen, etc., so that it is easy for the second barrier film to prevent these elements from entering the capacitor. It is possible to prevent the capacitor from deteriorating due to the element.

(1) Investigation Results Prior to the description of the embodiments, the investigation results conducted by the inventor will be described.

  1 to 4 are cross-sectional views showing a method of manufacturing a ferroelectric capacitor sample used in the investigation.

  In order to produce this sample, first, as shown in FIG. 1A, a silicon oxide film is formed as a first interlayer insulating film 2 above the silicon substrate 1 by a CVD method.

  Then, an alumina film having a thickness of 70 nm is formed as an adhesion film 3 on the first interlayer insulating film 2 by sputtering, and then the first conductive film 4, the ferroelectric film 5, and the first film are formed thereon. Two conductive films 6 are formed in this order by sputtering.

Among them, a platinum film having a thickness of 150 nm is formed as the first conductive film 4, and a PZT (Pb (Zr, Ti) O ₃ ) film having a thickness of 90 nm is formed as the ferroelectric film 5. . Then, as the second conductive film 6, a iridium oxide film having a two-layer structure in which the lower layer is 50 nm and the upper layer is 200 nm thick is formed. Note that crystallization annealing for crystallizing the ferroelectric film 5 is performed after the lower layer of the second conductive film 6 is formed.

  Next, as shown in FIG. 1B, each of the films 3 to 6 is patterned, and a ferroelectric capacitor Q is formed by laminating the lower electrode 4a, the capacitor dielectric film 5a, and the upper electrode 6a in this order. Form.

  Subsequently, as shown in FIG. 2A, a first alumina film having a thickness of 20 nm is formed on the entire upper surface of the silicon substrate 1 by sputtering.

  Further, a silicon oxide film having a thickness of about 1400 nm is formed on the first alumina film 7 as the second interlayer insulating film 8 by the CVD method, and then the surface is polished by the CMP (Chemical Mechanical Polishing) method. And flatten.

  Then, a second alumina film 9 having a thickness of 20 to 50 nm is formed on the second interlayer insulating film 8 planarized in this manner by sputtering. Then, a silicon oxide film having a thickness of 20 to 50 nm is formed on the second alumina film 9 by the CVD method, and this is used as a cap insulating film 10.

  Of the films formed in this manner, the first and second alumina films 7 and 9 prevent hydrogen in the external atmosphere from reaching the capacitor dielectric film 5a, and the capacitor dielectric due to reduction by hydrogen. It plays a role of preventing the body membrane 5a from deteriorating.

  Next, as shown in FIG. 2B, the films 7 to 10 are patterned by photolithography and etching to form first and second holes 8a and 8b on the lower electrode 4a and the upper electrode 6a, respectively. To do.

  Then, as shown in FIG. 3A, a titanium nitride film is sputtered to a thickness of about 300 nm as a barrier film 12 serving as a tungsten growth nucleus on the inner surfaces of the holes 8a and 8b and the upper surface of the cap insulating film 10. Form by law.

Thereafter, as shown in FIG. 3B, a tungsten film 13 is formed on the barrier film 12, and the holes 8a and 8b are completely filled with the tungsten film 13. The tungsten film 13 is formed by, for example, a CVD method using a mixed gas of tungsten hexafluoride (WF ₆ ) gas and hydrogen gas as a reaction gas.

  Then, as shown in FIG. 4, the excess barrier film 12 and the tungsten film 13 on the cap insulating film 10 are removed by polishing by the CMP method, and these films are conductive only in the holes 8a and 8b. Leave as plug 15.

  Thereby, a write signal and a read signal to the capacitor Q can be applied to the lower electrode 4a and the upper electrode 6a through the conductive plug 15, respectively.

  The basic structure of this sample was completed through the steps so far.

  As described with reference to FIG. 3B, in this sample, the barrier film 12 is formed as a growth nucleus of the tungsten film 13. Since hydrogen gas is used when forming the tungsten film 13, the barrier film 12 is also required to play a role of blocking the hydrogen so that the capacitor dielectric film 5a is not reduced by hydrogen.

  However, if foreign matter adheres on the upper electrode 6a, the barrier film 12 is formed on the foreign matter, and therefore the barrier film 12 is insufficient on the foreign matter. The hydrogen barrier property will be reduced.

  As a source of such foreign matter, for example, there is an etching mask when the upper electrode 6a is formed by patterning the second conductive film 6 (FIG. 1B). As the etching mask, a hard mask such as a titanium nitride film that can withstand the sputtering effect during etching is used. When the hard mask is removed by wet processing or dry etching, small foreign matters having a size of 0.2 μm or less may remain on the upper electrode 6a.

  Even when a resist pattern is used as the etching mask, foreign matter may remain on the upper electrode 6a to some extent.

  FIG. 5 is a wafer map obtained by inspecting the sample with a defect inspection apparatus, and a defect is generated at a circled portion.

  FIG. 6 is a planar image obtained by observing one of the defects with a scanning electron microscope (SEM). As shown in this, a film bulge 17 is generated at a site where a defect is observed.

  FIG. 7 is a diagram in which a cross section of a portion where the bulge 17 is present is observed with a TEM (Transmission Electron Microscope) and drawn based on the observation.

  As shown in the figure, a cavity S is generated in the upper electrode 6a in the portion where the bulge is present. In the cavity S, the hydrogen barrier property of the barrier film 12 is deteriorated by the foreign matter as described above, so that when the tungsten film 13 is formed (FIG. 3B), hydrogen passes through the barrier film 12 and is It is considered that the iridium oxide in the upper electrode 6a was formed by reduction.

  Further, when forming the tungsten film 13, tungsten hexafluoride gas is also used, so that the fluorine S permeates the barrier film 12 and the upper electrode 6a is eroded by the highly reactive fluorine, so that the cavity S is generated. It is also considered.

  When the cavity S is generated in this manner, the contact resistance between the conductive plug 15 and the upper electrode 6a increases, and the yield of the semiconductor device decreases.

  Further, the capacitor dielectric film 5a is reduced by hydrogen which is the cause of the generation of the cavity S, and the ferroelectric characteristics of the capacitor dielectric film 5a such as the residual polarization charge amount may be deteriorated. For this reason, the retention characteristic, which is the information retention characteristic of the capacitor Q, is lowered, and the reliability of the semiconductor device is lowered.

  Therefore, in order to prevent such a decrease in the yield and retention characteristics of the semiconductor device, the barrier film 12 on the ferroelectric capacitor Q is required to have a high barrier property against hydrogen or the like.

  The inventor of the present application has come up with an embodiment described below based on such knowledge.

(2) First Embodiment FIGS. 8 to 23 are cross-sectional views in the course of manufacturing a semiconductor device according to the first embodiment.

  This semiconductor device is a planar-type FeRAM and is manufactured as follows.

  First, steps required until a sectional structure shown in FIG.

  First, a trench for element isolation is formed in an n-type or p-type silicon (semiconductor) substrate 30. Then, an element isolation insulating film 31 is formed in the trench, and the element isolation insulating film 31 defines an active region of the transistor. Such an element isolation structure is called STI (Shallow Trench Isolation), but LOCOS (Local Oxidation of Silicon) may be adopted instead.

  Next, a p-type impurity such as boron is introduced into the active region of the silicon substrate 30 to form a p-well 32, and then the surface of the active region is thermally oxidized to form a thermal oxide film serving as the gate insulating film 33 with about 6 pieces. Form a thickness of ˜7 nm.

  Subsequently, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are sequentially formed on the entire upper surface of the silicon substrate 30. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film. Thereafter, these films are patterned by photolithography and etching to form the gate electrode 34 on the silicon substrate 30.

  On the p-well 32, two gate electrodes 34 are arranged substantially in parallel with a space therebetween, each of which becomes a part of a word line.

  Next, phosphorus is introduced as an n-type impurity into the silicon substrate 30 beside the gate electrode 34 by ion implantation using the gate electrode 34 as a mask to form first and second source / drain extensions 35a and 35b.

  Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 30, and the insulating film is etched back to leave an insulating spacer 37 beside the gate electrode 34. As the insulating film, a silicon oxide film is formed by, for example, a CVD method.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the silicon substrate 30 while using the insulating spacers 37 and the gate electrode 34 as a mask, so that the first and second silicon substrates 30 on the side of the gate electrode 34 are first and second-implanted. Two source / drain regions 36a and 36b are formed. Among these, the second source / drain region 36b between the two gate electrodes 34 becomes a part of the bit line.

  Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 30 by sputtering. Then, the refractory metal film is heated and reacted with silicon to form a refractory silicide layer 38 such as a cobalt silicide layer on the silicon substrate 30 in the first and second source / drain regions 36a and 36b. The resistance of each source / drain region 36a, 36b is reduced. Such a refractory metal silicide layer is also formed on the surface layer of the gate electrode 34.

  Thereafter, the refractory metal layer which has not reacted on the element isolation insulating film 31 or the like is removed by wet etching.

  Through the steps so far, the MOS transistor TR having the gate insulating film 33, the gate electrode 34, the first and second source / drain regions 36a, 36b, and the like is formed in the active region of the silicon substrate 30. .

  Next, as shown in FIG. 8B, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 30 by plasma CVD, and this is used as a cover insulating film 41.

Further, a silicon oxide (SiO ₂ ) film having a thickness of about 1000 nm is formed on the cover insulating film 41 as a first interlayer insulating film 42 by plasma CVD using a TEOS (Tetraethoxysilane) gas. Then, the upper surface of the first interlayer insulating film 42 is polished and planarized by the CMP method, and the thickness of the first interlayer insulating film 42 is set to about 785 nm.

  Subsequently, as shown in FIG. 8C, the cover insulating film 41 and the first interlayer insulating film 42 are patterned by photolithography and etching, and are formed on the first and second source / drain regions 36a and 36b. A contact hole 42a is formed.

  Thereafter, as shown in FIG. 9A, first conductive plugs 43 electrically connected to the first and second source / drain regions 36a, 36 are formed in these contact holes 42a.

  In order to form the first conductive plug 43, for example, a titanium film having a thickness of about 30 nm and a titanium nitride film having a thickness of about 20 nm are formed as barrier films in this order in the contact hole 42a by the sputtering method. To do. Then, a tungsten film is formed to a thickness of about 300 nm on this barrier film by the CVD method, and the contact hole 42a is completely buried with this tungsten film. Thereafter, the excess barrier film and the tungsten film on the first interlayer insulating film 42 are removed by polishing by the CMP method, and these films are left in the contact holes 42 a as the first conductive plugs 43.

  Since the first conductive plug 43 formed in this way is mainly made of tungsten that is easily oxidized, there is a possibility that it will be easily oxidized in an oxygen-containing atmosphere and cause contact failure.

  Therefore, in the next step, as shown in FIG. 9B, the first conductive plug 43 and the first interlayer insulating film 42 are used as an anti-oxidation insulating film 45 for preventing the oxidation of the first conductive plug 43. A silicon oxynitride film having a thickness of about 100 nm is formed on each of these by CVD.

  Then, a silicon oxide film having a thickness of about 130 nm is formed on the oxidation-preventing insulating film 45 by a CVD method using TEOS gas, and this silicon oxide film is used as the insulating adhesion film 46.

  Thereafter, the insulating adhesive film 46 is degassed by annealing the insulating adhesive film 46 for 30 minutes in a nitrogen atmosphere at a substrate temperature of about 650 ° C.

  Next, as shown in FIG. 9C, an alumina film having a thickness of about 20 nm is formed on the insulating adhesion film 46 as a lower electrode adhesion film 47 by sputtering. Thereafter, the alumina of the lower electrode adhesion film 47 is sufficiently oxidized by RTA (Rapid Thermal Anneal). The lower electrode adhesion film 47 is formed in order to improve adhesion between a capacitor lower electrode, which will be described later, and the insulating adhesion film 46.

Subsequently, as shown in FIG. 10A, a platinum film having a thickness of about 150 nm is formed as the first conductive film 48 by sputtering. Instead of the platinum film, a single layer film of any one of an iridium film, a ruthenium film, a ruthenium oxide (RuO ₂ ) film, and a SrRuO ₃ film, or a laminated film thereof is formed as the first conductive film 48. Also good.

  Here, since the lower electrode adhesion film 47 is formed in advance before the first conductive film 48 is formed, the adhesion between the first conductive film 48 and the insulating adhesion film 46 is enhanced.

Next, as shown in FIG. 10B, PZT (Pb (Zr _{x) is formed} as a first ferroelectric film 49 on the first conductive film 48 by RF (Radio Frequency) sputtering using a PZT target. , Ti _1-x ) O ₃ : 0 ≦ x ≦ 1) film is formed to a thickness of about 90 nm.

  The deposition temperature of the first ferroelectric film 49 is not particularly limited. However, when the film forming temperature is 150 ° C. or higher, the orientation of PZT in the first ferroelectric film 49 after crystallization annealing described later is randomly oriented in the (101) direction, etc. The orientation in the (111) direction, which is advantageous for improvement, may decrease. On the other hand, it is difficult to accurately control the film formation temperature at a low temperature. In view of these, the deposition temperature of the first ferroelectric film 49 is preferably 0 ° C. to 150 ° C., for example, 50 ° C.

Further, the first ferroelectric film 49 is not limited to the PZT film. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the first ferroelectric film 49. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the first ferroelectric film 49.

  Further, the method for forming the first ferroelectric film 49 is not limited to the sputtering method, and the first ferroelectric film 49 may be formed by a sol-gel method or a MOCVD (Metal Organic CVD) method.

  Among these film formation methods, the first ferroelectric film 49 formed by sputtering is not crystallized immediately after the film formation and is amorphous and has poor ferroelectric properties.

  Therefore, in the next step, as shown in FIG. 11A, crystallization annealing is performed on the first ferroelectric film 49 in an oxygen-containing atmosphere, and PZT in the first ferroelectric film 49 is changed. Crystallize.

  The crystallization annealing is performed by RTA in an atmosphere of oxygen and argon adjusted so that the oxygen concentration is 1.25%, the substrate temperature is about 600 ° C., and the processing time is about 90 seconds. .

  In the case where the first ferroelectric film 49 is formed by the MOCVD method, the first ferroelectric film 49 is crystallized at the time of film formation, and thus the above crystallization annealing is not necessary.

  Thereafter, as shown in FIG. 11B, a PZT film is formed to a thickness of about 10 to 30 nm on the first ferroelectric film 49 by RF sputtering, and this PZT film is formed into the second ferroelectric film. The body membrane 50 is used.

The second ferroelectric film 50 is not limited to a PZT film. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the second ferroelectric film 50. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the second ferroelectric film 50.

  Note that PZT formed by sputtering is not crystallized immediately after film formation. Therefore, at this time, the second ferroelectric film 50 is in an amorphous state.

  Next, as shown in FIG. 12A, a second conductive film 51 for the upper electrode is formed on the amorphous second ferroelectric film 50 by sputtering.

  As the second conductive film 51, for example, an iridium oxide film having a thickness of about 50 nm can be formed by sputtering an iridium target in a mixed atmosphere of argon gas and oxygen gas.

  Subsequently, as shown in FIG. 12B, crystallization annealing is performed on the amorphous second ferroelectric film 50 in an oxygen-containing atmosphere, so that PZT in the second ferroelectric film 50 is obtained. Is crystallized, and the crystallinity of the first ferroelectric film 49 thereunder is further enhanced.

  The conditions for this crystallization annealing are not particularly limited, but in this embodiment, the substrate temperature is about 710 ° C. and the processing time is 120 seconds. Furthermore, as the annealing atmosphere, a mixed atmosphere of oxygen gas and argon gas whose oxygen concentration is adjusted to 1% by flow rate ratio is used.

  Since the second ferroelectric film 50 is not crystallized and is amorphous at the initial stage of the crystallization annealing, iridium oxide of the second conductive film 51 becomes a grain boundary of the second ferroelectric film 50. Difficult to spread. Thereby, it is possible to suppress the occurrence of a leak path in the second ferroelectric film 50 due to the diffused iridium oxide.

  Furthermore, this crystallization annealing also provides an advantage that oxygen in the annealing atmosphere is supplied to the second ferroelectric film 50 through the second conductive film 51, and oxygen vacancies in the second ferroelectric film 50 are compensated. can get. In order to obtain such advantages, the thickness of the second conductive film 51 is preferably as thin as possible so that oxygen can easily permeate, for example, 10 to 100 nm.

  However, if the thin second conductive film 51 is formed on the second ferroelectric film 50 in this way, damage in the subsequent etching process cannot be absorbed by the second conductive film 51 alone, and the first In addition, the second ferroelectric films 49 and 50 may be deteriorated.

  Therefore, in the next step, as shown in FIG. 13A, a conductive protective film 52 for protecting the first and second ferroelectric films 49 and 50 is formed on the second conductive film 51. Then, an iridium oxide film having a thickness of about 200 nm is formed by sputtering.

  Thereafter, the PZT adhering to the back surface of the silicon substrate 30 when the first and second ferroelectric films 49 and 50 are formed is cleaned and removed.

  Subsequently, as shown in FIG. 13B, a titanium nitride film having a thickness of about 34 nm is formed on the conductive protective film 52 as a hard mask 53 by sputtering.

  This titanium nitride film can be formed, for example, by sputtering a titanium target in a mixed atmosphere of argon gas having a substrate temperature of 200 ° C. and a flow rate of 30 sccm and a nitrogen gas having a flow rate of 90 nm.

  The hard mask 53 is not limited to a titanium nitride film, and a hard film made of any of TaN, TiON, TiOx, TaOx, TaON, TiAlOx, TaAlOx, TiAlON, TaAlON, TiSiON, TaSiON, TiSiOx, AlOx, and ZrOx is hard. A mask 53 may be formed.

  Thereafter, a photoresist is applied on the hard mask 53, and is exposed and developed to form a first resist pattern 57.

  Next, as shown in FIG. 14A, the hard mask 53 is patterned in an island shape using the first resist pattern 57 as a mask.

  Then, as shown in FIG. 14B, the second conductive film 51 and the conductive protective film 52 are dry-etched using the island-like hard mask 53 as a mask, and these films 51 remaining without being etched. , 52 are upper electrodes 63.

  Here, the side surface of the first resist pattern 57 may recede due to damage during etching. On the other hand, since the hard mask 53 is made of a material whose etching rate is slower than that of the resist such as titanium nitride, the side surface of the hard mask 53 does not recede and the upper electrode 63 can be easily patterned to the designed dimensions.

  Thereafter, the first resist pattern 57 is removed, and the hard mask 53 is further removed by dry etching.

  At this time, an etching product at the time of forming the upper electrode 63 is attached to the side surface of the first resist pattern 57 in a fence shape. However, since the etching product is removed together with the hard mask 53, the upper electrode is removed. Etching products can be prevented from remaining as foreign matter on 63.

  Next, as shown in FIG. 15A, in order to recover the damage received by the first and second ferroelectric films 49 and 50 in the steps so far, the ferroelectric films 49 and 50 are formed on the ferroelectric films 49 and 50, respectively. On the other hand, annealing is performed in an oxygen-containing atmosphere.

  Such annealing is called recovery annealing, and in this embodiment is performed at a substrate temperature of 600 to 700 ° C., for example, 650 ° C., for about 40 minutes.

  Next, as shown in FIG. 15B, a photoresist is applied to the entire upper surface of the silicon substrate 30, and is exposed and developed to form a second resist pattern 58.

  Then, as shown in FIG. 16A, the first and second ferroelectric films 49 and 50 are dry-etched using the second resist pattern 58 as a mask. As a result, a capacitor dielectric film 62 having these ferroelectric films 49 and 50 is formed under the upper electrode 63.

  Thereafter, the second resist pattern 58 is removed.

  Note that recovery annealing may be performed on the capacitor dielectric film 62 after the second resist pattern 58 is removed. The recovery annealing is performed in an oxygen-containing atmosphere at a substrate temperature of 300 to 400 ° C. and a processing time of 30 to 120 minutes.

  Next, as shown in FIG. 16B, a first alumina film 65 is deposited on each of the first conductive film 48, the capacitor dielectric film 62, and the upper electrode 63 by a CVD method or a sputtering method to a thickness of 20 to 50 nm. It is formed to a thickness of about.

  The first alumina film 65 prevents reducing substances such as hydrogen and moisture from entering the capacitor dielectric film 62, and prevents the capacitor dielectric film 62 from being reduced and deteriorated by these substances. To play a role.

  As a film having such a function, in addition to the alumina film, there are a titanium oxide film, a tantalum oxide film, a zirconium oxide film, an aluminum nitride film, a tantalum nitride film, and an aluminum oxynitride film. Furthermore, nitride films such as a silicon oxynitride film, a silicon nitride film, and a boron nitride film, and a silicon carbide (SiC) film also have a barrier property against hydrogen. Therefore, instead of the first alumina film 65, any one of the above films may be formed. The same applies to the second and third alumina films and the embodiments described later.

  Then, recovery annealing is performed on the capacitor dielectric film 62 at a substrate temperature of 400 to 600 ° C. and a processing time of about 30 to 120 minutes in an oxygen-containing atmosphere.

  Thereafter, a photoresist is applied on the first alumina film 65, and is exposed and developed to form a third resist pattern 66.

  Next, as shown in FIG. 17A, the first alumina film 65 and the first conductive film 48 are dry-etched using the third resist pattern 66 as a mask, and are formed below the capacitor dielectric film 62. A lower electrode 61 is formed.

  In this dry etching, the portion of the lower electrode adhesion film 47 not covered with the lower electrode 61 is also etched away.

  Then, after removing the third resist pattern 66, recovery annealing is performed on the capacitor dielectric film 62 under conditions of a substrate temperature of 300 to 400 ° C. and a processing time of 30 to 60 minutes.

  Through the steps so far, the ferroelectric capacitor Q having the lower electrode 61, the capacitor dielectric film 62, and the upper electrode 63 is formed in the cell region of the silicon substrate 30.

  Next, as shown in FIG. 17B, a second alumina film 70 having a thickness of about 20 nm is formed on the entire upper surface of the silicon substrate 30 by sputtering or CVD.

  Similar to the first alumina film 65, the second alumina film 70 serves to protect the capacitor dielectric film 62 from reducing substances such as hydrogen and moisture.

  Thereafter, recovery annealing is performed on the capacitor dielectric film 62 under conditions where the substrate temperature is 500 to 700 ° C. and the processing time is 30 to 60 minutes in an oxygen-containing atmosphere. By such recovery annealing, oxygen in the capacitor dielectric film 62 is supplemented by oxygen in the annealing atmosphere, and the ferroelectric characteristics of the capacitor dielectric film 62 are recovered.

  Next, steps required until a sectional structure shown in FIG.

  First, a silicon oxide film having a thickness of about 1400 nm is formed as the second interlayer insulating film 71 on the second alumina film 70 by plasma CVD using TEOS gas.

Then, the upper surface of the second interlayer insulating film 71 is polished and flattened by the CMP method, and then the second interlayer insulating film 71 is dehydrated by N ₂ O plasma treatment or N ₂ plasma treatment, and the upper surface thereof is removed. Nitrid to prevent moisture re-adsorption.

  The conditions for this dehydration treatment are not particularly limited, but for example, the substrate temperature is about 350 ° C. and the treatment time is about 2 minutes.

  Next, in order to protect the capacitor dielectric film 62 from a reducing substance such as hydrogen, a third alumina 72 is formed on the second interlayer insulating film 71 to a thickness of about 20 to 150 nm by sputtering or CVD. To do. The reason why the lower limit of the thickness is set to 20 nm is that if it is thinner than this, the barrier property of hydrogen is lowered. Further, the upper limit of the thickness is set to 150 nm because if it is thicker than this, it becomes difficult to form holes in the third alumina film 72 which is difficult to etch in a later step.

  Thereafter, a silicon oxide film having a thickness of about 20 to 50 nm is formed on the third alumina film 72 by a plasma CVD method using TEOS gas, and this silicon oxide film is used as a cap insulating film 73.

  Next, as shown in FIG. 18B, a photoresist is applied on the cap insulating film 73, and it is exposed and developed to form a fourth resist pattern 59.

Then, each of the insulating films 65 and 70 to 73 on the capacitor Q is dry-etched through the window 59a provided in the fourth resist pattern 59, whereby the first and second electrodes reaching the upper electrode 63 and the lower electrode 61, respectively. Holes 71a and 71b are formed. The etching gas used in this step is not particularly limited, but in this embodiment, a mixed gas of C ₄ F ₈ , Ar, O ₂ , and CO is used.

  Thereafter, the fourth resist pattern 59 used for the etching mask is removed.

  Note that, after removing the fourth resist pattern 59, foreign matters on the surface of the cap insulating film 73 and the inner surfaces of the holes 71a and 71b may be removed by brush scrubber processing.

  Next, as shown in FIG. 19A, a photoresist is applied again on the cap insulating film 73, and it is exposed and developed to form a fifth resist pattern 60.

  Then, the insulating films 46 and 70 to 73 are dry-etched through the window 60a of the fifth resist pattern 60 to form a third hole 71c on the first conductive plug.

In this etching, for example, a mixed gas of C ₄ F ₈ , Ar, O ₂ and CO is used as an etching gas. Since the antioxidant insulating film 45 serves as an etching stopper for the etching gas, the antioxidant insulating film 45 remains on the first conductive plug 43 without being etched.

  Thereafter, the fifth resist pattern 60 is removed.

  Note that after the fifth resist pattern 60 is removed, recovery annealing may be performed on the capacitor dielectric film 62 in an oxygen-containing atmosphere. The recovery annealing is performed, for example, under conditions of a substrate temperature of 400 to 600 ° C. and a processing time of 30 to 120 minutes. Even if annealing is performed in an oxygen-containing atmosphere in this manner, the oxidation-preventing insulating film 45 on the first conductive plug 43 blocks oxygen transmission, so that contact is caused by oxidation of the first conductive plug 43. It will not be bad.

  Note that this recovery annealing may be performed in an ozone atmosphere instead of the oxygen-containing atmosphere.

  Subsequently, as shown in FIG. 19B, the anti-oxidation insulating film 45 remaining under the third hole 71c is etched and removed by sputter etching using argon gas, and the first conductive plug 43 is removed. Expose the clean surface. Foreign substances in the holes 71a and 71b on the capacitor Q can be removed by such sputter etching.

  Next, steps required until a sectional structure shown in FIG.

  First, the second interlayer insulating film 71 is annealed and degassed in an inert gas atmosphere or a reduced pressure atmosphere.

  Then, the entire upper surface of the silicon substrate 30 is etched by about 10 nm by RF etching using argon plasma, and the natural oxide film on the upper surface of the first conductive plug 43 is removed.

  Next, titanium nitride (TiN) is formed by sputtering as a conductive first barrier film 67 on the inner surfaces of the first to third holes 71a to 71c and the surfaces of the upper electrode 63 and the lower electrode 61 exposed from the holes 71b and 71c, respectively. ) Form a film.

  Here, the third hole 71c on the first conductive plug 43 has a higher aspect ratio than the holes 71a and 71b on the capacitor Q. Therefore, it is preferable to form the first barrier film 67 by a sputtering method capable of forming a film with a good coverage in a hole having a high aspect ratio, such as a sputtering method using SIP (Self Ionized Plasma) technology.

  In addition, although the film-forming conditions of the 1st barrier film | membrane 67 are not specifically limited, In this embodiment, argon gas and nitrogen gas are introduce | transduced into the SIP chamber provided with the titanium target, substrate temperature is 150-250 degreeC, For example, the first barrier film 67 is formed at 200 ° C. In this case, the flow rate of each gas is, for example, 50 sccm for argon gas and 90 sccm for nitrogen gas.

  The first barrier film 67 plays a role of preventing hydrogen, fluorine, and the like in the external atmosphere from entering the capacitor Q in addition to the function as a growth nucleus of the conductive film for plug such as a tungsten film.

  In addition to titanium nitride, the material of the film having such a function includes TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, and ZrAlN metal nitrides. Any film may be formed as the first barrier film 67. Further, any one of the metal oxynitrides of TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfAlON, ZrAlON, TiSiON, and TaSiON may be used as the material of the first barrier film 67. Furthermore, a noble metal such as Ir and Ru, or an oxide film of any of IrOx and RuOx may be formed as the first barrier film 67. In addition, a Ti film, a Ta film, and a TiN film that is a nitride film thereof, a Ti / TiN film formed by laminating a TaN film, a Ti / TaN film, a Ta / TiN film, and a Ta / TaN film are either One barrier film 67 may be formed.

  Next, as shown in FIG. 20B, the first barrier film 67 is made of titanium oxynitride (TiON) obtained by natural oxidation of titanium nitride by exposing the first barrier film 67 to the atmosphere and naturally oxidizing the surface thereof. A conductive second barrier film 68 is formed on the first barrier film 67 to a thickness of several angstroms.

  Since oxygen in the film of the second barrier film 68 has a high barrier property against hydrogen, fluorine, etc., the risk that the capacitor Q is exposed to these elements as compared with the case where the first barrier film 67 is used as a single layer. Can be reduced.

  Further, when the second barrier film 68 is formed by natural oxidation in this way, oxygen atoms that cause a reduction in the electrical resistance of the film are not excessively taken into the film, so that the conductivity of the second barrier film 68 is reduced. The property can be kept good.

  In order to prevent such an increase in electrical resistance due to oxygen, it is preferable to form the second barrier 68 with a thickness smaller than that of the first barrier film 67.

  As for the time of natural oxidation, it is preferable to expose the first barrier film 67 to the atmosphere for 5 minutes or more from the viewpoint of surely performing natural oxidation. However, it is preferable to perform natural oxidation in a period of 7 days or less because the mass production efficiency is lowered if the product is exposed to the atmosphere longer than 7 days.

  The substrate temperature at the time of natural oxidation is not particularly limited. When natural oxidation is performed at a temperature higher than room temperature (18 to 24 ° C.), the silicon substrate 30 may be heated by a hot plate. Thereby, natural oxidation can be promoted.

  Further, in the case of using the above-mentioned titanium nitride substitute as the material of the first barrier film 67, the material of the second barrier film 68 formed by oxidizing the substitute is TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfAlON, ZrAlON, TiSiON, TaSiON, IrOx, RuOx, and the like.

  The method for forming the second barrier film 68 is not limited to natural oxidation.

  For example, the second barrier film 68 may be formed by oxidizing the surface of the first barrier film 67 in an annealing chamber such as an RTA chamber or a furnace.

  In this case, annealing is preferably performed at a substrate temperature of 500 ° C. or lower in order to prevent a large amount of oxygen from being taken into the film due to excessive oxidation and causing the second barrier film 68 to have a high resistance. Also, in the oxidizing atmosphere, in order to prevent excessive oxidation, the flow rate ratio of oxygen gas in the mixed gas of inert gas and oxygen gas is preferably as low as possible, for example, 1% or less. Argon gas or nitrogen gas can be used as the inert gas. Among these, nitrogen gas is more preferable than argon gas in that nitrogen atoms that enhance conductivity are taken into the second barrier film 68 and the resistance of the second barrier film 68 is reduced.

  Alternatively, the SIP chamber used to form the first barrier film 67 is subsequently used, and oxygen is introduced into the SIP chamber to oxidize the surface of the first barrier film 67, so that the second barrier film 67 is oxidized. A film 68 may be formed. During the introduction of oxygen, the supply of argon gas and nitrogen gas, which are the sputtering gases for the first barrier film 67, may be continued or stopped. Further, the supply of sputtering power when the first barrier film 67 is formed may be stopped to oxidize the surface of the first barrier film 68. Alternatively, the sputtering power may be supplied and oxynitrided by reactive sputtering. A second barrier film 68 made of titanium may be formed.

  In this manner, since the second barrier film 68 can be continuously formed without taking out the silicon substrate 30 from the SIP chamber after the first barrier film 67 is formed, the mass production efficiency of the semiconductor device is improved.

  Furthermore, regardless of which oxidation method is used, the second barrier film 68 containing oxygen atoms has a higher electrical resistance than the first barrier film 67, so the second barrier film 68 is used as the first barrier film. It is preferable to make it thinner than the film 67 to lower the electrical resistance of the entire laminated film.

  Next, as shown in FIG. 21A, a titanium nitride film is formed as a conductive third barrier film 69 on the second barrier film 68 to a thickness of about 50 nm by sputtering.

  The method for forming the third barrier film 69 is not particularly limited. Similarly to the first barrier film 67, the third barrier film 69 may be formed by sputtering in the SIP chamber, or may be a plating method, an organometallic decomposition method, a CSD (Chemical Solution Deposition) method, a chemical vapor phase, or the like. Any of vapor deposition, epitaxial growth, and MOCVD (Metal Organic CVD) may be used.

  Since any of these methods does not involve film oxidation, the oxygen concentration of the third barrier film 69 is lower than that of the second barrier film 68.

  Further, the material of the third barrier film 69 is not limited to titanium nitride, and an alternative similar to the first barrier film 67 can be used. However, from the viewpoint that the same deposition apparatus as that of the first barrier film 67 can be used and no new capital investment is required, a film made of the same material as the first barrier film 67 is used as the third barrier film 68. Preferably formed.

  By forming the third barrier film 69 in this way, the barrier properties of the first and second barrier films 67 and 68 against elements such as hydrogen and fluorine can be supplemented.

  Further, since the second barrier film 68 is interposed between the first barrier film 67 and the third barrier film 69, the crystal grain boundaries of the first barrier film 67 and the second barrier film 68 are shifted from each other. Thus, it becomes easy to prevent intrusion of hydrogen or fluorine through the crystal grain boundary.

  The third barrier film 69 protects the capacitor Q from hydrogen and the like in this way. However, when only the first and second barrier films 67 and 68 can sufficiently barrier hydrogen or the like, It may be omitted.

  Next, as shown in FIG. 21B, a tungsten film is formed on the third barrier film 69 as a plug conductive film 74 to a thickness of about 300 nm by a CVD method, and each hole 71a is formed by the conductive film 74. Embed ~ 71c completely.

  In the CVD method, a mixed gas of tungsten hexafluoride gas and hydrogen gas is used. As described above, the barrier property of the second barrier film 68 against hydrogen and fluorine is enhanced by oxygen in the film. Due to such a high barrier property of the second barrier film 68, the capacitor Q can be protected from the film formation atmosphere of the conductive film 74, and a cavity as shown in FIG. It is possible to prevent the ferroelectric characteristics of the capacitor dielectric film 62 from being deteriorated.

  The conductive film 74 is not limited to a tungsten film, and may be a copper film or a polysilicon film. Among these, regarding the copper film, when the film is formed by the CVD method in which hydrogen is contained in the film formation atmosphere, the actual benefit of the hydrogen barrier by the second barrier film 68 is obtained. Further, since the polysilicon film formation atmosphere also contains hydrogen, it is preferable to protect the capacitor Q from hydrogen by forming the second barrier film 68 having a high hydrogen barrier property.

  Next, as shown in FIG. 22, the excess barrier films 67 to 69 and the conductive film 74 on the upper surface of the cap insulating film 73 are polished by the CMP method, and these films are second only in the holes 71a to 71c. The conductive plug 77 is left.

  Thereafter, the natural oxide film on the upper surface of the second conductive plug 77 is removed by etching using argon plasma.

  Next, as shown in FIG. 23, a metal laminated film is formed on the second conductive plug 77 and the cap insulating film 73, and this metal laminated film is patterned to form a first-layer metal wiring 78.

  As the metal laminated film, for example, a titanium nitride film having a thickness of about 50 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride film having a thickness of about 50 nm are formed in this order by sputtering. Form.

  Further, on this first layer metal wiring 78, as shown in the figure, third to sixth interlayer insulating films 83 to 86 and second to fifth layer metal wirings 79 to 82 are alternately laminated to form a multilayer wiring structure. Form.

  Then, a first passivation film 87 made of silicon oxide and a second passivation film 88 made of silicon nitride are formed in this order on the uppermost fifth-layer metal wiring 82.

  Thereafter, a polyimide coating film is formed on the second passivation film 88 and thermally cured to form a protective insulating film 89.

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  In the present embodiment, as described with reference to FIG. 20B, the second barrier film having a higher oxygen concentration than the first barrier film 67 is obtained by oxidizing the surface of the first barrier film 67. 68 was formed. As described above, the second barrier film 68 having an oxygen concentration higher than that of the first barrier film 67 has a higher barrier property against hydrogen, fluorine, and the like than the first barrier film 67.

  Therefore, even if foreign matter adheres to the upper electrode 63 during the manufacture of the semiconductor device, and the first and second barrier films 67 and 68 are formed on the foreign matter, the barrier properties of these films are reduced. Can be maintained. As a result, for example, when the plug conductive film 74 is formed (FIG. 21B), hydrogen and fluorine in the film formation atmosphere hardly reach the capacitor Q, and the cavity caused by these elements becomes the upper electrode. It is possible to suppress the occurrence at 63. Thereby, the contact resistance between the upper electrode 63 and the second conductive plug 77 is stabilized, and the yield of the semiconductor device is improved.

  Further, since the second barrier film 68 thus barriers hydrogen, it is possible to prevent the capacitor dielectric film 62 from being reduced by hydrogen. As a result, the ferroelectric characteristics of the capacitor dielectric film 62 such as the residual polarization charge amount can be maintained, and the retention characteristics of the semiconductor device can be improved.

  In the above description, the second barrier film 68 having a high oxygen concentration is formed on the first barrier film 67. However, the order of forming these films may be reversed. In that case, the upper electrode 63 and the lower electrode 61 are in contact with the second barrier film 68. However, when a noble metal oxide film such as an iridium oxide film is formed as the upper electrode 63, the second barrier film 68 and the noble metal oxide film may react to increase the contact resistance. Therefore, in this case, it is preferable to form the second barrier film 68 on the first barrier film 67 as in this embodiment.

  The second barrier film 68 has higher electrical resistance than the first barrier film 67 and the third barrier film 68 due to oxygen in the film. Therefore, from the viewpoint of reducing the resistance of the second conductive plug 71, it is preferable to form the second barrier film 68 thinner than the first barrier film 67 and the third barrier film 69.

  Below, the investigations conducted by the inventors of the present application in relation to the present embodiment will be described.

First Survey This survey examined how the barrier properties of the barrier film depend on the slot number. The slot number represents the processing order of the silicon substrates in one lot (25) in ascending order. The first substrate in one lot is represented by slot 1 and the last substrate is represented by slot 25. .

  24A and 24B are sectional views of the first and second samples S1 and S2 used in this investigation.

  As shown in FIG. 24A, the first sample S1 is formed by forming a silicon oxide film 44, an iridium oxide film 54, and a titanium nitride film 55 on the silicon substrate 40 in this order. Among these, the iridium oxide film 54 corresponds to the upper electrode 63 (see FIG. 22). The uppermost titanium nitride film 55 corresponds to a barrier film and has a thickness of 100 nm.

  On the other hand, as shown in FIG. 24 (b), in the second sample S2, the titanium nitride film 55 is formed in two layers, and the titanium oxynitride film 56 is formed by naturally oxidizing titanium nitride between them. Formed. The titanium oxynitride film 56 is formed by exposing the titanium nitride film 55 to the atmosphere for 5 minutes, and corresponds to the second barrier film 68 of the present embodiment. Note that the thickness of the titanium nitride film 55 above and below the titanium oxynitride film 56 is 50 nm.

  FIG. 25 (a) is a graph obtained by measuring the hydrogen concentration in each of the samples S1 and S2 using a SIMS (Secondary Ionization Mass Spectrometer).

  The horizontal axis of these graphs indicates the depth from the surface of each sample, and the vertical axis indicates the concentration of hydrogen, oxygen, or the like.

  In this investigation, sample S1 was placed in slot 1 and slot 24 of one lot. Slots 2 to 23 are all dummy wafers. Then, the sample S2 was placed in the slot 25.

  As shown in FIG. 25A, the hydrogen concentration in the single layer titanium film 55 of the sample S1 is different between the slot 1 and the slot 24. In particular, it can be seen that the barrier property of the titanium nitride film 55 decreases as the hydrogen concentration in the slot 24 increases and the slot number increases.

  This is presumably because the chamber is heated while the titanium nitride film is formed in the sputtering chamber, and the sputtering atmosphere in the chamber changes.

  As described above, when the single-layer titanium film 55 as in the sample S1 is used as the barrier film, there is a possibility that the yield of the semiconductor device may be reduced due to the reduction in barrier properties.

  On the other hand, the sample S2 has a hydrogen concentration in the titanium nitride film 55 lower than that of the slot 24 although it is placed in the slot 25 where the sputtering atmosphere is considered to vary most compared to the slot 1. This is presumably because hydrogen is blocked by the titanium oxynitride film 56.

  From this result, it is clear that by forming the titanium oxynitride film 56 as in the sample S2, the hydrogen barrier property is enhanced, and the variation in the barrier property due to the variation in the deposition atmosphere of the titanium nitride film is also reduced. It was. Therefore, the barrier property is good in all slots of one lot, and the yield of the semiconductor device can be improved as compared with the case where a single-layer titanium nitride film is used as the barrier film.

  FIG. 25 (b) is a graph obtained by investigating the oxygen concentration by SIMS for the same sample as FIG. 25 (a).

  As shown in this, in the second sample S2 in the slot 25, the oxygen concentration is high in the middle of the titanium nitride film. Thereby, it was confirmed that the titanium oxynitride film 56 was actually formed at a depth in the middle of the titanium nitride film 55.

Second Investigation As shown in FIG. 25A, in sample S1 in which a single-layer titanium nitride film is formed, the barrier property of the titanium nitride film depends on the slot number.

  In this study, we investigated how the composition of the titanium nitride film depends on the slot number by RBS (Rutherford Backscattering Spectroscopy) analysis. The results are schematically shown in FIGS. 26 (a) to (c).

  As shown in these drawings, in this investigation, a silicon oxide film 64 was formed on the iridium oxide film 54 using TEOS gas, and a hole 64 a was formed in the silicon oxide film 64.

  In the samples of FIGS. 26A and 26B, a single layer of titanium nitride film 55 is formed in the hole 64a to a thickness of 100 nm by sputtering, and then the hole 64a is filled with the tungsten film 75.

  On the other hand, in the sample of FIG. 26C, after forming the titanium nitride film 55 to a thickness of 50 nm in the hole 64a by sputtering, the surface is naturally oxidized in the atmosphere for 5 minutes to form the titanium oxynitride film 56. Formed. Then, a titanium nitride film 55 having a thickness of 50 nm was again formed on the titanium oxynitride film 56 by sputtering, and a tungsten film 75 was formed thereon.

  In this investigation, as in the first investigation, the samples shown in FIGS. 26A and 26B were put in one slot 1 and slot 24, respectively, and the sample shown in FIG.

  As shown in FIG. 26A, the single layer titanium nitride film 55 in the slot 1 has a titanium composition ratio of 46% and a nitrogen composition ratio of 54%. However, in the upper part, titanium is 47.5% and nitrogen is 52.5%. In FIG. 26A, such a difference in composition ratio is schematically shown by hatching density.

  This reveals that the composition ratio of the single-layer titanium nitride film 55 fluctuates even during the film formation.

  Similarly, as shown in FIG. 26 (b), the composition ratio of the single layer titanium nitride in the slot 25 varies in the film.

  Further, comparing FIGS. 26A and 26B, it is understood that the composition ratio varies depending on the slot number. When the composition ratio varies in this way, the barrier property against hydrogen or the like also varies depending on the slot number.

  On the other hand, as shown in FIG. 26C, when the titanium oxynitride film 56 is formed in the middle of the titanium nitride film 55, the composition ratio of the titanium film 55 above and below the titanium oxynitride film 56 becomes the same. Variations in the composition ratio are suppressed.

  As described above, when the titanium oxynitride film is formed as in this embodiment, not only the hydrogen barrier property is improved, but also the composition variation of the titanium nitride film can be suppressed. It is possible to suppress fluctuations depending on the slot number and fluctuations depending on the slot number.

Third survey In this survey, the barrier properties of the titanium oxynitride film were further investigated by SIMS.

  The result of the investigation is shown in FIG.

As shown in FIG. 27, the sample used for the investigation is formed by forming a silicon oxide (SiO ₂ ) film and a titanium nitride (TiN) film in this order on a silicon (Si) substrate. Of these, a titanium nitride film is first formed to a thickness of 50 nm by sputtering, and then the surface is naturally oxidized in the atmosphere for 5 minutes to form a titanium oxynitride (TiON) film, which is then sputtered again. To a thickness of 50 nm.

  In FIG. 27, the horizontal axis indicates the depth from the surface of the titanium nitride film, and the vertical axis indicates the concentration of each element.

  In the investigation, this sample was annealed in a deuterium D atmosphere at a substrate temperature of 400 ° C. for 30 minutes. The reason why deuterium is used instead of hydrogen is that deuterium has less background noise and is suitable for measurement.

  As shown in FIG. 27, deuterium D enters from the back side (right side in the figure) of the silicon substrate, and the concentration thereof decreases as the surface approaches the surface of the titanium nitride film 50. This revealed that titanium oxynitride has a barrier property against deuterium D.

  Note that the concentration of hydrogen H is higher than that of deuterium D. This is because the background of hydrogen is higher than that of deuterium D, which does not indicate that hydrogen permeates the titanium oxynitride film. Absent.

  Further, since the oxygen concentration has a peak B at a midway depth of the titanium nitride film, it was confirmed that a titanium oxynitride film can be formed by natural oxidation of the titanium nitride film.

(3) Second Embodiment In the first embodiment, the planar type FeRAM has been described.

  On the other hand, in this embodiment, a stack type FeRAM in which a conductive plug is formed immediately below the lower electrode will be described. The stack type FeRAM has a smaller capacitor occupation area than the planar type, and is advantageous for high integration.

  28 to 42 are cross-sectional views of the semiconductor device according to the second embodiment of the present invention in the middle of manufacture. In these drawings, the same elements as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted below.

  This semiconductor device is manufactured as follows.

  First, as shown in FIG. 28A, according to the steps of FIGS. 8A and 8B of the first embodiment, a MOS transistor TR is formed on the silicon substrate 30, and the MOS transistor TR is covered with a cover insulating film. 41 and a first interlayer insulating film 42.

  Next, as shown in FIG. 28B, contact holes are formed in the insulating films 41 and 42 by photolithography and etching, and a first conductive plug 43 is formed therein.

  As described in the first embodiment, the first conductive plug 43 has tungsten as a main component, and easily oxidizes in an oxygen-containing atmosphere to easily cause a contact failure.

  Therefore, in the next step, as shown in FIG. 28C, a silicon oxynitride film is formed to a thickness of about 130 nm by the CVD method as an anti-oxidation insulating film 92 for preventing the first conductive plug 43 from being oxidized. .

  Note that a silicon nitride film or an alumina film may be formed as the antioxidant insulating film 92 instead of the silicon oxynitride film.

  Further, a silicon oxide film having a thickness of about 300 nm is formed on the oxidation-preventing insulating film 92 by plasma CVD using TEOS gas, and this silicon oxide film is used as a second interlayer insulating film 93.

  Then, a first hole 93a is formed in each of the insulating films 92 and 93 above the first source / drain region 36a by photolithography and etching, and is electrically connected to the first conductive plug 43. Two conductive plugs 91 are formed in the first contact hole 93a.

  The method for forming the second conductive plug 91 is not particularly limited.

  In the present embodiment, a titanium nitride film and a tungsten film are formed in this order on the upper surface of the second interlayer insulating film 93 and the inner surface of the first hole 93a, and these are polished by the CMP method to be in the first hole 93a. Is left as the second conductive plug 91 only.

  In the CMP, a slurry in which the polishing rate of the titanium nitride film and the tungsten film to be polished is higher than the polishing rate of the second interlayer insulating film 93, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used. In order not to leave a polishing residue on the second interlayer insulating film 93, the CMP polishing amount is set to be larger than the total thickness of the titanium nitride film and the tungsten film, and this CMP is over-polished. .

  As a result, the height of the upper surface of the second conductive plug 91 becomes lower than that of the second interlayer insulating film 93, and a recess is formed in the second interlayer insulating film 93 around the second conductive plug 91. Sometimes formed. The depth of the recess is 20 to 50 nm, typically about 50 nm.

Next, as shown in FIG. 29A, NH ₃ plasma treatment is performed on the surface of the second interlayer insulating film 93 to bond NH groups to oxygen atoms on the surface of the second interlayer insulating film 93. .

The NH ₃ plasma process, for example, using a parallel plate type plasma processing chamber having a counter electrode to about 9mm spaced position with respect to the silicon substrate 30, a substrate temperature of 400 ° C. under a pressure of 266 Pa, NH ₃ into the chamber The gas is supplied at a flow rate of 350 sccm. In this case, high frequency power of 13.56 MHz is supplied to the silicon substrate 30 side with a power of 100 W, and high frequency power of 350 kHz is supplied to the counter electrode with a power of 55 W for 60 seconds.

  Next, as shown in FIG. 29B, a titanium film having a thickness of 100 to 300 nm, for example, is formed on each of the second interlayer insulating film 93 and the second conductive plug 91 as a base conductive film 94 by sputtering. Formed to 100 nm.

  The conditions for forming the titanium film are not particularly limited. In this embodiment, the substrate temperature is set to 20 ° C. in an argon atmosphere of 0.15 Pa in a sputtering chamber in which the distance between the titanium target and the silicon substrate 30 is set to 60 mm. Then, 2.6 kW of DC power is applied to the sputtering atmosphere for 35 seconds to form the titanium film.

  The base conductive film 94 is not limited to a titanium film, and any of a tungsten film, a silicon film, and a copper film may be formed as the base conductive film 94.

Here, since NH groups are bonded to oxygen atoms on the surface of the second interlayer insulating film 93 by NH ₃ plasma treatment in advance in the step of FIG. 29A, titanium in the base conductive film 94 is converted into oxygen atoms. It becomes difficult to be captured. Therefore, titanium can freely move on the surface of the second interlayer insulating film 93, and the base conductive film 94 made of titanium self-organized in the (002) direction is obtained.

  Thereafter, the base conductive film 94 is annealed in a nitrogen atmosphere to nitride the titanium of the base conductive film 94. The titanium nitride obtained by nitriding in this way preferably has a (111) orientation in order to align PZT described later in the (111) direction.

  Although the annealing conditions are not particularly limited, in this embodiment, the annealing is performed by RTA at a substrate temperature of about 650 ° C. and a processing time of about 60 seconds.

  By the way, the above-described recess is formed around the second conductive plug 91 on the upper surface of the second interlayer insulating film 93 by performing CMP in the process of FIG. May have been. Therefore, irregularities reflecting this recess may be formed on the upper surface of the base conductive film 94.

  However, if there are such irregularities, the crystallinity of a ferroelectric film formed later above the underlying conductive film 94 may deteriorate.

  Therefore, in the next step, as shown in FIG. 29C, the upper surface of the underlying conductive film 94 is polished and planarized by the CMP method. The slurry used in the CMP is not particularly limited, but in this embodiment, SSW2000 manufactured by Cabot Microelectronics Corporation is used.

  The thickness of the underlying conductive film 94 after this CMP varies within the plane of the silicon substrate 30 and between the plurality of silicon substrates 30 due to polishing errors. In consideration of the variation, in this embodiment, the target value of the thickness of the underlying conductive film 94 after CMP is set to 50 to 100 nm, more preferably 50 nm, by controlling the polishing time.

  Thus, after CMP is performed on the base conductive film 94, the crystal in the vicinity of the upper surface of the base conductive film 94 is distorted by polishing. However, if the lower electrode of the capacitor is formed above the underlying conductive film 94 in which the crystal is distorted as described above, the distortion is picked up by the lower electrode, and the crystallinity of the lower electrode is deteriorated. The ferroelectric characteristics of the ferroelectric film will deteriorate.

In order to avoid such inconvenience, in the next step, as shown in FIG. 30A, NH ₃ plasma treatment is performed on the base conductive film 94, so that the crystal distortion of the base conductive film 94 is reduced. Do not reach the upper membrane.

The NH ₃ plasma processing conditions are the same as those in the NH ₃ plasma processing of FIG.

Next, as shown in FIG. 30B, a titanium film is formed to a thickness of approximately 5 by sputtering as the crystalline conductive film 95 on the base conductive film 94 from which crystal distortion has been eliminated by the NH ₃ plasma treatment. Formed to 20 nm. Further, RTA with a substrate temperature of 650 ° C. and a processing time of 60 seconds is performed on the crystalline conductive film 95 in a nitrogen atmosphere to nitride the crystalline conductive film 95.

  Thereby, a crystalline conductive film 95 made of titanium nitride oriented in the (111) direction is obtained.

  The crystalline conductive film 95 has a function as an adhesion film in addition to the function of increasing the orientation of a film formed later on the crystalline conductive film 95 by the action of its own orientation.

  The crystalline conductive film 95 is not limited to a titanium nitride film. For example, a noble metal film such as a thin iridium film or platinum film of about 20 nm may be formed as the crystalline conductive film 95.

  Next, as shown in FIG. 30C, a titanium aluminum nitride (TiAlN) film is formed on the crystalline conductive film 95 as a conductive oxygen barrier film 96 to a thickness of about 100 nm.

  This titanium aluminum nitride film can be formed by a reactive sputtering method in which a target made of an alloy of titanium and aluminum is sputtered in a mixed atmosphere of argon gas and nitrogen gas. In that case, the argon gas flow rate is set to about 40 sccm, and the nitrogen gas flow rate is about 10 sccm. The pressure is about 253.3 Pa, the substrate temperature is 400 ° C., and the sputtering power is 1.0 kW.

  Next, as illustrated in FIG. 31A, an iridium film is formed on the conductive oxygen barrier film 96 by sputtering, and the iridium film is used as a first conductive film 97.

  This iridium film is formed to a thickness of about 100 nm with a sputtering power of 0.5 kW at a substrate temperature of 500 ° C. under a pressure of 0.11 Pa, for example.

Note that the first conductive film 97 is not limited to an iridium film, and may be a noble metal film other than the iridium film, for example, a platinum film. Further, a film made of a conductive metal oxide such as PtO, IrOx, SrRuO ₃ may be formed as the first conductive film 97.

  Next, as shown in FIG. 31B, a PZT film having a thickness of about 100 nm is formed as a first ferroelectric film 98 on the first conductive film 97 by MOCVD.

  The MOCVD method is performed as follows.

First, Pb (DPM) ₂ (chemical formula Pb (C ₁₁ H ₁₉ O ₂ ) ₂ )), Zr (dmhd) ₄ (chemical formula Zr (C ₉ H ₁₅ O ₂ ) ₄ ), and Ti (O-iOr) ₂ ( Each of DPM) ₂ (chemical formula Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is 0.3 mol / l in THF (Tetra Hydro Furan: C ₄ H ₈ O) solvent. Dissolve at a concentration to create Pb, Zr, and Ti liquid raw materials. Next, these liquid raw materials are supplied to the vaporizer of the MOCVD apparatus at a flow rate of 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min, respectively, to vaporize them, so that Pb, Zr, and Ti A raw material gas is obtained. The vaporizer is supplied with a THF solvent having a flow rate of 0.474 ml / min together with each liquid raw material.

  Further, while supplying the source gas to the chamber, the pressure in the chamber is set to 665 Pa, and the substrate temperature is maintained at 620 ° C. Then, by maintaining such a state for 620 seconds, the PZT film described above is formed to a thickness of 100 nm.

  Since the first ferroelectric film 98 formed by the MOCVD method is crystallized at the time of film formation, crystallization annealing is not necessary.

  The film formation method of the first ferroelectric film 98 is not limited to the MOCVD method, but a sputtering method, a sol-gel method, a metal organic decomposition (MOD) method, a CSD (Chemical Solution Deposition) method, Further, the first ferroelectric film 98 may be formed by an epitaxial growth method. Among these, in the case of sputtering, for example, the first ferroelectric film 98 is not crystallized at the time of film formation, so crystallization annealing is performed after the film formation as in the first embodiment.

Further, the first ferroelectric film 98 is not limited to PZT. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the first ferroelectric film 98. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the first ferroelectric film 98.

  Next, as shown in FIG. 31C, a PZT film is formed on the first ferroelectric film 98 to a thickness of about 1 to 30 nm, for example, 20 nm by RF sputtering, and this PZT film is formed into the second ferroelectric film. A body membrane 99 is used. Since the PZT formed by the sputtering method is not crystallized immediately after the film formation, the second ferroelectric film 99 is amorphous at this point.

  Thereafter, as shown in FIG. 32A, an iridium oxide film having a thickness of 10 to 75 nm, for example, 50 nm, is formed as a second conductive film 100 on the second ferroelectric film 99 by sputtering.

  In the sputtering method, an iridium target is sputtered with a mixed gas of argon gas and oxygen gas, whereby iridium scattered from the iridium target is oxidized in a sputtering atmosphere to form the iridium oxide film.

  Moreover, although the film-forming conditions of the 2nd electrically conductive film 100 are not specifically limited, In this embodiment, substrate temperature shall be 300 degreeC and sputter | spatter power shall be about 1-2 kW. By adopting such conditions, an iridium oxide film crystallized at the time of film formation is formed.

  Note that the second conductive film 100 is not limited to an iridium oxide film. The second conductive film 100 may be formed by using a sputtering target made of any one of platinum, ruthenium, rhodium, rhenium, osmium, and palladium and performing sputtering under conditions in which these metals are oxidized.

  Subsequently, as shown in FIG. 32B, crystallization annealing is performed on the second ferroelectric film 99 in a state where the second conductive film 100 is formed, so that the second ferroelectric film is formed. Crystallize 99 PZT.

  Since this crystallization annealing is performed in an oxygen-containing atmosphere, oxygen is supplied from the annealing atmosphere to the second ferroelectric film 99, and oxygen vacancies in the second ferroelectric film 99 are compensated. Furthermore, this crystallization annealing can also provide an advantage that the plasma damage received by the second ferroelectric film 99 during the formation of the second conductive film 100 can be recovered.

  In this embodiment, this annealing is performed by RTA in a mixed gas atmosphere of oxygen gas and argon gas. The gas flow rate is not particularly limited, but the oxygen gas flow rate is 20 sccm and the argon gas flow rate is 2000 sccm. The processing time is 60 seconds, and the substrate temperature is 650 to 750 ° C., for example, 725 ° C.

  Thereafter, as shown in FIG. 33A, an iridium oxide film is formed on the second conductive film 100 to a thickness of about 100 to 300 nm by sputtering, and the iridium oxide film is formed into the first conductive protective film. The film 101 is used.

  The film forming conditions of the first conductive protective film 101 are not particularly limited.

  In the present embodiment, argon gas and oxygen gas are used as the sputtering gas, and the film forming pressure is 0.8 Pa. Then, the first conductive protective film 101 made of iridium oxide having a thickness of about 200 nm is formed by setting the film formation time to 79 seconds with a sputtering power of 1.0 kW.

  When oxygen is insufficient in the first conductive protective film 101, the proportion of iridium having a reducing action in the first conductive protective film 101 increases. In this case, moisture or the like is reduced by the first conductive protective film 101 to become hydrogen, and the first and second ferroelectric films 98 and 99 may be deteriorated by the hydrogen.

Therefore, as the iridium oxide of the first conductive protective film 101, by using the iridium oxide whose composition is as close as possible to the stoichiometric composition (IrO ₂ ) of iridium, the proportion of iridium in the film is reduced. It is preferable to prevent deterioration of the ferroelectric films 98 and 99 due to hydrogen. The composition of the iridium oxide can be controlled to some extent by adjusting the flow rate ratio of the oxygen gas in the sputtering gas.

Note that the material of the first conductive protection film 101 is not limited to iridium oxide. Instead of iridium oxide, a film of any one of iridium, ruthenium, rhodium, rhenium, osmium, and palladium, or a film made of these oxides, or a single-layer film of any of SrRuO ₃ films, or a laminated film thereof. The first conductive protective film 101 may be formed.

  Next, as shown in FIG. 33B, an iridium film is formed as a second conductive protective film 102 on the first conductive protective film 101 to a thickness of about 100 nm by sputtering.

  In the sputtering method, argon gas is used as the sputtering gas, the film forming pressure is 1 Pa, and the sputtering power is 1.0 kW.

Note that a platinum film or an SrRuO ₃ film may be formed as the second conductive protective film 102 instead of the iridium film.

  Thereafter, the PZT attached to the back surface of the silicon substrate 30 when the first and second ferroelectric films 98 and 99 are formed is cleaned and removed.

  Next, steps required until a sectional structure shown in FIG.

  First, a titanium nitride film is formed on the second conductive protective film 102 by sputtering, and the titanium nitride film is used as the first hard mask 103.

  The first hard mask 103 is not limited to a titanium nitride film. A single layer film of a titanium aluminum nitride film, a tantalum aluminum nitride (TaAlN) film, a tantalum nitride (TaN) film, or a stacked film thereof may be formed as the first hard mask 103.

  Then, a silicon oxide film is formed as the second hard mask 104 on the first hard mask 103 by a plasma CVD method using TEOS gas.

  Thereafter, the first and second hard masks 103 and 104 are patterned by photolithography and etching, and these masks are formed into island shapes as shown in the drawing.

Next, as shown in FIG. 34 (a), the first and second hard masks 103 and 104 are covered by plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas. The non-exposed portions of the films 97 to 102 are dry-etched.

  Thus, the first conductive film 97 and the second conductive film 100 become the lower electrode 97a and the upper electrode 100a, respectively, and the first and second ferroelectric films 98 and 99 become the capacitor dielectric film 98a.

  Through the steps up to here, the ferroelectric capacitor Q including the lower electrode 97a, the capacitor dielectric film 98a, and the upper electrode 100a is formed in the cell region of the silicon substrate 30.

  Next, as shown in FIG. 35A, the second hard mask 104 is removed by dry etching or wet etching.

  Then, as shown in FIG. 35B, the underlying conductive film 94, the crystalline conductive film 95, and the conductive oxygen barrier film 96 that are not covered with the capacitor Q are removed by dry etching.

This etching is performed using, for example, a down flow type plasma etching chamber and using a mixed gas of 5% CF ₄ gas and 95% O ₂ gas as an etching gas. Further, high frequency power having a frequency of 2.45 GHz and a power of 1400 W is supplied to the upper electrode of the chamber, and the substrate temperature is set to 200 ° C.

  Note that the first hard mask 103 remains on the capacitor Q without being removed by this etching.

  Subsequently, as shown in FIG. 36A, a first alumina film 110 is formed on the entire upper surface of the silicon substrate 30 to a thickness of about 20 nm by sputtering. Note that an alumina film having a thickness of about 2 to 5 nm may be formed by MOCVD instead of sputtering.

  Thereafter, recovery annealing is performed on the capacitor dielectric film 98a in an oxygen-containing atmosphere for the purpose of recovering the damage received by the capacitor dielectric film 98a in the steps so far. The conditions for this recovery annealing are not particularly limited, but in this embodiment, the recovery annealing is performed at a substrate temperature of 550 to 700 ° C., for example, 600 ° C.

  Subsequently, as shown in FIG. 36B, a second alumina film 111 is formed to a thickness of about 38 nm on the first alumina film 110 by MOCVD.

  The first and second alumina films 110 and 111 have a function of blocking a reducing substance such as hydrogen, and prevent the capacitor dielectric film 98a from being reduced to deteriorate its ferroelectric characteristics. Take a role.

  Next, steps required until a sectional structure shown in FIG.

  First, a silicon oxide film is formed to a thickness of about 1500 nm on the second alumina film 111 by plasma CVD, and the silicon oxide film is used as the third interlayer insulating film 112. In the plasma CVD method, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as a film forming gas.

  Thereafter, the upper surface of the third interlayer insulating film 112 is polished and planarized by the CMP method.

Next, by annealing the third interlayer insulating film 112 in an atmosphere of N ₂ O plasma or N ₂ plasma, the third interlayer insulating film 112 is dehydrated and its upper surface is nitrided to prevent re-adsorption of moisture. To do.

  Next, in order to protect the capacitor dielectric film 98a from hydrogen or the like, a third alumina film is formed on the third interlayer insulating film 112 to a thickness of about 20 to 100 nm by sputtering or MOCVD.

  Further, a silicon oxide film having a thickness of about 800 to 1000 nm is formed on the third alumina film 113 by plasma CVD using TEOS gas, and this silicon oxide film is used as a cap insulating film 114.

  Note that a silicon oxynitride film or a silicon nitride film may be formed as the cap insulating film 114 instead of the silicon oxide film.

  Next, as shown in FIG. 37 (b), the insulating films 110 to 114 are patterned by photolithography and etching to form first holes 112a in these insulating films above the upper electrode 100a.

  Then, in order to recover the damage received by the capacitor dielectric film 98a in the steps so far, recovery annealing is performed at a substrate temperature of about 450 ° C. in an oxygen-containing atmosphere.

  Next, as shown in FIG. 38A, the second holes 112b are formed in the insulating films 92, 93, 110 to 114 above the second source / drain regions 36b by photolithography and etching.

  Thereafter, the third interlayer insulating film 113 and the like are dehydrated by annealing. The annealing is preferably performed in an inert gas atmosphere or a reduced-pressure atmosphere in order to prevent oxidation of the first conductive plug 43 exposed from the second hole 112b.

  Next, steps required until a sectional structure shown in FIG.

  First, the natural oxide film on the upper surface of the second conductive protective film 102 and the first conductive plug 43 exposed from the holes 112a and 112b is removed by RF etching using argon plasma.

  Then, a titanium nitride film having a thickness of about 75 nm is formed by sputtering as a conductive first barrier film 118 on the inner surface of each of the holes 112a and 112b and the surface of the second conductive protection film 102 exposed from the first hole 112a. Form to thickness.

  The first barrier film 118 is formed in order to prevent cavities and the like from being formed in the capacitor Q by these elements by barriering hydrogen, fluorine, and the like.

  Note that the aspect ratio of the second hole 112b above the second source / drain region 36b is higher than that of the first hole 112a. Therefore, it is preferable to form the first barrier film 118 with good coverage in each of the holes 112a and 112b by using the sputtering method using the SIP technique described in the first embodiment.

  In addition, although the film formation conditions of the first barrier film 118 are not particularly limited, in this embodiment, argon gas and nitrogen gas are introduced into a SIP chamber provided with a titanium target, and the substrate temperature is set to 150 to 250 ° C. For example, the first barrier film 118 is formed at 200 ° C. The flow rate of each gas is, for example, 50 sccm for argon gas and 90 sccm for nitrogen gas.

  The first barrier film 118 is not limited to a titanium nitride film. As a material of the first barrier film 118, in addition to titanium nitride, metal nitrides such as TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, and ZrAlN can be used. Further, a metal oxynitride such as TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfAlON, ZrAlON, TiSiON, and TaSiON may be used as the material of the first barrier film 118. Further, a noble metal such as Ir and Ru, or an oxide of IrOx and RuOx, which are oxides thereof, may be formed as the first barrier film 118. In addition, a Ti film, a Ta film, and a TiN film that is a nitride film thereof, a Ti / TiN film formed by laminating a TaN film, a Ti / TaN film, a Ta / TiN film, and a Ta / TaN film are used. One barrier film 118 may be formed.

  Subsequently, as shown in FIG. 39A, the first barrier film 118 is exposed to the atmosphere and the surface thereof is naturally oxidized, whereby a conductive second barrier film 119 made of titanium oxynitride (TiON). Is formed to a thickness of several angstroms on the first barrier film 118. The natural oxidation is performed, for example, for a period of 5 minutes to 7 days while maintaining the substrate temperature at 0 to 100 ° C.

  As described in the first embodiment, since the titanium oxynitride film has a high barrier property against hydrogen, fluorine, etc., the capacitor Q is exposed to these elements as compared with the case where the first barrier film 118 is used as a single layer. It is possible to reduce the risk of being lost.

  Note that instead of natural oxidation, the surface of the first barrier film 118 may be oxidized by annealing to form the second barrier film 119. In that case, in order to prevent the electric resistance of the second barrier film 119 from being lowered due to excessive oxidation, it is preferable to perform annealing at a substrate temperature of 500 ° C. or lower.

  Furthermore, in order to increase the mass production efficiency, the surface of the first barrier film 67 may be oxidized by continuously using the SIP chamber used for forming the first barrier film 118 and introducing oxygen into the SIP chamber. Good.

  Next, as shown in FIG. 39B, a titanium nitride film having a thickness of about 75 nm is formed on the second barrier film 119 as a conductive third barrier film 120 by sputtering.

  The method for forming the third barrier film 120 is not particularly limited. Similarly to the first barrier film 118, the third barrier film 120 may be formed by sputtering in the SIP chamber, or may be a plating method, a metal organic decomposition method, a CSD method, a chemical vapor deposition method, or an epitaxial growth method. Either of the MOCVD method and the MOCVD method may be used.

  As described in the first embodiment, since any of these methods does not involve oxidation of the film, the oxygen concentration of the third barrier film 120 is lower than that of the second barrier film 119.

  Note that the material of the third barrier film 120 is not limited to titanium nitride, and an alternative similar to the first barrier film 118 may be used. However, from the viewpoint that the same film forming apparatus as that of the first barrier film 118 can be used and no new capital investment is required, a film made of the same material as the first barrier film 118 is used as the third barrier film 120. Preferably formed.

  The third barrier film 120 protects the capacitor Q from hydrogen or the like, but is omitted when only the first and second barrier films 118 and 119 can sufficiently barrier hydrogen or the like. Also good.

  Subsequently, as shown in FIG. 40, a tungsten film is formed on the third barrier film 119 as a plug conductive film 121 by a CVD method to a thickness of about 300 nm. The holes 112a and 112b are completely filled.

  In the CVD method, a mixed gas of tungsten hexafluoride gas and hydrogen gas is used, but fluorine and hydrogen are blocked by the second barrier film 118. Therefore, it is possible to prevent the ferroelectric characteristics of the capacitor dielectric film 98a from deteriorating due to these elements and the generation of cavities in the upper electrode 100a.

  Here, the conductive film 121 is not limited to a tungsten film, and may be a copper film or a polysilicon film. As described in the first embodiment, hydrogen is also contained in the film formation atmosphere of these films, so that the benefit of the hydrogen barrier by the second barrier film 119 can be obtained.

  Next, as shown in FIG. 41, the excess barrier films 118 to 120 on the upper surface of the cap insulating film 114 and the conductive film 121 are polished by the CMP method, and these films are third only in the holes 112a and 112b. The conductive plug 116 is left.

  Of the third conductive plug 116, the one formed on the capacitor Q is electrically connected to the upper electrode 100a, and the one formed on the second source / drain region 36b is the first conductive plug. It is electrically connected to the plug 43.

  Thereafter, in order to remove the natural oxide film on the upper surface of the third conductive plug 116, the upper surface is etched by sputter etching with argon plasma.

  Next, as shown in FIG. 42, a metal laminated film is formed on each of the third conductive plug 116 and the cap insulating film 114 by sputtering, and is patterned to form a first metal wiring 115. .

  As the metal laminated film, for example, a titanium nitride film having a thickness of about 50 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride film having a thickness of about 50 nm are formed in this order.

  Thereafter, the second to fifth layer metal wirings and the interlayer insulating film are alternately laminated to obtain a multilayer wiring structure, but details thereof are omitted.

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  In the above-described embodiment, as described with reference to FIG. 39A, the surface of the first barrier film 1118 is oxidized to form the second barrier film 119. The second barrier film 119 whose oxygen concentration is higher than that of the first barrier film 118 by oxidation has a higher barrier property against hydrogen, fluorine, and the like than the first barrier film 118.

  Therefore, similarly to the first embodiment, it is possible to prevent a cavity from being formed in the upper electrode 100a by hydrogen or fluorine, and to stabilize the contact resistance between the upper electrode 100a and the third conductive plug 116 (see FIG. 41). Can be made.

  Furthermore, since the second barrier film 119 barriers hydrogen as described above, the capacitor dielectric film 98a can be prevented from being reduced by hydrogen, and the ferroelectric characteristics of the capacitor dielectric film 98a, such as residual polarization charge, can be prevented. The amount and the like can be maintained.

  As a result, in this embodiment, the yield and retention characteristics of the semiconductor device can be improved.

(4) Third Embodiment This embodiment is different from the second embodiment only in the method of forming the conductive plug, and the other points are the same as the second embodiment.

  In the present embodiment, the conductive plug is formed as follows.

  43 and 44 are enlarged cross-sectional views in the middle of manufacturing the conductive plug according to the present embodiment. In these drawings, elements described in the second embodiment are denoted by the same reference numerals as those in the second embodiment, and description thereof is omitted below.

  First, by performing the steps of FIGS. 28A to 40 described in the second embodiment, as shown in FIG. 43A, the first hole 112a is filled with the conductive film 121 for plug. As the conductive film 121, for example, a tungsten film or a polysilicon film can be formed.

  In the figure, the third alumina film 113 and the cap insulating film 114 (see FIG. 37A) described in the second embodiment are omitted, but these insulating films are formed in accordance with the second embodiment. It may be formed on the third interlayer insulating film 112.

  Next, as shown in FIG. 43B, the excess first to third barrier films 118 to 120 and the conductive film 121 on the third interlayer insulating film 112 are polished and removed by the CMP method.

  As shown in the figure, in this embodiment, the upper surface of the conductive film 121 is lowered to a depth in the middle of the first hole 112a by performing over polishing in the CMP.

  Next, as shown in FIG. 44A, a copper film 130 is formed on each of the conductive film 121 and the third interlayer insulating film 112. The method for forming the copper film 130 is not particularly limited. For example, a copper seed layer may be previously formed on the third interlayer insulating film 112 by a CVD method, and the copper film 130 may be formed by an electrolytic plating method using the copper seed layer as a power feeding layer.

  Then, as shown in FIG. 44B, the excess copper film 130 on the third interlayer insulating film 112 is removed by polishing by the CMP method, and the copper film 130 is left only in the first hole 112a. .

  Thus, the third conductive plug 116 including the first to third barrier films 118 to 120, the conductive film 121, and the copper film 130 is formed in the first hole 112a.

  Thus, the main process of the method for forming a conductive plug according to this embodiment is completed.

  According to such a method of forming the conductive plug 116, the low resistance copper film 130 is left to a depth in the middle of the first hole 112a, so that the hole 112a is formed only by the conductive film 121 such as a tungsten film or a polysilicon film. The resistance of the plug 116 can be reduced as compared with the case of embedding.

  Furthermore, the copper film 130 formed in the step of FIG. 44A is sufficient if the hole 112a is embedded in the portion above the conductive film 121, and is thinner than the case where the entire hole 112a is embedded. That's it. Control of the remaining film thickness by CMP becomes easier as the original thickness is thinner. Therefore, by forming the copper film 130 thin in this way, the height of the upper surface of the copper film 130 is set to the upper surface of the third interlayer insulating film 112 when the copper film 130 is polished in the step of FIG. It becomes easy to match, and these upper surfaces can be made into a continuous flat surface.

  Therefore, if the method for forming the conductive plug 112 is applied to the method for forming the second conductive plug 91 (see FIG. 28C), the flatness of the capacitor dielectric film 98a is improved, and the capacitor dielectric Ferroelectric properties such as the amount of residual polarization charge of the body film 98a can be improved.

  Although the copper film 130 is formed in this example, the polished surface can be made flat as described above even if a tungsten film or a polysilicon film is formed instead.

  The following additional notes are disclosed for each embodiment described above.

(Appendix 1) Forming a capacitor having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film above the semiconductor substrate;
Forming an insulating film on the capacitor;
Forming a hole reaching the upper electrode in the insulating film;
Forming a first barrier film on the inner surface of the hole and the surface of the upper electrode exposed from the hole;
Forming a second barrier film having a higher oxygen concentration than the first barrier film on the first barrier film;
Forming a conductive film above the second barrier film and filling the holes;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 2) In the manufacturing method of the semiconductor device of Additional remark 1,
A method of manufacturing a semiconductor device, wherein the second barrier film is formed by oxidizing the surface of the first barrier film.

(Appendix 3) In the method for manufacturing a semiconductor device according to Appendix 1 or Appendix 2,
The method of manufacturing a semiconductor device, wherein the second barrier film is thinner than the first barrier film.

(Appendix 4) In the method for manufacturing a semiconductor device according to any one of Appendix 1 to Appendix 3,
The first barrier film is a TiN film;
The method for manufacturing a semiconductor device, wherein the second barrier film is a TiON film.

(Supplementary Note 5) In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 4,
A method of manufacturing a semiconductor device, further comprising: forming a third barrier film having an oxygen concentration lower than that of the second barrier film on the second barrier film before filling the holes.

(Additional remark 6) In the manufacturing method of the semiconductor device of Additional remark 5,
The semiconductor device manufacturing method, wherein the third barrier film is made of the same material as the first barrier film.

(Appendix 7) a semiconductor substrate;
A capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film;
An insulating film formed on the capacitor and having a hole reaching the upper electrode;
A first barrier film formed on the inner surface of the hole and on the surface of the upper electrode in the hole;
A second barrier film formed on the first barrier film and having a higher oxygen concentration than the first barrier film;
A conductive film formed above the second barrier film and burying the contact hole;
A semiconductor device comprising:

(Appendix 8) In the semiconductor device according to Appendix 7,
The semiconductor device, wherein the second barrier film is thinner than the first barrier film.

(Supplementary Note 9) In the semiconductor device according to Supplementary Note 7 or Supplementary Note 8,
The first barrier film is a TiN film;
The semiconductor device, wherein the second barrier film is a TiON film.

(Supplementary Note 10) In the semiconductor device according to any one of Supplementary Notes 7 to 9,
A semiconductor device, further comprising a third barrier film formed between the second barrier film and the conductive film and having an oxygen concentration lower than that of the second barrier film.

(Supplementary note 11) In the semiconductor device according to supplementary note 10,
The semiconductor device according to claim 3, wherein the third barrier film is made of the same material as the first barrier film.

FIGS. 1A and 1B are cross-sectional views (part 1) showing a method for manufacturing a sample of a ferroelectric capacitor used in the investigation. FIGS. 2A and 2B are sectional views (No. 2) showing a method for manufacturing a sample of a ferroelectric capacitor used in the investigation. FIGS. 3A and 3B are cross-sectional views (part 3) showing a method for producing a ferroelectric capacitor sample used in the investigation. FIG. 4 is a cross-sectional view (No. 4) showing a method for producing a ferroelectric capacitor sample used in the investigation. FIG. 5 is a wafer map obtained by inspecting a sample with a defect inspection apparatus. FIG. 6 is a planar image obtained by observing one of the defects in FIG. 5 by SEM. FIG. 7 is a view drawn based on a cross-sectional TEM image of a portion in which the bulge is confirmed in FIG. 8A to 8C are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the first embodiment. 9A to 9C are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 10A and 10B are cross-sectional views (part 3) in the course of manufacturing the semiconductor device according to the first embodiment. 11A and 11B are cross-sectional views (part 4) in the course of manufacturing the semiconductor device according to the first embodiment. 12A and 12B are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 13A and 13B are cross-sectional views (part 6) in the middle of manufacturing the semiconductor device according to the first embodiment. 14A and 14B are cross-sectional views (part 7) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 15A and 15B are cross-sectional views (part 8) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 16A and 16B are cross-sectional views (part 9) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 17A and 17B are cross-sectional views (part 10) in the middle of the manufacture of the semiconductor device according to the first embodiment. 18A and 18B are cross-sectional views (part 11) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 19A and 19B are cross-sectional views (part 12) in the middle of manufacturing the semiconductor device according to the first embodiment. 20A and 20B are cross-sectional views (No. 13) in the course of manufacturing the semiconductor device according to the first embodiment. 21A and 21B are cross-sectional views (part 14) in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a cross-sectional view (No. 15) of the semiconductor device according to the first embodiment while the semiconductor device is being manufactured. FIG. 23 is a cross-sectional view (No. 16) of the semiconductor device according to the first embodiment while the semiconductor device is being manufactured. 24A and 24B are cross-sectional views of samples used in the first embodiment of the present invention. FIGS. 25A and 25B are graphs obtained by investigating the concentration of each element in the sample of the first embodiment by SIMS. FIGS. 26A to 26C are diagrams showing the results obtained by investigating how the composition of the titanium nitride film depends on the slot number by the RBS analysis. FIG. 27 is a graph obtained by investigating the barrier property of the oxynitride film by SIMS. 28A to 28C are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the second embodiment. 29A to 29C are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the second embodiment. 30A to 30C are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the second embodiment. 31A to 31C are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device according to the second embodiment. 32A and 32B are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device according to the second embodiment. FIGS. 33A and 33B are cross-sectional views (part 6) of the semiconductor device according to the second embodiment during manufacture. 34A and 34B are cross-sectional views (part 7) in the middle of manufacturing the semiconductor device according to the second embodiment. FIGS. 35A and 35B are cross-sectional views (part 8) in the middle of manufacturing the semiconductor device according to the second embodiment. FIGS. 36A and 36B are cross-sectional views (part 9) in the middle of the manufacture of the semiconductor device according to the second embodiment. 37A and 37B are cross-sectional views (part 10) in the middle of the manufacture of the semiconductor device according to the second embodiment. 38A and 38B are cross-sectional views (part 11) in the middle of the manufacture of the semiconductor device according to the second embodiment. FIGS. 39A and 39B are cross-sectional views (part 12) in the course of manufacturing the semiconductor device according to the second embodiment. FIG. 40 is a cross-sectional view (No. 13) of the semiconductor device according to the second embodiment during manufacture. FIG. 41 is a cross-sectional view (No. 14) of the semiconductor device according to the second embodiment while the semiconductor device is being manufactured. FIG. 42 is a cross-sectional view (No. 15) of the semiconductor device according to the second embodiment while the semiconductor device is being manufactured. 43A and 43B are cross-sectional views (part 1) in the middle of manufacturing the conductive plug according to the third embodiment. 44A and 44B are cross-sectional views (part 4) in the middle of manufacturing the conductive plug according to the third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 30, 40 ... Silicon substrate, 2 ... 1st interlayer insulation film, 3 ... Adhesion film | membrane, 4 ... 1st electrically conductive film, 4a ... Lower electrode, 5 ... Ferroelectric film, 5a ... Capacitor dielectric film, 6 ... 2nd conductive film, 6a ... Upper electrode, 7 ... 1st alumina film, 8 ... 2nd interlayer insulation film, 8a, 8b ... 1st and 2nd hole, 9 ... 2nd alumina film, DESCRIPTION OF SYMBOLS 10 ... Cap insulating film, 12 ... Barrier film, 13 ... Tungsten film, 15 ... Conductive plug, 17 ... Swell, 31 ... Element isolation insulating film, 32 ... p well, 33 ... Gate insulating film, 34 ... Gate electrode, 35a 35b, first and second source / drain extensions, 36a, 36b, first and second source / drain regions, 37, insulating spacers, 38, refractory silicide layer, 41, cover insulating film, 42,. First interlayer insulating film 42a. , 43 ... first conductive plug, 44 ... silicon oxide film, 45 ... antioxidation insulating film, 46 ... insulating adhesion film, 47 ... lower electrode adhesion film, 48 ... first conductive film, 49 ... first. 1 Ferroelectric film 50... Second ferroelectric film 51. Second conductive film 52. Conductive protective film 53. Hard mask 54 54 Iridium oxide film 55. Titanium nitride film 57 ... 1st resist pattern, 61 ... Lower electrode, 62 ... Capacitor dielectric film, 63 ... Upper electrode, 64 ... Silicon oxide film, 64a ... Hole, 65 ... 1st alumina film, 67-69 ... 1st-1st 3 ... barrier film 70 ... second alumina film 71 ... second interlayer insulating film 71a-71c ... first to third holes 72 ... third alumina film 73 ... cap insulating film 74 ... Conductive film for plug, 75 ... tungsten film, 77 ... second conductive Plugs 78 to 62 ... 1st to 5th layer metal wiring, 83 to 86 ... 3rd to 6th interlayer insulating films, 87, 88 ... 1st and 2nd passivation films, 91 ... 2nd conductive plugs , 92 ... Antioxidation insulating film, 93 ... Second interlayer insulating film, 93a ... First hole, 94 ... Base conductive film, 95 ... Crystalline conductive film, 96 ... Conductive oxygen barrier film, 97 ... First Conductive film, 98 ... first ferroelectric film, 99 ... second ferroelectric film, 100 ... second conductive film, 101 ... first conductive protective film, 102 ... second conductive hydrogen barrier Membrane 103 ... first hard mask 104 ... second hard mask 110 ... first alumina film 111 ... second alumina film 112 ... third interlayer insulating film 112a, 112b ... second Third hole 113... Third alumina film 114. Cap insulating film 115 Layer metal wirings, 116 ... third conductive plugs, 118-120 ... first to third barrier film, 121 ... conductive film for the plug, 130 ... copper film.

Claims (2)

Forming a capacitor having a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film above the semiconductor substrate;
Forming an insulating film on the capacitor;
Forming a hole reaching the upper electrode in the insulating film;
The inner surface of the hole, and have a conductivity on the surface of the upper electrode exposed from the hole, forming a first barrier film including a titanium nitride,
The first barrier film is subjected to a treatment in the atmosphere or a heat treatment in an atmosphere in which a flow rate ratio of the oxygen gas in a mixed gas of nitrogen gas and oxygen gas is 1% or less. on one of the barrier film, the high oxygen concentration than the first barrier film, have a conductivity, and forming a second barrier film including a titanium oxynitride,
On the second barrier layer, wherein the lower oxygen concentration than the second barrier film, have a conductivity, and forming a third barrier film containing titanium nitride,
Forming a conductive film on the third barrier film and filling the holes;
Only including,
The method for manufacturing a semiconductor device, wherein the first barrier film, the second barrier film, and the third barrier film are barrier films against hydrogen or fluorine . In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second barrier film is thinner than the first barrier film.

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