JP4065351B2 - 欠陥密度の低いＴｉ−Ｓｉ−Ｎ及びＴｉ−Ｂ−Ｎベースの絶縁保護性障壁膜の製法 - Google Patents

欠陥密度の低いＴｉ−Ｓｉ−Ｎ及びＴｉ−Ｂ−Ｎベースの絶縁保護性障壁膜の製法 Download PDF

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JP4065351B2
JP4065351B2 JP30117997A JP30117997A JP4065351B2 JP 4065351 B2 JP4065351 B2 JP 4065351B2 JP 30117997 A JP30117997 A JP 30117997A JP 30117997 A JP30117997 A JP 30117997A JP 4065351 B2 JP4065351 B2 JP 4065351B2
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film
layer
silicon
atmosphere
boron
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Japanese (ja)
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JPH10189491A5 (https=
JPH10189491A (ja
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− ピン ル ジオン
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テキサス インスツルメンツ インコーポレイテツド
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Priority claimed from US08/784,657 external-priority patent/US6017818A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP30117997A 1996-10-31 1997-10-31 欠陥密度の低いＴｉ−Ｓｉ−Ｎ及びＴｉ−Ｂ−Ｎベースの絶縁保護性障壁膜の製法 Expired - Fee Related JP4065351B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2879896P 1996-10-31 1996-10-31
US028798 1997-01-21
US08/784,657 US6017818A (en) 1996-01-22 1997-01-21 Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US784657 1997-01-21

Publications (3)

Publication Number Publication Date
JPH10189491A JPH10189491A (ja) 1998-07-21
JPH10189491A5 JPH10189491A5 (https=) 2005-07-07
JP4065351B2 true JP4065351B2 (ja) 2008-03-26

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JP30117997A Expired - Fee Related JP4065351B2 (ja) 1996-10-31 1997-10-31 欠陥密度の低いＴｉ−Ｓｉ−Ｎ及びＴｉ−Ｂ−Ｎベースの絶縁保護性障壁膜の製法

Country Status (3)

Country Link
JP (1) JP4065351B2 (https=)
KR (1) KR19980032971A (https=)
TW (1) TW363213B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475912B1 (en) 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
WO2007094044A1 (ja) * 2006-02-14 2007-08-23 Fujitsu Limited 半導体装置の製造方法、及び半導体製造装置
JP2008041977A (ja) * 2006-08-08 2008-02-21 Nec Electronics Corp 半導体回路装置の製造方法

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Publication number Publication date
TW363213B (en) 1999-07-01
KR19980032971A (ko) 1998-07-25
JPH10189491A (ja) 1998-07-21

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