KR19980032971A - 낮은 결함밀도의 등각 Ｔｉ－Ｓｉ－Ｎ 및 Ｔｉ－Ｂ－Ｎ 기초장벽막 제조방법 - Google Patents

낮은 결함밀도의 등각 Ｔｉ－Ｓｉ－Ｎ 및 Ｔｉ－Ｂ－Ｎ 기초장벽막 제조방법 Download PDF

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Publication number
KR19980032971A
KR19980032971A KR1019970053690A KR19970053690A KR19980032971A KR 19980032971 A KR19980032971 A KR 19980032971A KR 1019970053690 A KR1019970053690 A KR 1019970053690A KR 19970053690 A KR19970053690 A KR 19970053690A KR 19980032971 A KR19980032971 A KR 19980032971A
Authority
KR
South Korea
Prior art keywords
boron
silicon
film
layer
rich
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019970053690A
Other languages
English (en)
Korean (ko)
Inventor
루지옹-핑
Original Assignee
윌리엄비.켐플러
텍사스인스트루먼츠인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/784,657 external-priority patent/US6017818A/en
Application filed by 윌리엄비.켐플러, 텍사스인스트루먼츠인코포레이티드 filed Critical 윌리엄비.켐플러
Publication of KR19980032971A publication Critical patent/KR19980032971A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019970053690A 1996-10-31 1997-10-20 낮은 결함밀도의 등각 Ｔｉ－Ｓｉ－Ｎ 및 Ｔｉ－Ｂ－Ｎ 기초장벽막 제조방법 Withdrawn KR19980032971A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2879896P 1996-10-31 1996-10-31
US60/028798 1996-10-31
US8/784657 1997-01-21
US08/784,657 US6017818A (en) 1996-01-22 1997-01-21 Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density

Publications (1)

Publication Number Publication Date
KR19980032971A true KR19980032971A (ko) 1998-07-25

Family

ID=26704095

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970053690A Withdrawn KR19980032971A (ko) 1996-10-31 1997-10-20 낮은 결함밀도의 등각 Ｔｉ－Ｓｉ－Ｎ 및 Ｔｉ－Ｂ－Ｎ 기초장벽막 제조방법

Country Status (3)

Country Link
JP (1) JP4065351B2 (https=)
KR (1) KR19980032971A (https=)
TW (1) TW363213B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475912B1 (en) 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
WO2007094044A1 (ja) * 2006-02-14 2007-08-23 Fujitsu Limited 半導体装置の製造方法、及び半導体製造装置
JP2008041977A (ja) * 2006-08-08 2008-02-21 Nec Electronics Corp 半導体回路装置の製造方法

Also Published As

Publication number Publication date
TW363213B (en) 1999-07-01
JPH10189491A (ja) 1998-07-21
JP4065351B2 (ja) 2008-03-26

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Legal Events

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PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000