JP4050628B2 - Voltage level shifter and display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage level shifter and a display device.
[0002]
[Prior art]
In a display device such as an organic EL (electroluminescence) display device or a liquid crystal display device, pixels each having a display element and a pixel circuit are arranged in a matrix on a substrate, and the pixels are arranged by a voltage level shifter, a buffer, a shift register, or the like. Display is performed by driving with the configured driving circuit. In such a display device, the driver circuit may be formed over the previous substrate.
[0003]
For example, in Patent Document 1 below, in a voltage level shifter used in an interface circuit of an active matrix type liquid crystal display device, all transistors (MOSFETs) constituting the voltage level shifter have the same conductivity type. Are listed.
[0004]
However, the present inventors have found that the voltage level shifter described in Patent Document 1 is not always sufficient from the viewpoint of efficiently amplifying a signal.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-24502
[0006]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and an object thereof is to provide a voltage level shifter configured by transistors of the same conductivity type and capable of efficiently amplifying signals, and a display device using the voltage level shifter. .
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, the first and second transistors sequentially connected in series to the first power supply terminal, the first input terminal to which the first input signal is supplied, and the control of the second transistor. A third transistor connected between the first transistor and a control terminal connected to a second power supply terminal; a first terminal connected to the first transistor of the second transistor; and the control terminal of the second transistor; A first capacitor connected between the first power supply terminal, fourth and fifth transistors sequentially connected in series to the first power supply terminal, and a second input signal complementary to the first input signal. A sixth transistor connected between the second input terminal connected to the control terminal of the fifth transistor and having a control terminal connected to the second power supply terminal; and the fourth transistor of the fifth transistor. A second capacitor connected between the connected second terminal and the control terminal of the fifth transistor, wherein the first to sixth transistors have the same conductivity type, and the first terminal A voltage level shifter is provided, wherein the voltage level shifter is connected to a control terminal of a fourth transistor, and the second terminal is connected to a control terminal of the first transistor.
[0008]
According to a second aspect of the present invention, a substrate, a drive circuit provided on the substrate and provided with a voltage level shifter according to the first side surface, and arranged in a matrix on the substrate and driven by the drive circuit A display device comprising a plurality of pixels is provided.
[0009]
In the first and second aspects, the first and second transistors may be connected in series between the first power supply terminal and the second power supply terminal. The fourth and fifth transistors may be connected in series between the first power supply terminal and the second power supply terminal.
[0010]
Alternatively, the first and second transistors may be connected in series between the first power supply terminal and the first input terminal. The fourth and fifth transistors may be connected in series between the first power supply terminal and the second input terminal.
[0011]
The voltage level shifter includes a seventh transistor connected between the first terminal and the second transistor side terminal of the first transistor and having a control terminal connected to the second input terminal, a second terminal, and a fourth transistor. An eighth transistor having a control terminal connected to the first input terminal may be further included between the transistor and a terminal on the fifth transistor side. In this case, the conductivity types of the seventh and eighth transistors may be equal to the conductivity types of the first to sixth transistors.
[0012]
The voltage level shifter may have at least one of the first and second terminals as an output terminal.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the same or similar component, and the overlapping description is abbreviate | omitted.
[0014]
FIG. 1 is a block diagram schematically showing a display device according to the first embodiment of the present invention. In FIG. 1, as an example, the display device 1 is drawn as an organic EL display device.
[0015]
A display device 1 shown in FIG. 1 includes an insulating substrate 2 such as glass, and pixels 3 are arranged in a matrix on one main surface of the substrate 2. These pixels 3 define a display area 4 on the main surface of the substrate 2. A scanning signal line driver 5a and a video signal line driver 5b are arranged as drive circuits in a region outside the display region 4, that is, a peripheral region.
[0016]
Each pixel 3 includes a selection switch Sw, a driving transistor Tr, a capacitor C, and an organic EL element 31 as a display element in this example. The selection switch Sw arranged in each pixel 3 has a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel (active matrix type). The selection switch Sw and the driving transistor Tr are, for example, p-channel thin film transistors. The selection switch Sw is connected between the gate of the driving transistor Tr and the video signal line 7, and the gate of the selection switch Sw is connected to the scanning signal line 6. The driving transistor Tr and the organic EL element 31 are connected in series between the power supply wiring 8 and GND, and the capacitor C is connected between the source of the driving transistor Tr (power supply wiring 8 side) and the gate. It is connected. The selection switch Sw, the driving transistor Tr, and the capacitor C constitute a pixel circuit.
[0017]
The scanning signal line driver 5a includes a vertical shift register 50a, a level shifter (voltage level shifter) 51a, and a buffer circuit (not shown). The vertical shift register 50a includes a plurality of flip-flops, and the scanning signal line 6 is connected to the output terminal of each stage flip-flop. The scanning signal line driver 5a amplifies the voltage of the vertical clock signal (CKV) and the vertical scanning pulse (STV) input from the outside with the level shifter 51a and the buffer circuit, and then outputs them to the vertical shift register 50a. The vertical shift register 50a outputs vertical scanning pulses as scanning signals to the corresponding scanning signal lines 6 while shifting the vertical scanning pulses to the next stage one by one in synchronization with the vertical clock signal.
[0018]
The video signal line driver 5b includes a horizontal shift register 50b, a video signal bus 52, an analog switch 53, and a level shifter (voltage level shifter) 51b. The video signal line driver 5b amplifies the voltage of the horizontal clock signal (CKH) and the horizontal scanning pulse (STH) input from the outside with the level shifter 51b, and then outputs them to the horizontal shift register 50b. The horizontal shift register 50b outputs the horizontal scanning pulse (STH) to the corresponding analog switch 53 while shifting the horizontal scanning pulse (STH) to the next stage one by one in synchronization with the horizontal clock signal (CKH). When the analog switch 53 is turned on by a horizontal scanning pulse output from each output terminal of the shift register 50b, the video signal bus 52 and the video signal line 7 are brought into conduction, so that the video signal (DATA) supplied to the video signal bus 52 is electrically connected. Are sampled on the corresponding video signal line 7.
[0019]
FIG. 2 is a circuit diagram showing the voltage level shifter according to the first embodiment of the present invention. In FIG. 2, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, in the display device 1 shown in FIG. 1, at least one of the drivers 5a and 5b adopts the circuit configuration shown in FIG.
[0020]
The voltage level shifter 51 includes transistors having the same conductivity type, here, p-channel thin film transistors Tr1 to Tr6 and capacitors C1 and C2. The voltage level shifter 51 is configured to amplify the voltage of complementary input signals supplied from the input terminal IN1 and the input terminal IN2 and output the amplified signals from the nodes N3 and N4.
[0021]
That is, the transistors Tr1 and Tr2 are connected in series between a power supply terminal VDD that supplies a power supply voltage and a power supply terminal GND that supplies a ground voltage. The transistor Tr3 is connected between an input terminal IN1 to which an input signal is supplied and the gate of the transistor Tr2, and the gate of the transistor Tr3 is connected to a power supply terminal GND for supplying a ground voltage. The capacitor C1 is connected between the source and gate of the transistor Tr2.
[0022]
The transistors Tr4 and Tr5 are connected in series between a power supply terminal VDD that supplies a power supply voltage and a power supply terminal GND that supplies a ground voltage. The transistor Tr6 is connected between an input terminal IN2 to which an input signal complementary to the previous input signal is supplied and the gate of the transistor Tr5, and the gate of the transistor Tr6 supplies a ground voltage. It is connected to the. The capacitor C2 is connected between the source and gate of the transistor Tr5.
[0023]
Further, the gate of the transistor Tr1 is connected to the source of the transistor Tr5, and the gate of the transistor Tr4 is connected to the source of the transistor Tr2.
[0024]
The buffer circuit 54 includes transistors having the same conductivity type, here, p-channel thin film transistors Tr9 to Tr11, and a capacitor C3. The buffer circuit 54 is configured to be supplied with complementary signals from the nodes N3 and N4 and to output a voltage-amplified output signal from the output terminal OUT.
[0025]
That is, the transistors Tr9 and Tr10 are connected in series between a power supply terminal VDD that supplies a power supply voltage and a power supply terminal GND that supplies a ground voltage. The transistor Tr11 is connected between the node N3 and the gate of the transistor Tr10, and the gate of the transistor Tr11 is connected to a power supply terminal GND that supplies a ground voltage. The gate of the transistor Tr9 is connected to the node N4, and the capacitor C3 is connected between the source and gate of the transistor Tr10.
[0026]
Next, the operation of the voltage level shifter 51 will be described.
The input signal supplied to the input terminals IN1 and IN2 is, for example, a horizontal clock signal or a vertical clock signal. Consider a state in which input signals that repeat predetermined High level and Low level signals in a predetermined cycle are complementarily input to the input terminals IN1 and IN2, respectively.
[0027]
When a low level signal is supplied to the input terminal IN1 and a high level signal is supplied to the input terminal IN2 from a state where the transistors Tr1 and Tr5 are nonconductive and the transistors Tr2 and Tr4 are conductive at a certain timing, the transistor Tr3 is nonconductive. In this state, the transistor Tr6 is in a conducting state. In this state, the node N3 outputs a signal having a magnitude substantially equal to the ground voltage, and the node N4 outputs a signal having a magnitude substantially equal to the power supply voltage.
[0028]
Next, consider a case where, from this state, the input signal supplied to the input terminal IN1 is switched to the High level and the input signal supplied to the input terminal IN2 is switched to the Low level.
[0029]
When the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the gate-source voltage Vgs (= gate potential-source potential) of the transistor Tr3 decreases, and the potential of the node N1 increases. When the potential of the node N1 increases, the gate-source voltage Vgs of the transistor Tr2 increases, and the transistor Tr2 approaches the non-conductive state from the conductive state.
[0030]
On the other hand, when the input signal supplied to the input terminal IN2 is switched from the High level to the Low level, the gate-source voltage Vgs of the transistor Tr6 increases, and the transistor Tr6 approaches the non-conductive state from the conductive state. Until the transistor Tr6 is completely turned off, a current can flow between the source and drain of the transistor Tr6, so that the potential of the node N2 drops. As a result, the gate-source voltage Vgs of the transistor Tr5 decreases, and the transistor Tr5 approaches the conductive state from the non-conductive state.
[0031]
When the transistor Tr5 approaches the conducting state, the potential of the node N4 decreases. As a result, the gate-source voltage Vgs of the transistor Tr1 decreases, and the transistor Tr1 approaches the conductive state from the non-conductive state.
[0032]
As described above, since the transistor Tr2 is close to the non-conductive state, the potential of the node N3 increases when the transistor Tr1 approaches the conductive state. As a result, the gate-source voltage Vgs of the transistor Tr4 increases, and the transistor Tr4 approaches the non-conductive state from the conductive state.
[0033]
When the transistor Tr4 approaches the non-conductive state, the potential of the node N4 further decreases, and the change of the transistor Tr1 from the non-conductive state to the conductive state is promoted. As the change of the transistor Tr1 from the non-conductive state to the conductive state proceeds, the potential of the node N3 further increases, and the change of the transistor Tr4 from the conductive state to the non-conductive state is promoted. Thus, eventually, the transistor Tr1 is almost completely turned on, and the transistor Tr4 is almost completely turned off.
[0034]
By the way, when the transistor Tr4 changes from the conductive state to the nonconductive state in accordance with the switching of the input signals to the terminal IN1 and the terminal IN2, the source potential of the transistor Tr5 decreases. Therefore, when the capacitor C2 and the transistor Tr6 are not provided, the output signal voltage output from the node N4 cannot be set to a sufficiently low value, or the Low level input signal input to the terminal IN2 is set to a lower voltage. There is a need.
[0035]
For example, when the low-level input signal voltage VinL input to the terminal IN2 is higher than the threshold voltage Vth (Vth is a negative value) of the transistor Tr5, the gate-source voltage Vgs of the transistor Tr5 is equal to the threshold voltage Vth. It changes and becomes constant at that value. In this case, the magnitude of the output signal output from the node N4 is the difference VinL−Vth (> 0) between the low-level input signal VinL and the threshold voltage Vth. That is, the output signal output from the node N4 cannot be made equal to the ground voltage supplied from the ground terminal GND. In order to make the output signal output from the node N4 equal to the ground voltage supplied from the ground terminal GND, the low level input signal must be set to a lower voltage.
[0036]
On the other hand, in the structure of FIG. 2 in which the capacitor C2 and the transistor Tr6 are provided, when the signal input to the terminal IN2 is switched from the high level to the low level, the gate potential of the transistor Tr5 becomes almost equal to the low level signal potential. In addition, the transistor Tr6 approaches the non-conductive state from the conductive state. Therefore, due to the effect of capacitive coupling by the capacitor C2, the potential of the node N2 separated from the terminal IN2 can be further lowered as the source potential of the transistor Tr5 decreases, and the gate potential of the transistor Tr5 also decreases. That is, even when the source potential of the transistor Tr5 is lowered, the gate-source voltage Vgs of the transistor Tr5 is maintained at a sufficiently low value. Therefore, the output signal output from the node N4 can be made substantially equal to the ground voltage supplied from the ground terminal GND without setting the low level input signal to a lower voltage.
[0037]
The output signal output from the node N3 can be made equal to the power supply voltage supplied from the power supply terminal VDD. That is, the transistor Tr3 changes from a non-conduction state to a conduction state in accordance with switching of input signals to the terminals IN1 and IN2. Therefore, the gate of the transistor Tr2 has the same potential as the high level signal, and the gate-source voltage Vgs of the transistor Tr2 becomes sufficiently high. Therefore, the transistor Tr2 is finally turned off. In this way, an output signal having a magnitude substantially equal to the power supply voltage is finally output from the node N3.
[0038]
As is apparent from the above, the signal can be efficiently amplified when the circuit configuration of FIG. 2 is adopted. When the input signal supplied to the input terminal IN1 is switched from the High level to the Low level and the input signal supplied to the input terminal IN2 is switched from the Low level to the High level, the operation from the node N3 is completely reversed by the operation reverse to the above. An output signal having a magnitude equal to the ground voltage can be output, and an output signal having a magnitude equal to the power supply voltage can be output from the node N4.
[0039]
The complementary output signals output from the nodes N3 and N4 are then supplied to the buffer circuit 54. The buffer circuit 4 generates an output signal to be supplied to the shift register from these signals as follows.
[0040]
When the node N3 outputs an output signal having a magnitude equal to the power supply voltage and the node N4 outputs an output signal having a magnitude equal to the ground voltage, the gate-source voltage Vgs of the transistors Tr9 and Tr11 is sufficiently low, The transistors Tr9 and Tr11 are turned on. As a result, the gate-source voltage Vgs of the transistor Tr10 becomes higher than the threshold voltage Vth, and the transistor Tr10 is turned off. Therefore, the magnitude of the output signal output from the output terminal OUT is equal to the power supply voltage supplied from the power supply terminal VDD.
[0041]
When the node N3 outputs an output signal having a magnitude equal to the ground voltage and the node N4 outputs an output signal having a magnitude equal to the power supply voltage, the gate-source voltage Vgs of the transistor Tr9 is high, and the transistor Tr9 is not turned on. It approaches the conduction state. Further, the gate-source voltage Vgs of the transistor Tr11 increases, and the gate potential of the transistor Tr10 decreases. In this process, the source potential of the transistor Tr10 decreases, and accordingly, the gate potential of the transistor Tr10 also decreases. That is, even when the source potential of the transistor Tr10 is lowered, the gate-source voltage Vgs of the transistor Tr10 is maintained at a sufficiently low value. Therefore, the transistor Tr10 becomes almost completely conductive, and the magnitude of the output signal output from the output terminal OUT is equal to the ground voltage supplied from the ground terminal GND.
[0042]
FIG. 3 is a graph showing an example of level shifting that can be performed by the circuit of FIG. In the figure, the horizontal axis indicates time, and the vertical axis indicates voltage. In the figure, reference characters V (IN), V (N1), V (N3), and V (OUT) indicate the voltages of the terminal IN1, the nodes N1, N3, and the terminal OUT, respectively. Note that the data shown in FIG. 3 is obtained when the low-level and high-level input signals supplied to the terminals IN1 and IN2 are 0 V and 3 V, respectively, and the power supply voltage supplied to the power supply terminal VDD is 10 V. It is a thing. As shown in FIG. 3, according to the circuit of FIG. 2, the signal can be efficiently amplified.
[0043]
The nodes N1 and N2 are disconnected from the input terminals when the transistors Tr2 and Tr5 are switched to the conductive state, and operate by capacitive coupling with the output terminals N3 and N4. The change of N4 and the gate terminals N1 and N2 of Tr2 and Tr5 have a relationship of accelerating the change. Therefore, even when a voltage level shifter is configured by a single conductivity type TFT, it can operate at a higher speed than the conventional one. This voltage level shifter can be integrally formed on the glass substrate simultaneously with the pixel circuit, and a display device with good display timing can be achieved.
[0044]
In addition, since no current flows between the power supply and GND except at the moment when the signal High / Low is switched, heat generation from the drive circuit can be suppressed, and thermal deterioration of the EL element can be prevented. . Further, the present invention is not limited to application to an organic EL display device, but can be applied to all active matrix display devices. For example, when applied to a liquid crystal display device, the influence on the liquid crystal layer is prevented. Can do.
[0045]
Next, a second embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing a voltage level shifter according to the second embodiment of the present invention. In FIG. 4, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 4 can be employed in at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0046]
In the circuit shown in FIG. 4, the drain of the transistor Tr2 is connected to the input terminal IN1 instead of the second power supply terminal GND, and the drain of the transistor Tr5 is connected to the input terminal IN2 instead of the second power supply terminal GND. Is similar to the circuit shown in FIG.
[0047]
When the structure shown in FIG. 4 is adopted, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly as described below.
[0048]
First, when the transistors Tr1 and Tr5 are in a non-conducting state and the transistors Tr2 and Tr4 are in a conducting state at a certain timing, a state in which a low level input signal is supplied to the input terminal IN1 and a high level input signal is supplied to the input terminal IN2. Think. In this state, the transistors Tr1, Tr3, Tr5 are in a non-conductive state, and the transistors Tr2, Tr4, Tr6 are in a conductive state. In this state, the node N3 outputs a signal having a magnitude approximately equal to the low level input signal, and the node N4 outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD.
[0049]
Next, consider a case where, from this state, the input signal supplied to the input terminal IN1 is switched to the High level and the input signal supplied to the input terminal IN2 is switched to the Low level.
[0050]
When the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the gate-source voltage Vgs of the transistor Tr3 decreases and the potential of the node N1 increases. When the potential of the node N1 increases, the gate-source voltage Vgs of the transistor Tr2 increases, and the transistor Tr2 approaches the non-conductive state from the conductive state. Here, since the drain of the transistor Tr2 is connected to the input terminal IN1 in the circuit of FIG. 4, in the process in which the transistor Tr2 changes from the conductive state to the nonconductive state, the voltage between the source and drain of the transistor Tr2 (= source (Potential-drain potential) is lower than that of the circuit of FIG. Therefore, according to the circuit shown in FIG. 4, the change from the conducting state to the non-conducting state of the transistor Tr2 proceeds more quickly than in the circuit shown in FIG.
[0051]
On the other hand, when the input signal supplied to the input terminal IN2 is switched from the High level to the Low level, the gate-source voltage Vgs of the transistor Tr6 increases, and the transistor Tr6 approaches the non-conductive state from the conductive state. Until the transistor Tr6 is completely turned off, a current can flow between the source and drain of the transistor Tr6, so that the potential of the node N2 drops. As a result, the gate-source voltage Vgs of the transistor Tr5 decreases, and the transistor Tr5 approaches the conductive state from the non-conductive state. Here, since the drain of the transistor Tr5 is connected to the input terminal IN2 in the circuit of FIG. 4, if the low-level input signal at the input terminal IN2 is smaller than the ground potential supplied from the power supply terminal GND, the transistor Tr5 is In the process of changing from the non-conductive state to the conductive state, the source-drain voltage (= source potential-drain potential) of the transistor Tr5 becomes higher than that of the circuit of FIG. Therefore, according to the circuit shown in FIG. 4, the change from the non-conductive state to the conductive state of the transistor Tr <b> 5 can be advanced more quickly than in the circuit of FIG. 2.
[0052]
As described above, according to the circuit shown in FIG. 4, the change between the non-conductive state and the conductive state of the transistors Tr2 and Tr5 accompanying the switching of the signal level at the input terminals IN1 and IN2 is greater than that in the circuit shown in FIG. It can proceed quickly. Therefore, the change between the non-conductive state and the conductive state of the transistors Tr1 and Tr4 can proceed more rapidly. Therefore, according to the present embodiment, in addition to the effects described in the first embodiment, inversion of the signal level at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly. be able to.
[0053]
FIG. 5 is a graph showing an example of level shifting that can be performed by the circuit of FIG. In the figure, the horizontal axis indicates time, and the vertical axis indicates voltage. In the figure, reference characters V (IN), V (N1), V (N3), and V (OUT) indicate the voltages of the terminal IN1, the nodes N1, N3, and the terminal OUT, respectively. Note that the data shown in FIG. 5 is obtained when the low-level and high-level input signals supplied to the terminals IN1 and IN2 are 0V and 3V, respectively, and the power supply voltage supplied to the power supply terminal VDD is 10V. It is a thing.
[0054]
As shown in FIG. 5, according to the circuit of FIG. 4, a signal can be efficiently amplified. 5 and 3, the circuit shown in FIG. 4 can suppress the time lag of the voltage V (OUT) with respect to the voltage V (IN) as compared with the circuit shown in FIG.
[0055]
Next, a third embodiment of the present invention will be described.
FIG. 6 is a circuit diagram showing a voltage level shifter according to the third embodiment of the present invention. In FIG. 6, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 6 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0056]
The circuit shown in FIG. 6 is the same as the circuit shown in FIG. 4 except that the drain of the transistor Tr10 is connected between the source of the transistor Tr11 and the node N3. By adopting such a structure, the effects described in the first and second embodiments can be obtained, and the buffer circuit 54 can be operated more quickly.
[0057]
FIG. 7 is a graph showing an example of level shifting that can be performed by the circuit of FIG. In the figure, the horizontal axis indicates time, and the vertical axis indicates voltage. In the figure, reference characters V (IN), V (N1), V (N3), and V (OUT) indicate the voltages of the terminal IN1, the nodes N1, N3, and the terminal OUT, respectively. Note that the data shown in FIG. 7 is obtained when the low-level and high-level input signals supplied to the terminals IN1 and IN2 are 0 V and 3 V, respectively, and the power supply voltage supplied to the power supply terminal VDD is 10 V. It is a thing.
[0058]
As shown in FIG. 7, the circuit of FIG. 6 can efficiently amplify the signal. 7 and 5, the circuit shown in FIG. 7 can suppress the time lag of the voltage V (OUT) with respect to the voltage V (IN) compared to the circuit shown in FIG.
[0059]
Next, a fourth embodiment of the present invention will be described.
FIG. 8 is a circuit diagram showing a voltage level shifter according to the fourth embodiment of the present invention. In FIG. 8, voltage level shifters 51-1 and 51-2 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 8 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0060]
The circuit shown in FIG. 8 employs the same configuration as the voltage level shifter 51 shown in FIG. The voltage level shifter 51-2 is the same as the voltage level shifter 51-1 except that the gates of the transistors Tr3 ′ and Tr6 ′ and the sources of the transistors Tr2 ′ and Tr5 ′ are connected to the power supply terminal VSS. The buffer circuit 54 of FIG. 8 is the same as the buffer circuit 54 of FIG. 2 except that the transistor Tr10 is connected between the transistor Tr9 and the power supply terminal VSS, and the gate of the transistor Tr11 is connected to the power supply terminal VSS. It is the same.
[0061]
In the circuit of FIG. 8, nodes N3 and N4 of the voltage level shifter 51-1 are connected to the gates of the transistors Tr2 ′ and Tr5 ′ via the transistors Tr3 ′ and Tr6 ′, and are used as input terminals of the voltage level shifter 51-2. Plays the role of In the circuit of FIG. 8, nodes N3 ′ and N4 ′ serve as output terminals to the buffer circuit 54 of the voltage level shifter 51-2. When such a structure is adopted, the signal can be amplified more efficiently as described below.
[0062]
First, when the transistors Tr1, Tr5, Tr1 ′, Tr5 ′ are in a non-conductive state and the transistors Tr2, Tr4, Tr2 ′, Tr4 ′ are in a conductive state at a certain timing, a low level input signal is input to the input terminal IN1. Consider a state in which a high level input signal is supplied to the input terminal IN2. In this state, the transistors Tr1, Tr3, Tr5, Tr1 ′, Tr3 ′, Tr5 ′ are in a non-conduction state, and the transistors Tr2, Tr4, Tr6, Tr2 ′, Tr4 ′, Tr6 ′ are in a conduction state.
[0063]
In this state, the node N3 outputs a signal having a magnitude substantially equal to the ground voltage, and the node N4 outputs a signal having a magnitude substantially equal to the power supply voltage. The node N3 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VSS, and the node N4 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD.
[0064]
Next, consider a case where, from this state, the input signal supplied to the input terminal IN1 is switched to the High level and the input signal supplied to the input terminal IN2 is switched to the Low level.
[0065]
When the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the node N3 outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD. On the other hand, when the input signal supplied to the input terminal IN2 is switched from the High level to the Low level, the node N4 outputs a signal having a magnitude approximately equal to the ground voltage. Accordingly, the node N3 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD, and the node N4 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VSS.
[0066]
In this way, in the circuit of FIG. 8, the voltage level shifter 51-1 converts the High level input signal to a higher value and outputs the Low level input signal to the voltage level shifter 51-2 without converting. That is, a more amplified input signal is supplied to the voltage level shifter 51-2. Therefore, compared with the circuit shown in FIG. 2, a more amplified output signal can be supplied to the buffer circuit 54, and a greater amplification effect can be obtained.
[0067]
In the circuit of FIG. 8, since the nodes N3 and N4 are used as the output terminals of the voltage level shifter 51-1, the signal output from the voltage level shifter 51-1 is hardly affected by the threshold value. Therefore, stable operation is possible with the circuit of FIG.
[0068]
Next, a fifth embodiment of the present invention will be described.
FIG. 9 is a circuit diagram showing a voltage level shifter according to the fifth embodiment of the present invention. In FIG. 9, voltage level shifters 51-1 and 51-2 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 9 can be adopted by at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0069]
The circuit shown in FIG. 9 employs a configuration similar to that of the voltage level shifter 51 shown in FIG. The voltage level shifter 51-2 is the same as the voltage level shifter 51-1 except that the gates of the transistors Tr3 ′ and Tr6 ′ and the sources of the transistors Tr2 ′ and Tr5 ′ are connected to the power supply terminal VSS. The buffer circuit 54 in FIG. 9 is the same as the buffer circuit 54 in FIG. 2 except that the transistor Tr10 is connected between the transistor Tr9 and the power supply terminal VSS, and the gate of the transistor Tr11 is connected to the power supply terminal VSS. It is the same.
[0070]
In the circuit of FIG. 9, nodes N1 and N2 of the voltage level shifter 51-1 are connected to the gates of the transistors Tr2 ′ and Tr5 ′ via the transistors Tr3 ′ and Tr6 ′, and are used as input terminals of the voltage level shifter 51-2. Plays the role of In the circuit of FIG. 9, the nodes N3 ′ and N4 ′ serve as output terminals to the buffer circuit 54 of the voltage level shifter 51-2. When such a structure is adopted, the signal can be amplified more efficiently as described below.
[0071]
First, when the transistors Tr1, Tr5, Tr1 ′, Tr5 ′ are in a non-conductive state and the transistors Tr2, Tr4, Tr2 ′, Tr4 ′ are in a conductive state at a certain timing, a low level input signal is input to the input terminal IN1. Consider a state in which a high level input signal is supplied to the input terminal IN2. In this state, the transistors Tr1, Tr3, Tr5, Tr1 ′, Tr3 ′, Tr5 ′ are in a non-conduction state, and the transistors Tr2, Tr4, Tr6, Tr2 ′, Tr4 ′, Tr6 ′ are in a conduction state.
[0072]
In this state, the node N1 outputs a signal (negative value) having a magnitude approximately equal to the difference between the high level input signal and the power supply voltage supplied from the power supply terminal VDD, and the node N2 outputs a high level input signal. Output signals of equal magnitude. The node N3 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VSS, and the node N4 ′ outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD.
[0073]
Next, consider a case where, from this state, the input signal supplied to the input terminal IN1 is switched to the High level and the input signal supplied to the input terminal IN2 is switched to the Low level.
[0074]
When the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the transistor Tr3 is turned on, so that the node N1 outputs a signal having a magnitude equal to that of the High level input signal.
[0075]
On the other hand, when the input signal supplied to the input terminal IN2 is switched from the High level to the Low level, the gate-source voltage Vgs of the transistor Tr6 increases, and the transistor Tr6 changes from the conductive state to the non-conductive state. At this time, the potential of the node N4 also changes from the ground voltage supplied from the power supply terminal GND to a value substantially equal to the power supply voltage supplied from the power supply terminal VDD. As described in the first embodiment, at the time of this change, as the potential of the node N4 decreases, the gate potential of the transistor Tr5 also decreases. Therefore, the node N2 outputs a signal (negative value) having a magnitude approximately equal to the difference between the high level input signal and the power supply voltage supplied from the power supply terminal VDD.
[0076]
As described above, in the circuit of FIG. 9, the voltage level shifter 51-1 converts the Low level input signal to a lower value and outputs the High level input signal to the voltage level shifter 51-2 without converting. That is, a more amplified input signal is supplied to the voltage level shifter 51-2. Therefore, in the voltage level shifter 51-2, the potential of the power supply terminal VSS can be made lower than the ground potential. Therefore, compared with the circuit shown in FIG. 2, a more amplified output signal can be supplied to the buffer circuit 54, and a greater amplification effect can be obtained.
[0077]
FIG. 10 is a graph showing an example of level shifting that can be performed by the circuit of FIG. In the figure, the horizontal axis indicates time, and the vertical axis indicates voltage. In the figure, reference symbols V (IN), V (N1), V (N1 ′), V (N3 ′), and V (OUT) are a terminal IN1, nodes N1, N1 ′, N3 ′, and a terminal, respectively. The voltage of OUT is shown. Note that the data shown in FIG. 10 indicates that the low level and high level input signals supplied to the terminals IN1 and IN2 are 0 V and 3 V, respectively, the power supply voltage supplied to the power supply terminal VDD is 10 V, and the power supply terminal VSS is supplied. This is obtained when the power supply voltage to be supplied is -5V.
[0078]
As shown in FIG. 10, according to the circuit of FIG. 9, the signal can be efficiently amplified. Further, as is apparent from FIGS. 10 and 3, the circuit shown in FIG. 9 can provide a larger amplification effect than the circuit shown in FIG.
[0079]
Next, a sixth embodiment of the present invention will be described.
FIG. 11 is a circuit diagram showing a voltage level shifter according to the sixth embodiment of the present invention. In FIG. 11, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 11 can be adopted by at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0080]
The circuit shown in FIG. 11 is the circuit shown in FIG. 2 except that the transistor Tr7 is interposed between the drain of the transistor Tr1 and the node N3, and the transistor Tr8 is interposed between the drain of the transistor Tr4 and the node N4. It is the same.
[0081]
On the other hand, when the structure shown in FIG. 11 is adopted, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly as described below.
[0082]
First, when the transistors Tr1 and Tr5 are in a non-conducting state and the transistors Tr2 and Tr4 are in a conducting state at a certain timing, a state in which a low level input signal is supplied to the input terminal IN1 and a high level input signal is supplied to the input terminal IN2. Think. In this state, the transistors Tr1, Tr3, Tr5, Tr7 are in a non-conductive state, and the transistors Tr2, Tr4, Tr6, Tr8 are in a conductive state. In this state, the node N3 outputs a signal having a magnitude substantially equal to the ground voltage supplied from the power supply terminal GND, and the node N4 outputs a signal having a magnitude substantially equal to the power supply voltage supplied from the power supply terminal VDD. To do.
[0083]
Next, consider a case where, from this state, the input signal supplied to the input terminal IN1 is switched to the High level and the input signal supplied to the input terminal IN2 is switched to the Low level.
[0084]
When the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the gate-source voltage Vgs of the transistor Tr3 decreases and the potential of the node N1 increases. When the potential of the node N1 increases, the gate-source voltage Vgs of the transistor Tr2 increases, and the transistor Tr2 approaches the non-conductive state from the conductive state.
[0085]
On the other hand, when the input signal supplied to the input terminal IN2 is switched from the High level to the Low level, the gate-source voltage Vgs of the transistor Tr6 increases, and the transistor Tr6 approaches the non-conductive state from the conductive state. Until the transistor Tr6 is completely turned off, a current can flow between the source and drain of the transistor Tr6, so that the potential of the node N2 drops. As a result, the gate-source voltage Vgs of the transistor Tr5 decreases, and the transistor Tr5 approaches the conductive state from the non-conductive state. Here, since the gate of the transistor Tr8 is connected to the input terminal IN1 in the circuit of FIG. 11, as the input signal supplied to the input terminal IN1 is switched from the Low level to the High level, the node N4 and the power supply terminal VDD During this period, it is quickly turned off. Therefore, according to the circuit shown in FIG. 11, a change in the potential at the node N4 accompanying the switching of the signal level at the input terminals IN1 and IN2 can be generated more quickly than in the circuit of FIG.
[0086]
Further, when the potential change at the node N4 occurs promptly, the transistor Tr1 also rapidly changes from the nonconductive state to the conductive state. In addition, the change of the transistor Tr7 from the non-conductive state to the conductive state occurs very quickly. Therefore, according to the circuit shown in FIG. 11, the potential change at the node N <b> 3 due to the switching of the signal level at the input terminals IN <b> 1 and IN <b> 2 can be generated more quickly than in the circuit of FIG. 2.
[0087]
As described above, according to the circuit shown in FIG. 11, the potential change at the nodes N3 and N4 accompanying the switching of the signal level at the input terminals IN1 and IN2 can proceed more rapidly than the circuit shown in FIG. Therefore, according to the present embodiment, in addition to the effects described in the first embodiment, inversion of the signal level at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly. be able to.
[0088]
Next, a seventh embodiment of the present invention will be described.
FIG. 12 is a circuit diagram showing a voltage level shifter according to the seventh embodiment of the present invention. In FIG. 12, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 12 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0089]
The circuit shown in FIG. 12 is the same as the circuit shown in FIG. 4 except that the transistor Tr7 is interposed between the drain of the transistor Tr1 and the node N3, and the transistor Tr8 is interposed between the drain of the transistor Tr4 and the node N4. It is the same. That is, the circuit shown in FIG. 12 corresponds to a circuit in which a part of the circuit configuration shown in FIG. 11 is adopted in the circuit shown in FIG.
[0090]
According to this circuit, both of the effects described in the second and sixth embodiments can be obtained. That is, according to this embodiment, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly.
[0091]
Next, an eighth embodiment of the present invention will be described.
FIG. 13 is a circuit diagram showing a voltage level shifter according to the eighth embodiment of the present invention. In FIG. 13, a voltage level shifter 51 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 13 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0092]
The circuit shown in FIG. 13 is the same as the circuit shown in FIG. 6 except that the transistor Tr7 is interposed between the drain of the transistor Tr1 and the node N3 and the transistor Tr8 is interposed between the drain of the transistor Tr4 and the node N4. It is the same. That is, the circuit shown in FIG. 13 corresponds to a circuit in which a part of the circuit configuration shown in FIG. 11 is adopted in the circuit shown in FIG.
[0093]
According to this circuit, both of the effects described in the third and sixth embodiments can be obtained. That is, according to this embodiment, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly.
[0094]
Next, a ninth embodiment of the present invention will be described.
FIG. 14 is a circuit diagram showing a voltage level shifter according to the ninth embodiment of the present invention. In FIG. 14, voltage level shifters 51-1 and 51-2 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 14 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0095]
The circuit shown in FIG. 14 includes transistors Tr7 and Tr7 ′ interposed between the drain of the transistor Tr1 and the node N3 and between the drain of the transistor Tr1 ′ and the node N3 ′, respectively, and the drain of the transistor Tr4 and the node N4. 9 and the circuit shown in FIG. 9 except that transistors Tr8 and Tr8 ′ are interposed between the drain of the transistor Tr4 ′ and the node N4 ′. That is, the circuit shown in FIG. 14 corresponds to the circuit shown in FIG. 9 in which a part of the circuit configuration shown in FIG. 11 is adopted.
[0096]
According to this circuit, both of the effects described in the fifth and sixth embodiments can be obtained. That is, according to the present embodiment, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly, and a greater amplification effect can be obtained.
[0097]
Next, a tenth embodiment of the present invention will be described.
FIG. 15 is a circuit diagram showing a voltage level shifter according to the tenth embodiment of the present invention. In FIG. 15, voltage level shifters 51-1 and 51-2 and a buffer circuit 54 are depicted. Further, the circuit configuration shown in FIG. 15 can be employed at least one of the drivers 5a and 5b of the display device 1 shown in FIG.
[0098]
The circuit shown in FIG. 15 has transistors Tr7 and Tr7 ′ interposed between the drain of the transistor Tr1 and the node N3 and between the drain of the transistor Tr1 ′ and the node N3 ′, respectively, and the drain of the transistor Tr4 and the node N4. 8 and the circuit shown in FIG. 8 except that transistors Tr8 and Tr8 ′ are interposed between the drain of the transistor Tr4 ′ and the node N4 ′. That is, the circuit shown in FIG. 15 corresponds to a circuit in which a part of the circuit configuration shown in FIG. 11 is adopted in the circuit shown in FIG.
[0099]
According to this circuit, both of the effects described in the fourth and sixth embodiments can be obtained. In other words, according to the present embodiment, the signal level inversion at the output terminal OUT accompanying the inversion of the signal level at the input terminals IN1 and IN2 can be caused more quickly, and a larger amplification effect can be obtained, resulting in more stability. Operation is possible.
[0100]
As described above, according to the first to tenth embodiments, a sufficient on-current can be obtained even when the voltage level shifter is configured by a p-channel transistor.
[0101]
In the first to tenth embodiments, the case where the display device 1 is an organic EL display device has been described as an example. However, the display device 1 may be another display device such as a liquid crystal display device. In the first to tenth embodiments, each transistor is a p-channel transistor. However, these transistors may be n-channel transistors. In other words, each transistor only needs to be formed of the same conductivity type. Further, in the first to tenth embodiments, both of the signals output from the pair of output terminals of the voltage level shifter are used to generate a signal to be supplied to the shift register. Only the signal to be transmitted may be used.
[0102]
【The invention's effect】
As described above, according to the present invention, a voltage level shifter configured by transistors of the same conductivity type and capable of efficiently amplifying signals and a display device using the same are provided.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a display device according to a first embodiment of the invention.
FIG. 2 is a circuit diagram showing a voltage level shifter according to the first embodiment of the present invention.
FIG. 3 is a graph showing an example of level shifting that can be performed by the circuit of FIG. 2;
FIG. 4 is a circuit diagram showing a voltage level shifter according to a second embodiment of the present invention.
5 is a graph showing an example of level shifting that can be performed by the circuit of FIG. 4;
FIG. 6 is a circuit diagram showing a voltage level shifter according to a third embodiment of the present invention.
7 is a graph showing an example of level shifting that can be performed by the circuit of FIG. 6;
FIG. 8 is a circuit diagram showing a voltage level shifter according to a fourth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a voltage level shifter according to a fifth embodiment of the present invention.
10 is a graph showing an example of level shifting that can be performed by the circuit of FIG. 9;
FIG. 11 is a circuit diagram showing a voltage level shifter according to a sixth embodiment of the present invention.
FIG. 12 is a circuit diagram showing a voltage level shifter according to a seventh embodiment of the present invention.
FIG. 13 is a circuit diagram showing a voltage level shifter according to an eighth embodiment of the present invention.
FIG. 14 is a circuit diagram showing a voltage level shifter according to a ninth embodiment of the present invention.
FIG. 15 is a circuit diagram showing a voltage level shifter according to a tenth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Display apparatus; 2 ... Substrate; 3 ... Pixel; 4 ... Display area; 5a ... Scanning signal line driver; 5b ... Video signal line driver; 6 ... Scanning signal line; Display element 50a Vertical shift register 50b Horizontal shift register 51, 51a 51b 51-1, 51-2 Voltage level shifter 52 Video signal bus 53 Analog switch 54 Buffer circuit Sw ... Switch for selection; Tr, Tr1 to Tr11, Tr1 'to Tr8' ... Transistor; C, C1 to C3, C1 ', C2' ... Capacitor N1 to N4, N1 'to N4' ... Node; IN1, IN2 ... Input terminal OUT ... Output terminal; VDD ... Power supply terminal; GND ... Power supply terminal; VSS ... Power supply terminal

Claims (6)

The first and second transistors sequentially connected in series to the first power supply terminal, and the control terminal connected between the first input terminal to which the first input signal is supplied and the control terminal of the second transistor. A third transistor connected to a second power supply terminal, a first capacitor connected between the first terminal of the second transistor connected to the first transistor and the control terminal of the second transistor; , Fourth and fifth transistors sequentially connected in series to the first power supply terminal, a second input terminal to which a second input signal complementary to the first input signal is supplied, and the fifth transistor A sixth transistor connected between the control terminal of the transistor and a control terminal connected to the second power supply terminal; a second terminal connected to the fourth transistor of the fifth transistor; A second capacitor connected to the control terminal of the transistor, wherein the first to sixth transistors have the same conductivity type, and the first terminal is connected to the control terminal of the fourth transistor, The voltage level shifter, wherein the second terminal is connected to a control terminal of the first transistor. The first and second transistors are connected in series between the first power supply terminal and the second power supply terminal, and the fourth and fifth transistors are connected between the first power supply terminal and the second power supply terminal. The voltage level shifter according to claim 1, wherein the voltage level shifter is connected in series. The first and second transistors are connected in series between the first power supply terminal and the first input terminal, and the fourth and fifth transistors are connected between the first power supply terminal and the second input terminal. The voltage level shifter according to claim 1, wherein the voltage level shifter is connected in series. A seventh transistor connected between the first terminal and the second transistor side terminal of the first transistor and having a control terminal connected to the second input terminal; the second terminal; and the fourth transistor. And an eighth transistor having a control terminal connected to the first input terminal and having a control terminal connected to the terminal on the fifth transistor side of the transistor. The conductivity type of the seventh and eighth transistors is the The voltage level shifter according to any one of claims 1 to 3, wherein the voltage level shifter is equal to the conductivity type of the first to sixth transistors. The voltage level shifter according to any one of claims 1 to 4, wherein at least one of the first and second terminals is an output terminal. A substrate,
A drive circuit provided on the substrate and provided with the voltage level shifter according to any one of claims 1 to 5,
A display device comprising: a plurality of pixels arranged in a matrix on the substrate and driven by the driving circuit.

Images