JP4049124B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4049124B2 JP4049124B2 JP2004148055A JP2004148055A JP4049124B2 JP 4049124 B2 JP4049124 B2 JP 4049124B2 JP 2004148055 A JP2004148055 A JP 2004148055A JP 2004148055 A JP2004148055 A JP 2004148055A JP 4049124 B2 JP4049124 B2 JP 4049124B2
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- Prior art keywords
- film
- layer
- orientation
- tin
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
- Chemical Vapour Deposition (AREA)
Description
前記Ti膜は、スパッタ法を利用する。
前記バッファ膜は、TiN膜を化学気相成長法で形成する。
前記バッファ膜は、前記Ti膜より薄いTiN膜を形成する。
図3(b)は、本発明に係るアルミニウム配線のグレンサイズのばらつき及び結晶配向度合いを示す拡大表面図である。すなわち、結晶配向を(002)面としたTi膜上に、上述のようにTi膜の(002)結晶面配向の影響を引き継ぐ薄膜形成のCVD−TiN膜を配した。結果、上層のアルミニウム配線に関して、(111)結晶面の配向率は88.3%となった。グレンサイズの均一性も大幅に改善されていることがわかる。これにより、エレクトロマイグレーション耐性の高い配線形成が可能となる。
また、バッファ膜として薄膜形成するTiN膜M2はCVD法を用いて形成した。しかし、スパッタ技術を用いて10nm程度の均一な薄膜形成が可能ならば、Ti膜の結晶学的情報を崩さずにバッファ膜形成が達成できると考えられ、同様の効果を期待することができる。
また、アルミニウム層M3上のTiN膜4は反射防止膜として、スパッタ形成ではなく、CVD形成してもよい。あるいは、他の物質の反射防止膜を設けてもよい。
Claims (1)
- 半導体基板上の絶縁層に、複数の各々の素子に接続される配線部材を形成する半導体装置の製造方法において、
前記配線部材を形成する工程は、
前記半導体基板の上方に前記絶縁層を形成する工程と、
前記絶縁層にホールを形成する工程と、
前記絶縁層上の表面および前記ホールの表面に、スパッタリング法を用いて第一バリアメタルの第一層として第一Ti膜を(002)結晶面に高配向させるように形成する工程と、
前記第一バリアメタルの第二層として拡散または合金化を防止するアモルファス構造を有する第一TiN膜を堆積させ、前記第一Ti膜の配向性が引き継がれるように形成する工程と、
前記ホールに前記第一Ti膜及び前記第一TiN膜を介してタングステンプラグを形成する工程と、
前記タングステンプラグの表面を平坦化し、かつ前記絶縁膜上の表面に形成された前記第一Ti膜及び前記第一TiN膜を除去する工程と、
第一チャンバ内で、前記絶縁層上の表面および前記タングステンプラグの表面に、スパッタリング法を用いて第二バリアメタルの第一層として第二Ti膜を(002)結晶面に高配向させるように形成する工程と、
第二チャンバ内で、前記第二バリアメタルの第二層として拡散または合金化を防止するアモルファス構造を有する第二TiN膜を堆積させ、前記第二Ti膜の配向性が引き継がれるように形成する工程と、
第三チャンバ内で、前記第二TiN膜上に前記配線部材の主要部として、少なくとも前記第二Ti膜の配向性の影響を受けることにより(111)結晶面に高配向制御されるアルミニウムを主成分とした導電層を形成する工程と、
を含み、
前記第二Ti膜を形成する工程において、前記チャンバ内の圧力を4×10 −2 Paとして、かつターゲットと前記半導体基板の間の距離を200mm以上300mm以下とし、前記第一チャンバないし第三チャンバはマルチチャンバであることを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004148055A JP4049124B2 (ja) | 2004-05-18 | 2004-05-18 | 半導体装置の製造方法 |
US11/126,975 US20050258541A1 (en) | 2004-05-18 | 2005-05-11 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004148055A JP4049124B2 (ja) | 2004-05-18 | 2004-05-18 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005332878A JP2005332878A (ja) | 2005-12-02 |
JP4049124B2 true JP4049124B2 (ja) | 2008-02-20 |
Family
ID=35374433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004148055A Expired - Fee Related JP4049124B2 (ja) | 2004-05-18 | 2004-05-18 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (1) | US20050258541A1 (ja) |
JP (1) | JP4049124B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080246082A1 (en) * | 2007-04-04 | 2008-10-09 | Force-Mos Technology Corporation | Trenched mosfets with embedded schottky in the same cell |
JP2012164940A (ja) * | 2011-02-09 | 2012-08-30 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2012199520A (ja) * | 2011-03-10 | 2012-10-18 | Toshiba Corp | 半導体装置およびその製造方法 |
JP5801221B2 (ja) * | 2012-02-22 | 2015-10-28 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
WO2016051970A1 (ja) * | 2014-09-30 | 2016-04-07 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3491237B2 (ja) * | 1993-09-24 | 2004-01-26 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の積層導電膜構造 |
JPH11186190A (ja) * | 1997-12-25 | 1999-07-09 | Sharp Corp | 半導体装置の製造方法 |
US6303490B1 (en) * | 2000-02-09 | 2001-10-16 | Macronix International Co., Ltd. | Method for barrier layer in copper manufacture |
JP3961399B2 (ja) * | 2002-10-30 | 2007-08-22 | 富士通株式会社 | 半導体装置の製造方法 |
-
2004
- 2004-05-18 JP JP2004148055A patent/JP4049124B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-11 US US11/126,975 patent/US20050258541A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2005332878A (ja) | 2005-12-02 |
US20050258541A1 (en) | 2005-11-24 |
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