JP4047492B2 - MIS type semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MIS type semiconductor device and a manufacturing method thereof, and more particularly to a device used for a source region and a drain region.
[0002]
[Prior art]
In order to meet the demand for higher performance due to higher integration based on miniaturization in recent years, when a semiconductor integrated circuit is formed, the gate electrode of the transistor is processed in a region close to the processing limit of lithography technology. For this reason, the variation in channel length caused by the variation in the gate electrode gives an increasingly large variation in the transistor characteristics, which decreases the product yield. On the other hand, with the miniaturization of the semiconductor integrated circuit, fine transistors and wirings are arranged extremely densely, and the wiring distance is long. Therefore, even if the transistor operation speed is increased based on miniaturization, there is a situation in which the circuit operation cannot be increased due to the parasitic capacitance and the parasitic resistance between the transistor and the wiring.
[0003]
The structure of a conventional planar transistor is shown in FIG. A gate electrode 3 is formed on the silicon substrate 1 via a gate insulating film 2. Wirings 4 a and 4 b are formed on the side of the gate electrode 3 with an insulating film 9 interposed therebetween. Further, a source diffusion layer 5a and a drain diffusion layer 5b are formed in the silicon substrate 1, and a region 6 between the diffusion layers 5a and 5b becomes a channel region. Reference numeral 7 denotes an element isolation insulating film, and reference numeral 8 denotes an interlayer insulating film.
[0004]
Since the diffusion layers 5 a and 5 b are distributed in the silicon substrate 1 adjacent to the channel region 6, this distribution weakens control of the channel region 6 by the gate electrode 3 and causes a so-called short channel effect, thereby causing variations in lithography processing. The influence of has been expanded.
[0005]
Further, for comparison in explaining the problems of the concave transistor described later and other conventional transistors, the current generated when the planar transistor is operated is shown by a one-dot chain line in FIG. The current injected from the wiring 4a enters the source diffusion layer 5a and corresponds to the accumulation layer (corresponding to the surface portion of the diffusion layer 5a facing the gate electrode 3 through the gate insulating film 2, and the number of diffusion layer active impurity concentrations). (Which has a carrier density of 10 times or more), enters the inversion layer of the channel region 6, flows to the wiring 4 b through the accumulation layer of the drain diffusion layer 5 b and the other diffusion layer region, thereby forming a current path. .
[0006]
In the diffusion layer region outside the accumulation layer, a high carrier concentration region on the surface of the substrate 1 is lost, and the current spreads deeply into the diffusion layers 5a and 5b due to the carrier concentration determined by the active impurity concentration, which causes a so-called spreading resistance. As shown by the alternate long and short dash line 26, a substantially linear current path is formed.
[0007]
Usually, the source region and the drain region are formed by introducing an impurity having a conductivity type opposite to that of the substrate by ion implantation using the gate electrode as a mask and activating or diffusing the impurity by a thermal process. The source region and the drain region connect the current path to the wiring with the channel, and in order to make this connection with a sufficiently low resistance value, it is necessary to diffuse and form a sufficiently deep region with high concentration.
[0008]
FIG. 27 is a diagram showing the relationship between the impurity concentration in the drain diffusion layer 5b in the electron concentration distribution during the operation of the planar transistor having a gate length of 0.1 μm, and is obtained by device simulation in the vicinity of the gate electrode 3 in FIG. is there. In the figure, only the drain diffusion layer 5b side is shown. In this simulation, 1V is applied to the gate electrode 3 and 1V is applied to the drain diffusion layer 5b.
[0009]
The bias applied to the source diffusion layer 5a is 0V. Therefore, the current is strongly controlled by the gate bias in the vicinity of the source diffusion layer 5a. In the vicinity of the drain diffusion layer 5b, the influence of the gate electrode 3 on the surface of the substrate 1 due to the bias applied to the drain diffusion layer 5b is weaker than in the case of the source diffusion layer 5a. However, since the gate insulating film 2 is extremely thin, the current is strongly controlled by the gate electrode 3 even in the vicinity of the drain diffusion layer 5b. Although the drain diffusion layer 5b will be mainly described below, the relationship between the electron concentration or current concentration distribution and the position of the gate electrode 3 or the diffusion layer impurity distribution is basically the same in the source diffusion layer 5a.
[0010]
The drain diffusion layer 5b is distributed to the lower side or the inner side of the edge of the gate electrode 3 for connection with the channel, and forms a pn junction with the channel impurity. This pn junction position is indicated by a thick line in FIG. At the junction position, the opposite conductivity type impurities cancel each other, and the net impurity concentration becomes zero.
[0011]
That is, as shown by the broken line in FIG. ²⁰ cm ^-3 Even if such a high concentration of impurity is introduced, the impurity concentration in the vicinity of the edge of the gate electrode 3 is generally lost due to diffusion and becomes low, and the impurity concentration further decreases as the junction approaches the center of the channel region 6 from the edge. . A depletion layer is formed around the junction, the carrier concentration (electron concentration) is extremely low, and the source diffusion layer 5a or the drain diffusion layer 5b is electrically isolated from the substrate 1 of the reverse conductivity type. For this reason, in FIG. _Ten The electron concentration distribution curve where (electron concentration) = 18 is log _Ten As can be seen from the fact that it is farther from the junction surface than the impurity concentration distribution curve where (impurity concentration) = 18, the carrier concentration (electron concentration) in the vicinity of the junction in the portion far from the surface of the substrate 1 of the drain diffusion layer 5b. Is lower than the impurity concentration.
[0012]
When the transistor operates, an inversion layer is formed on the surface of the substrate 1 in the channel region 6 by the voltage applied to the gate electrode 3. The high electron concentration region on the surface of the channel region 6 in FIG. 27 is this inversion layer. On the other hand, an accumulation layer is formed on the drain diffusion layer 5b side near the junction near the surface of the substrate 1 and is joined near the junction with the inversion layer formed on the channel region 6 side to form a current path.
[0013]
In FIG. 27, the portion of the drain diffusion layer 5b in the vicinity of the surface of the substrate 1 and in the vicinity of the bonding surface is the accumulation layer where the electron concentration is higher than the impurity concentration. Further, in the drain diffusion layer 5b, in a region having a high impurity concentration away from the edge of the gate electrode 3, the electron concentration matches the impurity concentration.
[0014]
FIG. 28 shows the relationship between the current density distribution and the position of the gate electrode 3 or the impurity concentration distribution when the same bias is applied to the same MOS transistor as in FIG. Inside the edge of the gate electrode 3, a region having a high current density is distributed in the vicinity of the surface of the substrate 1 due to the inversion layer formed on the surface of the channel region 6 or the accumulation layer formed on the surface of the impurity region. However, outside the edge of the gate electrode 3, the electric field generated by the gate electrode 3 suddenly weakens, so that a region with a high current density biased toward the surface of the substrate 1 is lost, and the current density is equal to the electron concentration of the drain diffusion layer 5 b. Along the high region, it is distributed to the back side of the substrate 1 at a low value.
[0015]
Therefore, in the region where the influence of the gate bias outside the edge of the gate electrode 3 is small, a sufficient accumulation layer can be induced by the gate bias and the parasitic resistance can be lowered. Instead, the carrier determined by the impurity concentration It is necessary to increase the concentration sufficiently and to distribute the substrate 1 deeply in accordance with the concentration to lower the resistance. That is, it is indispensable that the impurity concentration under the edge of the gate electrode 3 is sufficiently high and distributed to the substrate 1 to reduce the parasitic resistance in the region outside the edge.
[0016]
The results shown in FIGS. 27 and 28 are for an example of a typical planar MIS type transistor. Depending on the impurity distribution in the drain diffusion layer, the position of the gate electrode edge and the gate electrode in the vicinity of the edge are also shown. Depending on the shape, etc., the electron concentration distribution and current density distribution change. For example, the peak position in one or both of the drain diffusion layers may be located deep in the substrate, not the substrate surface. Even in this case, the situation is the same in which the storage layer is formed on the surface of the diffusion layer region by the electric field of the gate electrode and the parasitic resistance of the diffusion layer region under the edge is lowered.
[0017]
The impurity region inside the edge of the gate electrode 3 is indispensable in order to make the impurity concentration just below the edge of the gate electrode 3 high and sufficiently deeply distributed. However, due to the recent miniaturization, the length of the gate electrode 3 becomes extremely short, and the electric field applied to the channel region 6 by the impurity distribution of the diffusion layer 5a or 5b weakens the control of the electric field applied to the channel region 6 by the gate electrode 3, The so-called short channel effect is caused and the product yield is further deteriorated.
[0018]
In order to suppress this short channel effect, efforts are being made to reduce the junction depth of the diffusion layer 5a or 5b. However, as described above, in order to connect the channel region 6 and the high impurity concentration region of the drain diffusion layer 5b with sufficiently small parasitic resistance, the impurity concentration under the edge of the gate electrode 3 is distributed high and sufficiently deep. This is inconsistent with the achievement of the purpose of suppressing the short channel effect.
[0019]
A concave transistor is proposed as a structure for solving this contradiction. (For example, Nishimatsu et al., Groove Gate MOSFET, 8th Conf. On Solid State Device, pp.179-183, 1976). FIG. 29A shows a cross-sectional view of a conventional concave transistor structure. Portions common to those in FIG. In the conventional recessed transistor, the source diffusion layer 45a and the drain diffusion layer 45b are made higher than the surface of the recess bottom channel region, so that the impurity distribution in the diffusion layers 45a and 45b can be electrically controlled by the gate electrode 43 in the channel region. The effect on it is suppressed. In the concave transistor, the source and drain can be made thicker (deeper) while maintaining the distance from the bottom channel region of the recess, and the parasitic resistance per unit length of the diffusion layer portion of the source and drain can be reduced while suppressing the short channel effect. Can be lowered.
[0020]
However, a normal concave transistor has the following problems. FIG. 29B is an enlarged view of a main part of the concave transistor of FIG. An inversion layer 46 is formed on the bottom surface of the recess of the silicon substrate 1, an inversion layer 47 is formed on the side surface of the recess, and a storage layer 48 is formed on the side surface of the recess and in contact with the gate insulating film 42 in the diffusion layer 45 a. The The inversion layer 46 on the bottom surface of the recess corresponds to the inversion layer formed on the surface portion of the channel region 46 of the planar transistor of FIG.
[0021]
As described above, in the normal concave transistor, in addition to the inversion layer 46 on the bottom surface of the recess, the side channel portion and the source diffusion layer 45a and drain diffusion layer 45b connected to the side channel portion are also gated through the gate insulating film 42. A portion parallel to the electrode 43 is provided. In a portion parallel to the gate electrode 43 on the side surface of the recess, the recess side surface inversion layer 47 or the recess side surface accumulation layer 48 is generated in parallel with the side surface of the gate electrode 43 to form a current path, thereby generating a large parasitic capacitance.
[0022]
On the other hand, when the current path of the planar transistor shown in FIG. 26 is compared with the current path of the recessed transistor shown in FIG. 29, the current path of the planar transistor is linear. The angle formed by the current path on each side surface of the recess is close to an acute angle, and the distance of the current path to the wirings 4a and 4b connected to the diffusion layers 45a and 45b is increased.
[0023]
Further, normally, in order to suppress the parasitic capacitance between the gate electrode 43 or the wiring connected to the gate electrode 43 and the wirings 4a and 4b, or to suppress the leakage current generated therebetween, the gate electrode 43 and the diffusion layer In many cases, a non-conductive film region, that is, a side wall insulating film 49 is provided so as to lengthen the distance between the wirings 4a and 4b to 45a and 45b or to contact the gate side surface on the substrate 1.
[0024]
In the case of a normal concave transistor in which the bottom surface of the side wall insulating film 49 is formed in parallel with the bottom surface of the recess, a step between the bottom surface of the side wall insulating film 49 and the bottom surface of the recess through the inversion layer 47 or the accumulation layer 48 on the side surface of the recess. Since the current path is formed through a path close to an acute angle between the planes having, the current path is longer than that of the above-described planar transistor, and the parasitic resistance due to this is increased.
[0025]
Further, the carrier distribution peak around the channel is distributed in a very thin region of 0.01 μm or less along the channel surface. Therefore, when the current path close to the acute angle, that is, when the electron travel path is in the region close to the channel bottom surface, extra work is required for the carriers to follow the acute angle distribution of the carrier distribution peak, and the current value decreases. .
[0026]
On the other hand, as a conventionally known structure in the case of a p-type planar transistor, a transistor structure having a source region and a drain region having an oblique substrate surface is referred to as “Ultra-Shallow in-situ-doped raised source / drain structure for sub-tenth micron CMOS ", Y. Nakahara et al., pp. 174-175, 1996 Symposium on VLSI Technology Digest of Technical Papers. This structure is shown in FIG. In the case of the structure of FIG. 30, unlike the concave transistor shown in FIG. 29, the channel region and the source and drain are formed in a plane. Further, the current reaches the wiring (not shown) to the source and drain through the shallow diffusion layers 55a and 55b and the deep and deep diffusion layers 55c and 55d formed on the same plane as the channel region.
[0027]
That is, in the recessed transistor shown in FIG. 29, the accumulation layer 48 connected to the inversion layer of the channel region is located shallower than the depth of the channel bottom surface, thereby reducing the short channel effect by separating the diffusion layers 45a and 45b from the channel bottom surface. On the other hand, in the structure of FIG. 30, the accumulation layer formed in the source diffusion layer and the drain diffusion layer connected to the channel inversion layer has a channel region at the end adjacent to the channel region of the shallow diffusion layers 55a and 55b. It is formed on the same plane as the inversion layer. For this reason, the shallow diffusion layers 55a and 55b in FIG. 30 are distributed inside the silicon substrate 1 adjacent to the channel inversion layer, and a short channel effect occurs depending on the thickness.
[0028]
Therefore, in order to suppress the short channel effect, the shallow source diffusion layer 55a and the drain diffusion layer 55b are formed extremely shallowly adjacent to the channel region using silicon. In order to compensate for the thickness of the diffusion layers 55a and 55b, the epitaxial source diffusion layer 55e and the drain diffusion layer 55f are formed on the silicon substrate 1. Here, the edge of the gate electrode 53 is located on the shallow source diffusion layer 55a and the drain diffusion layer 55b at a position deviated from the surface of the epitaxial diffusion layers 55e and 55f via the nitride film side wall 56.
[0029]
Since it has such a structure, the influence of the electric field of the gate electrode 53 on the current path formed in the epitaxial diffusion layers 55e and 55f during the operation of this transistor is small. Therefore, the current flows through a wide region in the epitaxial diffusion layers 55e and 55f and has a resistance, but a current path is supplied in parallel to the diffusion layers 55a and 55b to reduce the parasitic resistance of the entire source and drain.
[0030]
That is, the effect of the epitaxial diffusion layers 55e and 55f in the structure of FIG. 30 is to compensate for the high resistance of the shallow diffusion layers 55a and 55b reaching the deep and dense diffusion layers 55c and 55d on the same plane as the channel bottom surface. It is to reduce.
[0031]
Further, by forming the surfaces of the epitaxial diffusion layers 55e and 55f obliquely, a thick oxide film side wall 57 is formed through the nitride film side wall 56 between the gate electrode 53 and the surface of the source / drain diffusion layer. The parasitic capacitance can be reduced.
[0032]
However, in the case of this transistor structure, since it is still a planar transistor, the short channel effect cannot be sufficiently suppressed only by controlling the thickness of the shallow diffusion layers 55a and 55b.
[0033]
[Problems to be solved by the invention]
As described above, when the conventional semiconductor device is used, it is impossible to suppress the short channel effect, reduce the parasitic capacitance and the parasitic resistance, and reduce the resistance of the current path.
[0034]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device that reduces parasitic resistance and parasitic capacitance and suppresses the short channel effect, and a method for manufacturing the same. .
[0035]
[Means for Solving the Problems]
An MIS type semiconductor device according to the present invention includes a semiconductor layer having a recess having a side wall that is gentler than a right angle at least in part, a gate electrode formed by sandwiching a gate insulating film above the bottom surface of the recess, A source region and a drain region formed in the semiconductor layer with the insulating film sandwiched between the side surfaces and the boundary surface with the insulating film being inclined with respect to the surface of the semiconductor layer; and wiring contacts connected to the surface of the semiconductor layer; And the edge of the gate electrode is located inside a recess provided in the semiconductor layer, and at least one of the gate electrode and the source region or the gate electrode and the drain region has a region facing each other. In addition, at least one of the source region and the drain region in the opposite region operates as a storage layer.
[0036]
Here, the edge of the gate electrode refers to a position where the side wall of the gate electrode not in contact with the gate insulating film intersects the gate insulating film. The gate insulating film is formed between the gate electrode and the source or drain region in a region sandwiched between the region where the gate electrode and the source region face each other and the region where the gate electrode and the drain region face each other. It shall mean an insulating film.
[0037]
Further, the fact that the edge of the gate electrode is positioned inside the recess includes the case where the edge of the gate electrode is positioned at the boundary point between the recess and the region outside the recess. Further, the present invention includes a case where the junction position between the source region and the channel region or the junction position between the drain region and the channel region in the vicinity of the gate insulating film is located immediately below the edge of the gate electrode.
[0038]
Preferably, in the insulating film formed between the source region or the drain region and the gate electrode, a region other than the region where the gate electrode and the source region or the gate electrode and the drain region face each other is more than the opposite region. It is formed thick.
[0039]
Further, another MIS type semiconductor device according to the present invention includes a semiconductor layer having a recess having a side wall that is gentler than a right angle at least partially, and a gate electrode formed by sandwiching a gate insulating film above the bottom surface of the recess. A source region and a drain region formed in the semiconductor layer with the insulating film sandwiched between the side surfaces of the gate electrode and the boundary surface with the insulating film being inclined with respect to the surface of the semiconductor layer; A channel region formed underneath, wherein the source region and the gate electrode have a first opposing region at a first junction position between the source region and the channel region in the vicinity of the gate insulating film, and the gate At the second junction position of the drain region and the channel region in the vicinity of the insulating film, the drain region and the gate electrode have a second opposing region, and the first or second opposing region is small. At least one of the source region or the drain region operates as an accumulation layer, and the first or second of the insulating films formed between at least one of the source region or the drain region and the gate electrode. The insulating film in the region other than the opposing region is formed to be thicker than the first or second opposing region.
[0040]
Desirable embodiments of the present invention are shown below.
[0041]
(1) The height of the gate insulating film has a portion that continuously increases from the vicinity of the center of the channel region to at least one of the source region and the drain region.
[0042]
(2) The gate insulating film between the channel region and the gate electrode is formed linearly.
[0043]
(3) A contact formed on the surface of the source region and the drain region so as to be separated from the gate electrode, and a boundary surface between the source region and the contact and between the drain region and the contact with the gate insulating film And a distance between the contact and the gate electrode is shorter than 1.5 times the gate width.
[0044]
(4) In (3), at least one of the surfaces of the source region and the drain region in the region closer to the contact than the first and second opposing regions is formed with an inclination with respect to the surface of the semiconductor layer. .
[0045]
(5) At least one of the heights of the lower surface of the source region or the drain region in the vicinity of the first or second opposing region is formed higher than the height of the channel region.
(6) In (3), the source region and the drain region are formed of a material having the same conductivity type as the channel region formed between the source region and the drain region.
[0046]
(7) The gate insulating film between the channel region and the gate electrode is formed in a straight line, and a corner portion is formed between both ends of the linear gate insulating film and a side wall which is gentler than a right angle. And at least one of the first and second joining positions is located between the corner portions.
[0047]
(8) The impurity concentration of the source region or the drain region at one end located below the gate electrode edge of at least one of the first or second opposing regions is 1 × 10 ¹³ cm ^-2 That's it.
[0048]
(9) The source region and the drain region are formed at a position shallower than the interface between the channel region and the gate insulating film.
[0049]
Here, the junction position between the source region or the drain region and the channel region refers to a boundary position of a junction formed by the source region or the drain region and the channel region.
[0050]
Further, in the method of manufacturing the MIS type semiconductor device according to the present invention, a step of forming a recess having a side wall that is gentler than a right angle is formed in the semiconductor layer by the RIE method, and a gate insulating film is formed so as to cover the surface of the semiconductor layer. A step of forming a conductive film on the gate insulating film including the recess, and a step of forming the gate electrode by patterning the conductive film using a lithography method so that the side wall is positioned on the side surface of the recess. It is characterized by having.
[0051]
Desirable embodiments of the present invention are shown below.
[0052]
(1) The side surface of the recess has an angle of approximately 45 degrees with respect to the surface of the semiconductor layer.
[0053]
(2) A step of forming a source region and a drain region in the semiconductor layer with the gate electrode interposed therebetween, a step of forming an interlayer insulating film on the semiconductor layer so as to cover the gate electrode, the source region, and the drain region, and an interlayer insulation Forming a contact hole connecting the wiring to at least one surface of the source region or the drain region by selectively removing the film using reactive ion etching, and the step of forming the contact hole includes: By using an insulating film that protects the sidewall and surface of the electrode as a mask, the gate electrode is formed in a self-aligning manner.
[0054]
Further, another method of manufacturing a MIS type semiconductor device according to the present invention includes a step of selectively laminating a first insulating film and a dummy gate on a first semiconductor layer, and a semiconductor material using the dummy gate as a mask. Forming a second semiconductor layer having sidewalls gentler than a right angle with the dummy gate interposed therebetween, and removing the first insulating film and the dummy gate; And a step of selectively forming a gate insulating film and a gate electrode sequentially in a region where the first insulating film and the dummy gate are formed.
[0055]
Desirable embodiments of the present invention are shown below.
[0056]
(1) After forming the second semiconductor layer, forming a second insulating film so as to cover the surfaces of the second semiconductor layer and the dummy gate, and depositing a filler on the second insulating film. And removing the first and second insulating films formed on the side walls of the dummy gate together with the dummy gate by exposing the surface of the filler to a flattened surface and removing the dummy gate. Forming a recess having a tapered portion having the same inclination as the side surface of the second semiconductor layer, forming a gate insulating film on the bottom surface of the formed recess, and conducting the conductive in the recess where the gate insulating film is formed. And embedding a conductive material using a damascene process.
[0057]
(2) The angle of at least one side wall of the second semiconductor layer is approximately 50 degrees or 30 degrees with respect to the surface of the first semiconductor layer.
[0058]
(3) Solid phase growth is epitaxial growth.
[0059]
(4) a step of forming a source region and a drain region on the surface of the second semiconductor layer, a step of forming an insulating film for protecting the gate electrode on the side wall and surface of the gate electrode after forming the gate electrode, Forming an interlayer insulating film over the first semiconductor layer so as to cover the film, and selectively removing the interlayer insulating film by reactive ion etching using the insulating film as a mask; A contact hole connected to the wiring is formed in at least one surface of the gate electrode in a self-aligning manner.
[0060]
(5) After forming the semiconductor layer, impurities are diffused only for a desired film thickness on the surface of the semiconductor layer.
[0061]
(6) After forming the gate insulating film and the gate electrode, ion implantation is performed using the gate electrode as a mask to diffuse impurities, and a source region and a drain region are formed in the semiconductor layer on the side surface of the gate electrode.
[0062]
(Function)
In the MIS type semiconductor device of the present invention, the edge of the gate electrode is located on the side wall of the recess including the region having the inclination of the source region and the drain region, and at least one of the gate electrode and the source region or the gate electrode and the drain region is the gate It has an area | region which opposes via an insulating film. Storage layers are formed during operation on the surfaces of the source and drain regions in the opposing regions. One end of the accumulation layer (hereinafter referred to as a first end) is a portion where the source region or the drain region forms a junction with the channel region, and the net impurity concentration is low. Therefore, although the carrier density determined by the impurity concentration is low, carriers of several tens of times higher than the carrier density in the case where it is not formed are accumulated in this accumulation layer. The resistance of the region close to the region forming the junction with the region is lowered.
[0063]
The other end of the accumulation layer (hereinafter referred to as the second end) is located away from the junction position with the channel region of the source region or the drain region, and is located at a point having a sufficiently high impurity concentration. Can do. In addition, since the second end portion is located shallower than the channel surface, the short channel effect does not occur even if impurities are distributed deeply from this position and the resistance of the region outside the gate edge is lowered.
[0064]
Further, since the accumulation layer is formed along the side wall having the inclination, the current path from the channel surface to the wiring is made close to a straight line to shorten the distance. Thus, since the channel surface and the wiring are connected by a short current path with a low resistivity, the parasitic resistance can be reduced.
[0065]
Further, the source region and the drain region on the side surface of the gate electrode are formed with an inclination with respect to the surface of the semiconductor layer. Accordingly, the interval between the gate electrode and the source region or the gate electrode and the drain region is widened, and the parasitic capacitance can be reduced.
[0066]
Unlike a planar transistor, the gate electrode and source region or the gate electrode and drain region are formed at a position shallower than the interface between the channel region and the gate insulating film. It is not necessary to form a diffusion layer in the vicinity of the region, and the short channel effect can be suppressed.
[0067]
Note that even when the source region and the drain region have a region protruding to the lower side than the interface between the channel region and the gate insulating film, by controlling the protruding region to a thickness enough to operate as an inversion layer, the above and The same effect is produced.
[0068]
In the method for manufacturing a semiconductor device according to the present invention, a concave portion having a side wall that is gentler than a right angle is formed in the semiconductor layer by the RIE method, a conductive film is formed on the semiconductor layer including the concave portion, and the side surface of the concave portion is formed. The conductive film is patterned using lithography so that the side wall is located. Thereby, it is possible to realize a MIS type semiconductor device that suppresses the short channel effect and reduces the parasitic capacitance and the parasitic resistance.
[0069]
Further, the source region and the drain region are formed by solid phase growth using the dummy gate as a mask in the MIS type semiconductor device, and the gate electrode is formed in the recess from which the dummy gate is removed, so that the source region and the drain region are formed. The gate electrode can be formed in a self-aligned manner, and no positional deviation occurs.
[0070]
Furthermore, by removing the dummy gate and the insulating film previously formed on the side wall of the dummy gate, a recess having a tapered portion having the same inclination as the side surface of the second semiconductor layer is formed between the bottom surface and the side wall. Thus, a region where the gate electrode and the second semiconductor layer operating as a source region or a drain region face each other can be formed.
[0071]
Further, by forming the gate electrode by a damascene process, it is possible to selectively perform ion implantation into the first semiconductor layer on the bottom surface of the recess that operates as a channel region.
[0072]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0073]
(First embodiment)
1 to 4 are diagrams for explaining the semiconductor device (concave MIS transistor) according to the first embodiment of the present invention, and FIGS. 1 and 4 are for explaining the configuration of the semiconductor device according to the present embodiment. FIG. 2 and FIG. 3 are process cross-sectional views showing a method for manufacturing the semiconductor device. FIG. 1A is a view of the semiconductor device as viewed from above. FIG. 1B is a sectional view taken along the line 6A-6A ′ in FIG. 1A, and FIG. 1C is a sectional view taken along the line 6B-6B ′. FIG. 1D shows a 6C-6C ′ cross-sectional view. In the following embodiments, an n-channel MIS transistor will be described. In the case of a p-channel MIS transistor, the conductivity type of each component may be reversed.
[0074]
In FIG. 1B, reference numeral 61 denotes a p-type silicon substrate using the (100) plane, and the impurity concentration is 5 × 10. ¹⁵ cm ^-3 Degree. As shown in FIG. 1A, the silicon substrate 61 is divided into an active region 62 and an element isolation region 63 formed so as to surround the active region 62. The element isolation region 63 includes an element isolation insulating film 64. Is formed.
[0075]
The active region 62 is a portion surrounded by a broken line in FIG. 1A, and the threshold voltage (V _th ) To adjust the impurity concentration 5 × 10 ¹⁷ cm ^-3 A channel ion implantation layer (not shown) is formed. A gate electrode 68 is formed on the silicon substrate 61 in the active region 62 via a gate insulating film 67, and wirings 70 a and 70 b are provided on both sides of the gate electrode 68 via an interlayer insulating film 69. The wirings 70a and 70b are connected to the source region and the drain region. The source region includes a first source diffusion layer 71a and a second source diffusion layer 72a, and the drain region includes a first drain diffusion layer 71b and a second drain diffusion layer 72b. The gate insulating film 67 is a thermal oxide film having a thickness of about 3.0 nm, for example.
[0076]
In FIG. 1B, the channel surface 65 is located deeper than the substrate surface 66. A recess having the channel surface 65 as a bottom is formed in the silicon substrate 61, and the sidewall of the recess has an inclined surface with a gentler angle than the right angle with respect to the channel surface 65, and the entire recess is covered with the gate insulating film 67. Here, the channel surface 65 refers to an interface between the channel region and the gate insulating film 67. The channel region is formed on the bottom surface of the recess below the channel surface 65.
[0077]
Further, a gate electrode 68 is embedded in the recess of the silicon substrate 61 through the gate insulating film 67 so as to face the channel region. Thus, a concave transistor structure having a channel region embedded in the substrate 61 is formed.
[0078]
A plane having a step between the channel surface 65 and the substrate surface 66 is formed along the sloped side wall of the gate insulating film 67, and the first source diffusion layer 71a and the first source are inclined with respect to the surface of the silicon substrate 61. The drain diffusion layer 71b (shown by oblique lines) is connected to the n-type second source diffusion layer 72a and the second drain diffusion layer 72b connected thereto (hereinafter 71a, 71b, 72a, 72b are simply combined). Called source and drain).
[0079]
The first source diffusion layer 71 a and the drain diffusion layer 71 b are formed toward the channel surface 65, and the second source diffusion layer 72 a and the drain diffusion layer 72 b are thick diffusion layers formed in parallel with the channel surface 65.
[0080]
Here, the diffusion depth and impurity concentration of the second source diffusion layer 72a and the second drain diffusion layer 72b are 0.05 μm and 5 × 10 5 respectively. ²⁰ cm ^-3 Degree.
[0081]
Contact holes 73a to 73c are opened in the interlayer insulating film 69, and the wirings 70a to 70c are n-type second source diffusion layer 72a and second drain diffusion layer 72b through the contact holes 73a to 73c. And a gate electrode 68 respectively. For example, the interlayer insulating film 69 is made of SiO. ₂ The wirings 70a to 70c are made of, for example, an Al film. The wirings 70a to 70c are formed such that the distance between the wirings 70a and 70b and the gate electrode 68 is shorter than 1.5 times the gate width. In addition, the first source diffusion layer 71a and the first drain diffusion layer 71b having an inclination with respect to the surface of the silicon substrate 61 have a region facing the gate electrode 68 at the tip, and include the region. It is formed with an inclination with respect to the surface of the silicon substrate 61 up to the vicinity of 70a and 70b (with deletion). In FIG. 1A, a gate electrode formation region indicated by a cross mark 74 is a region where the gate electrode 68 and the first source diffusion layer 71a and the drain diffusion layer 71b having an inclination overlap with each other, and an oblique line 75. The region indicates the formation region of the first source diffusion layer 71a and the drain diffusion layer 71b.
[0082]
Next, a method for manufacturing the concave MIS transistor according to the present embodiment will be described with reference to FIGS. 2A is a top view, FIG. 2B is a sectional view taken along 7A-7A ′ in FIG. 2A, FIG. 2C is a sectional view taken along 7B-7B ′ in FIG. 2D is a cross-sectional view taken along line 7C-7C ′ of FIG. 2A, FIG. 3A is a top view, and FIG. 3B is a cross-sectional view taken along line 8A-8A ′ of FIG. 3C is an 8B-8B ′ sectional view of FIG. 3A, and FIG. 3D is an 8C-8C ′ sectional view of FIG.
[0083]
First, in the active region 62 on the silicon substrate 61, SiO2 having a thickness of 0.02 μm. ₂ A film 91 is formed. Next, for example, using a desired photoresist pattern (not shown) as a mask, SiO formed in a region where the first source diffusion layer 71a and the first drain diffusion layer 71b having a channel and an inclination are formed. ₂ The film 91 and the silicon substrate 61 are etched by RIE (Reactive Ion Etching) to form a recess 92 having a bottom surface with a depth of about 0.1 μm from the substrate surface 66. At this time, by selecting the RIE condition, as shown in FIG. 2B, the side surface of the recess is formed obliquely with an angle of 45 degrees with respect to the bottom surface of the recess.
[0084]
Next, a polymer layer (not shown) generated during etching and SiO ₂ The film 91 is removed to expose the surface of the active region 62 of the silicon substrate 61 and, for example, heat treatment is performed in a hydrogen atmosphere at 950 ° C. for about 2 minutes, thereby performing damage recovery processing in the recess 92 caused by RIE. Next, a sacrificial SiO (not shown) having a thickness of about 5 nm is formed on the exposed silicon substrate 61 surface. ₂ The film is formed by, for example, a thermal oxidation method. Then, channel ion implantation for threshold voltage control or the like is performed on the lower silicon substrate 61 of the active region 62 including the recess 92 using the element isolation insulating film 64 or the like or a photoresist (not shown) as a mask. In the case of an n-type transistor, for example, a threshold voltage (V _th ) Is set, for example, with an acceleration voltage of 5 keV and a dose of 2 × 10 ¹² cm ^-2 Boron (B ⁺ ) Is implanted to form a p-type channel ion implantation layer in the channel region (not shown).
[0085]
Next, sacrificial SiO (not shown) ₂ After the film is peeled off, as shown in FIG. 3B, a gate insulating film 67 is formed on the surface of the silicon substrate 61 including the bottom surface and the inclined side surface of the recess 92 by thermal oxidation. Here, a film obtained by thermally nitriding the surface of the oxide film may be used for the gate insulating film 67. CVD-SiO ₂ Film, CVD-SiON film, CVD-Si _Three N _Four A stacked film including a film may be used for the gate insulating film 67.
[0086]
Next, a conductive layer to be the gate electrode 68 is formed on the gate insulating film 67 so that the inside of the recess 92 is filled, and the surface of the conductive layer is polished and smoothed by CMP (Chemical Mechanical Polishing). As the conductive layer to be the gate electrode 68, for example, a polysilicon layer doped with an n-type impurity is used.
[0087]
Next, as shown in FIG. 3B, by using the lithography technique, both ends of the conductive layer are included in the recess 92, and the ends of the conductive layer on the source and drain sides are closer to the channel bottom. The gate electrode 68 is formed by patterning so as to be located outside. Next, ion implantation 93 is performed on the silicon substrate 61 using the gate electrode 68, the element isolation insulating film 64, photoresist, and the like as a mask, and the first source diffusion layer 71a, the first drain diffusion layer 71b, and the first Two source diffusion layers 72a and a second drain diffusion layer 72b are formed. The ion implantation conditions are, for example, arsenic (As) ion implantation, an acceleration voltage of about 30 KeV, and a dose amount of 5 × 10. ¹⁵ cm ^-2 Degree.
[0088]
Smoothing the surface of the conductive layer by the CMP method when patterning the conductive layer suppresses the distortion of the gate pattern position of the lithography technique by the smoothing, and the first source diffusion layer 71a and the first drain diffusion layer having inclinations. This is because the edge of the gate electrode 68 is accurately included in the recess 92 in order to easily form 71b. That is, in order to perform the ion implantation 93 for forming the first source diffusion layer 71a and the first drain diffusion layer 71b and the second source diffusion layer 72a and the second drain diffusion layer 72b using the gate electrode 68 as a mask, This is because the formation region of the second source diffusion layer 72a and the second drain diffusion layer 72b varies depending on the formation position of the gate electrode 68 serving as a mask. Note that the edge of the gate electrode 68 refers to a position where the side wall of the gate electrode 68 not in contact with the gate insulating film 67 intersects the gate insulating film 67.
[0089]
The first source diffusion layer 71a and the first drain diffusion layer 71b need to be formed so that no accumulation layer is formed on the channel surface 65 in order to suppress the short channel effect. Therefore, by forming the gate electrode 68 so that the edge is located on the tapered side wall of the recess 92, the regions 71a and 71b extend from the tapered side wall to the vicinity of both ends of the channel surface 65, and the same as the channel region. A structure can be obtained in which the regions 71a and 71b do not expand up to the plane.
[0090]
Further, as shown in FIG. 3B, the edge of the gate electrode 68 is formed outside the bottom of the recess 92 so as to include only a part of the inclined side surface. The junction surface with the gate insulating film 67 can be formed obliquely in accordance with the inclination of the gate insulating film 67.
[0091]
After the ion implantation 93 for forming the source and drain, the impurities are activated by heat treatment at 900 ° C. for about 10 seconds using, for example, RTA (Rapid Thermal Anneal) as activation annealing. Here, for the formation of the source and drain, solid phase diffusion using the gate electrode 68 or the like as a mask after forming the gate electrode 68 without using the ion implantation 93 may be used.
[0092]
Next, as shown in FIG. ₂ After the interlayer insulating film 69 is formed on the entire surface, the contact holes 73a to 73c are formed in the interlayer so that a part of the second source diffusion layer 72a and the second drain diffusion layer 72b and a part of the gate electrode 68 are exposed. A hole is opened in the insulating film 69. Next, a metal such as an Al film or an Al—Cu film is formed on the entire surface so that the contact holes 73a to 73c are filled, and this metal is patterned to form wirings 70a to 70c (only a part of which is shown) according to circuit design. Are sequentially formed. Next, a passivation film (not shown) is deposited on the entire surface to complete the transistor partial manufacturing process.
[0093]
FIG. 4 shows an enlarged cross-sectional view of the vicinity of the first drain diffusion layer 71b having the inclination of the concave MIS transistor formed by the above process, along with the current path. According to the MIS transistor having the concave channel structure configured as described above, there is a step 2 between the channel surface 65 and the substrate surface 66 through the inversion layer and the accumulation layer formed along the side surface having the concave portion inclination. The current path connecting the two planes forms an obtuse angle with the traveling direction of the current path passing from the channel surface 65 to the vicinity of the substrate surface 66.
[0094]
Further, the surface of the region where the inclined first source diffusion layer 71 a and first drain diffusion layer 71 b face the gate electrode 68 operates as a storage layer. One end of the accumulation layer is a portion where the source or drain forms a junction with the channel region, and the net impurity concentration is low. Therefore, although the carrier density determined by the impurity concentration is low, carriers having a concentration of several tens of times the carrier density in the case where it is not formed are accumulated in this accumulation layer. Therefore, the first source diffusion layer 71a or The carrier density in the vicinity of the junction of the first drain diffusion layer 71b is compensated, and the resistance generated in the first source diffusion layer 71a and the first drain diffusion layer 71b is removed. The accumulation layer is formed along the sidewalls of the inclined first source diffusion layer 71a and first drain diffusion layer 71b. Therefore, as shown by the alternate long and short dash line in FIG. 4, the current path from the channel surface 65 to the contact on the surface of the silicon substrate 61 can be made close to a straight line, thereby shortening the current path, thereby reducing the parasitic resistance.
[0095]
Also, one end of the storage layer, that is, the end of the storage layer passing through the gate edge and in contact with the normal to the surface of the gate insulating film 67 is located shallower than the channel bottom and has a sufficiently high impurity concentration. Can be located at a point. Accordingly, without causing the short channel effect, the impurity distribution depth a at this position is deepened, and at the same time, the impurity distribution depth in the region outside the gate edge is deepened, and the resistance of this region can be lowered. Here, the impurity depth is the depth of the impurity distribution in the normal direction with respect to the surface of the first source diffusion layer 71a or the first drain diffusion layer 71b. In order to reduce the resistance, the impurity concentration integrated in the direction of the impurity distribution depth a is 1 × 10 ¹³ cm ^-2 The above is desirable. In addition, since the edge of the accumulation layer is located shallower than the channel bottom, even if impurities are distributed deeply from this position and the resistance of the region outside the gate edge is lowered, the short channel effect does not occur. .
[0096]
Further, since the distance between the first source diffusion layer 71a and the gate electrode 68 and the first drain diffusion layer 71b and the gate electrode 68 can be increased except for the region to be the storage layer, the parasitic capacitance can be reduced. Further, since the first source diffusion layer 71a and the first drain diffusion layer 71b have a concave transistor structure formed at a position shallower than the channel surface 65, the source and drain are formed in the same plane as the channel. The short channel effect which arises can be suppressed. In this concave transistor structure, the lower surfaces of the source and drain are located higher than the channel, particularly in the vicinity of the region where the first source diffusion layer 71a and the first drain diffusion layer 71b are opposed to the gate electrode 68. It is possible to suppress the short channel effect.
[0097]
If the lower end adjacent to the source and drain of the gate electrode 68 is formed linearly with a slope or rounded as shown in FIG. 4, an inversion layer or accumulation generated near the source and drain at both ends of the gate due to the electric field of the gate. The carrier concentration of the layer can be increased, and the resistance in the channel region in the vicinity of both ends of the gate and in the source and drain ends can be reduced. In addition, since the current path from the channel surface 65 to the source and drain is formed at an obtuse angle by this carrier distribution, work lost when electrons travel along an acute path can be reduced, and reduction in current value can be reduced. Can do.
[0098]
Further, the second source diffusion layer 72a and the second drain diffusion are held while the junction probe at the lower ends of the inclined first source diffusion layer 71a and the first drain diffusion layer 71b is held above the channel surface 65. If the junction search of the layer 72b is deepened, the resistance of the source and drain can be further reduced.
[0099]
Further, the region where the first source diffusion layer 71a and the gate electrode 68 and the first drain diffusion layer 71b and the gate electrode 68 are opposed to each other is not necessarily formed with a gentler inclination than the right angle with respect to the silicon substrate 61. Absent. For example, in the vicinity of the bottom of the gate electrode 68, the gate insulating film 67 is formed substantially perpendicular to the surface of the silicon substrate 61, and the distance from the gate electrode 68 gradually increases from a position away from the bottom of the gate electrode 68 by a predetermined distance. Thus, even in the structure in which the surfaces of the first source diffusion layer 71a and the first drain diffusion layer 71b are formed, the same effect as the present invention is achieved.
[0100]
In this embodiment, the edge of the gate electrode 68 is located inside the recess 92, but the edge of the gate electrode 68 may be located at the boundary point between the recess 92 and the region outside the recess 92. Further, the junction position between the source and the channel region or the junction position between the drain and the channel region in the vicinity of the gate insulating film 67 may be located immediately below the edge of the gate electrode 68. The same applies to the following embodiments.
[0101]
(Second Embodiment)
FIG. 5 is a process sectional view showing an embodiment for realizing a transistor structure of the present invention having a channel region having a curvature. Here, the distance between the gate electrode and the contact on the mask is set to zero, and the contact is formed in self-alignment with the gate electrode on the source or drain having an inclination.
[0102]
Hereinafter, a method for manufacturing the concave MIS transistor according to the present embodiment will be described.
[0103]
First, on the silicon substrate 61 in the active region, SiO2 having a thickness of 0.02 μm. ₂ A film 91 is formed. Next, Si _Three N _Four A film 101 is deposited to a thickness of 0.5 μm. For example, a desired photoresist pattern (not shown) is used as a mask to form Si _Three N _Four An opening of the film 101 is formed. Next, as shown in FIG. _Three N _Four The recess 102 is formed by etching the silicon substrate 61 by RIE using the film 101 as a mask. By adopting the configuration of the recess 102 as shown in the figure, the source region and the drain region connected to the contact can be formed higher than the channel region.
[0104]
Next, SiO is filled so as to fill the recess 102. ₂ A film 103 is deposited and Si _Three N _Four Planarization is performed by CMP using the film 101 as a stopper. Then, the region where the gate electrode is to be formed by RIE using the resist pattern as a mask by lithography using a photoresist. ₂ The film 103 is etched and opened. Further, as shown in FIG. 5B, the silicon substrate 61 at the bottom of the opening is etched to form a recess 104 in the channel region. At this time, the recess 104 is formed to have a substantially uniform curvature by adjusting the etching conditions. Next, the polymer layer (not shown) generated at the time of etching is removed to expose the surface of the silicon substrate 61. For example, heat treatment is performed in a hydrogen atmosphere at 800 ° C. for about 2 minutes to recover damage in the recess 104 caused by RIE. Process. At this time, for example, by performing heat treatment in a hydrogen atmosphere at 950 ° C. and 10 Torr for about 1 minute, it is possible to move the silicon atoms on the surface of the recess 104 by the balance of the surface energy and make the curvature of the recess more uniform. Next, if necessary, sacrificial SiO (not shown) having a thickness of about 5 nm is formed on the surface of the exposed silicon substrate 61. ₂ A film is formed by, for example, a thermal oxidation method, and channel ion implantation for threshold voltage control or the like is performed.
[0105]
Next, the sacrificial SiO ₂ The film is peeled off, and as the gate insulating film 105, for example, about 3 nm thick SiO ₂ A film is formed by a thermal oxidation method.
[0106]
Next, SiO ₂ A conductive film is deposited so that the inside of the recess 104 surrounded by the film 103 is filled. As the conductive film, for example, polysilicon doped with phosphorus at a high concentration is used. Next, Si _Three N _Four Planarization is performed by CMP using the film 101 as a stopper, and a gate electrode 68 is formed as shown in FIG. Next, Si is obtained by hot phosphoric acid treatment. _Three N _Four Film 101 is removed, followed by SiO ₂ The film 103 is removed by hydrofluoric acid treatment to expose the surface of the silicon substrate 61 that becomes the surface of the source and drain regions adjacent to the gate electrode 68. Next, the first source diffusion layer 106a and the first drain diffusion layer 106b are formed in a self-aligned manner at the gate end by ion implantation using the gate electrode 68 as a mask. Next, annealing is performed to activate the impurities in the first source diffusion layer 106a and the first drain diffusion layer 106b.
[0107]
Next, as shown in FIG. 5D, on the surface, for example, about 0.04 μm of Si. _Three N _Four After the film is deposited, Si is performed by a process of leaving a side wall by RIE. _Three N _Four The film is partially removed, and a sidewall nitride film 107 is formed on the side surface of the gate electrode 68. The thickness of the sidewall nitride film 107 is formed so that one end of the sidewall not contacting the gate electrode 68 is included in the recess 102.
[0108]
Next, the second source diffusion layer 108a and the second drain diffusion layer 108b are formed by ion implantation using the sidewall nitride film 107 as a mask. Thereby, the resistance of the source and drain can be lowered. When the resistance of the first source diffusion layer 106a and the first drain diffusion layer 106b is sufficiently low, the second source diffusion layer 108a or the second drain diffusion layer 108b may not be formed.
[0109]
Next, SiO ₂ An interlayer insulating film 69 is deposited and planarized by CMP using the gate electrode 68 as a stopper. Next, the upper part of the gate electrode 68 is receded by about 0.1 μm by CDE, and then Si is filled so as to fill the groove on the receded gate electrode 68. _Three N _Four A film is deposited and planarized by CMP to form a protective nitride film 109. Next, contact holes to the first source diffusion layer 107a and the first drain diffusion layer 107b are opened by RIE. Since the sidewall nitride film 107 and the protective nitride film 109 are formed, RIE can be performed with the distance from the gate electrode 68 on the mask being zero.
[0110]
Next, a conductive material, for example, polysilicon is filled into the opened contact hole to form wirings 110a and 110b. In order to reduce the contact resistance, Ti or the like may be deposited on the surface of the silicon substrate 61 on the bottom surfaces of the wirings 110a and 110b to be silicided.
[0111]
When the contact resistance of the source and drain is reduced by silicidation, the surface of the silicon substrate 61 is silicidized, so that there is a problem that the bottom surface of the silicidized portion is close to the junction of the diffusion layer and leakage current increases. Therefore, it is necessary to form a sufficiently deep diffusion layer for silicidation, and it is generally difficult to satisfy this requirement if a shallow junction is formed in order to reduce the short channel effect. In the present invention, since the source and drain are positioned higher than the channel region with an inclination, the diffusion layer of the source or drain can be deepened, and contact resistance can be easily reduced by silicidation.
[0112]
As described above, according to the present embodiment, the concave portion that defines the interface between the channel region and the gate insulating film is formed in a curved shape so that the current path is linear when viewed locally. The Accordingly, the current path can be shortened and the breakdown voltage of the gate insulating film 105 can be improved and the mobility of electrons can be prevented from being deteriorated as compared with a structure having a current path with a corner.
[0113]
Further, since the source and drain accumulation layers connected to the channel region are positioned with an inclination on the upper surface of the channel region, the short channel effect is suppressed.
[0114]
Next, the advantage by uniformly forming the radius of curvature of the channel region formed inside the recess will be described.
[0115]
When there is a part in the channel with a smaller radius of curvature compared to the peripheral part, the electric field due to the gate electrode diverges in this part compared to the peripheral part with a large radius of curvature, and carriers induced in the inversion layer are reduced. Resistance increases. When the curvature radius is uniform across the channel, this carrier reduction occurs across the channel, so the carrier concentration can be increased overall by lowering the substrate concentration across the channel. That is, a concave transistor having a uniform radius of curvature can be set to have a lower resistance and a lower substrate concentration than a concave transistor having a small radius of curvature or a corner portion. The low substrate concentration has an advantage that the junction leakage current with the drain diffusion layer can be suppressed.
[0116]
Furthermore, in the present embodiment, the area for transistor formation can be greatly reduced by forming the contact in a self-aligning manner with the distance between the gate and the contact on the mask being zero.
[0117]
(Third embodiment)
FIG. 6 is a cross-sectional view showing the overall configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present embodiment is a modification of the first embodiment. By adjusting the conditions of the ion implantation 93 shown in FIG. Impurity regions 94a and 94b are added to the source diffusion layer 71a and the first drain diffusion layer 71b.
[0118]
As shown in FIG. 6, the lower ends of the first source diffusion layer 71a and the first drain diffusion layer 71b are formed to cover the corner portion at the end of the channel surface 65, and impurity regions 94a and 94b covering the corner portion are formed. Is formed. In this structure, the carrier density of the corner portion at the end of the channel surface 65 also increases following the accumulation layer formed in the portion corresponding to the gate end of the first source diffusion layer 71a and the first drain diffusion layer 71b. The current value that flows when the transistor is operating can be further increased.
[0119]
The junction depth of the impurity regions 94a and 94b with respect to the channel surface 65 may be formed to be about the thickness of the inversion layer, for example, 0.01 μm or less. At the surface of the portion where the impurity regions 94a and 94b having inclinations are opposed to the gate electrode 68 through the gate insulating film 67, sufficient carriers are induced by the electric field of the gate electrode 68 during operation, and a storage layer is formed. A current path is formed. For this reason, for example, in the case of the conventional planar transistor shown in FIG. 26, the junction depth of about 0.02 μm into the substrate 1 is assumed in order to form a current path. Since the junction depths of the regions 94a and 94b can be formed shallow, the current value can be increased while suppressing the short channel effect.
[0120]
In this way, the n-type layer that is formed at both ends of the channel region and covers the corner portion connected to the inclined first source diffusion layer 71a and the first drain diffusion layer 71b and is very shallow and about the thickness of the inversion layer. By further forming the impurity regions 94a and 94b, the same effects as in the first embodiment can be obtained, and the carrier density in the corner portion can be increased as compared with the case of the first embodiment. A value can be obtained.
[0121]
(Fourth embodiment)
7 to 12 are views showing manufacturing steps of the semiconductor device (concave MIS transistor) according to the fourth embodiment of the present invention. The present embodiment relates to a manufacturing method for realizing a structure having the features of the concave transistor structure of the first embodiment shown in FIG. The present embodiment is different from the first embodiment in that the active region 62 has a tapered shape on the silicon substrate 61 that is not covered by the bottom surface of the gate electrode 68 and inclined with respect to the side surface of the gate electrode 68. An epitaxial region made of single crystal silicon having a surface and selectively epitaxially grown is provided, and portions having a surface with a slope of this epitaxial region are used as a source and a drain having a slope.
[0122]
Hereinafter, the manufacturing method of the concave MIS transistor of this embodiment will be described with reference to FIGS. 7 to 12, (a) is a view of the semiconductor device as viewed from above, and a cross-sectional view of 12A-12A ′ to 17A-17A ′ in (a) is shown in (b), and 12B-12B ′ to 17B-17B. 'Cross sectional view is shown in (c), and 12C-12C' to 17C-17C 'sectional views are shown in (d).
[0123]
As shown in FIG. 7B, the entire surface of the active region 62 is SiO. ₂ The film 131 is formed by, for example, a thermal oxidation method, and then SiN is formed in a region where the gate electrode 68 is to be formed using a lithography technique. _Four A dummy gate 132 made of a film is formed. Next, the oxide film in the region not covered with the dummy gate 132 in the active region 62 is removed by, for example, diluted hydrofluoric acid. Reference numeral 131 in FIG. 7B indicates that the remaining SiO is located under the dummy gate 132. ₂ It is a membrane.
[0124]
Next, a crystalline silicon layer is selectively epitaxially grown on the active region 62 using the dummy gate 132 as a mask and the silicon substrate 61 as a nucleus. When solid phase growth is performed on a surface on which a substance that blocks the distribution of silicon crystals serving as nuclei is disposed, such as the dummy gate 132, the edge of the silicon region does not grow by being piled up directly on the edge. A surface with a so-called facet appears. In the case of the present embodiment, the fact that the (111) plane has the smallest surface energy and the slowest growth rate in the silicon crystal is utilized, and a facet that forms an angle of about 50 degrees with the surface of the silicon substrate 61 at the (111) plane is used. .
[0125]
Specifically, first, in the LPCVD apparatus, the surface of the silicon substrate 61 in the exposed active region 62 is annealed in a hydrogen atmosphere at 900 ° C. for 180 seconds, for example. In the same chamber, for example, at 600 ° C. and 100 Torr, hydrogen gas 10 slm, SiH _Four Amorphous silicon is deposited on the entire surface for 28 seconds with a gas flow rate of 1 slm.
[0126]
Further, in the same chamber continuously, single crystal silicon is heated to 600 ° C., H ₂ When solid phase growth is performed by annealing in an atmosphere for 80 seconds, the silicon silicon crystal on the substrate surface serves as a nucleus and the amorphous silicon turns into single crystal silicon. At this time, SiO ₂ The portions in contact with the surfaces of the film 131 and the dummy gate 132 are not single-crystallized, and SiO ₂ Side walls having an angle of 50 degrees with respect to the surface of the silicon substrate 61 are formed with the film 131 and the dummy gate 132 as one end.
[0127]
In this manner, an epitaxial silicon region having an inclination with respect to the silicon substrate 61 in a self-aligned manner with respect to the formation region of the dummy gate 132 is selectively formed on the surface of the silicon substrate 61. Next, the portion remaining as amorphous silicon without being single-crystallized is removed with hydrofluoric acid to form a selective growth epitaxial region 133 shown in FIG. 7B.
[0128]
Next, as shown in FIG. 8B, the selective growth epitaxial region 133 and the dummy gate 132 are covered, for example, 10 nm of SiO. ₂ A film 141 is formed by a CVD method. SiO formed on the epitaxial region 133 ₂ The film 141 serves as a protective film for the ion implantation 142 in the next process. On the other hand, SiO on the region where the lower end of the side surface of the dummy gate 132 and the end of the epitaxial region 133 are in contact with each other. ₂ The film 141 is a film for forming end portions on the source and drain sides of the gate electrode 68 to be formed later on the sloped source and drain based on the difference from the thickness of the gate insulating film 171. The shape of the gate end 172 having the inclination shown in FIG. This SiO ₂ An active region and a gate electrode formation region which are thickened by the deposition of the film 141 are shown at 143 in FIG.
[0129]
Next, ion implantation 142 of n-type impurities is performed. After this ion implantation 142, for example, by thermal diffusion annealing that also serves as activation at 900 ° C. for 30 seconds by RTA, the implanted impurities are formed to a region facing the gate end 172 having a slope shown in FIG. The second source diffusion layer 152a and the second drain diffusion layer 152b shown in FIG. 9B are formed by diffusion. By performing ion implantation 142 on the surface having the inclination of the selective growth epitaxial region 133, the first source diffusion layer 151a and the first drain having the inclination due to the epitaxial layer facets are simultaneously formed on the surface having the inclination of the epitaxial region 133. A diffusion layer 151b is formed. The conditions for the ion implantation 142 may be the same as in the first embodiment, for example.
[0130]
Next, after depositing polysilicon on the entire surface of the device, CMP 153 is used to remove the upper-layer polysilicon using the dummy gate 132 as a stopper to form a polysilicon film 154 exposing the upper end of the dummy gate 132. The material deposited on the entire surface of the device is not limited to polysilicon, but can be variously changed depending on the material of the dummy gate 132 such as TEOS.
[0131]
Next, as shown in FIG. 10B, the dummy gate 132 is removed using hot phosphoric acid to form a recess 161 corresponding to the gate electrode portion. The recess 161 is a region where the gate insulating film 171 and the gate electrode 68 are embedded.
[0132]
Prior to the formation of the gate electrode 68, the V film is selectively formed in the concave portion using the polysilicon film 154 and the photoresist as a mask if necessary. _th Channel ion implantation 162 is performed for control. By performing channel ion implantation 162 at this stage, the ion implantation layer 163 can be selectively formed in the channel region. By this method, the impurity concentration in the region where the second source diffusion layer 152a and the second drain diffusion layer 152b are formed can be reduced as compared with the case where non-selective channel ion implantation is used. The junction leakage current of the source and drain can be reduced, and the junction capacitance can be reduced.
[0133]
Next, SiO formed on the bottom and side walls of the recess 161. ₂ Films 131 and 141 are removed. The recessed portion 161 after the removal has a tapered portion having the same inclination as the side surface of the second source diffusion layer 152a and the second drain diffusion layer 152b between the bottom surface and the side wall. That is, SiO formed on the side wall of the recess 161 ₂ The side wall of the recess 161 is widened by the thickness of the film 141, but SiO 2 ₂ Since the film 141 is formed on the inclined side surface of the epitaxial region 133, SiO ₂ This is because the film 141 is removed and a part of the inclined epitaxial region 133 is exposed.
[0134]
Next, as shown in FIG. 11B, a gate insulating film 171 is formed in the recess 161 by, for example, thermal oxidation. Note that as the gate insulating film 171, CVD-SiO ₂ Film, CVD-SiON film, CVD-Si _Three N _Four A laminated film including a film may be used. This gate insulating film 171 is made of SiO. ₂ Thinner than the film 141, for example, 3.5 nm of SiO ₂ It is formed by a film. Thus, SiO ₂ By forming the gate insulating film 171 thinner than the film 141, the boundary surface between the gate insulating film 171 and the first source diffusion layer 151a and the boundary surface between the gate insulating film 171 and the first drain diffusion layer 151b are changed into the region 151a. And a gate end 172 having the same inclination as the side surface of 151b.
[0135]
Next, in order to form the gate electrode 68, a conductive film is deposited on the entire surface so as to fill the recess 161, and then the conductive film outside the recess 161 is polished and removed by CMP. The first source diffusion layer 151a and the first drain diffusion layer 151b facing the gate end portion 172 having the slopes at both ends of the gate electrode 68 are portions that operate as a storage layer. A metal film can be used as the conductive film for forming the gate electrode 68. This is because the gate electrode 68 is not affected by the high temperature process because the high temperature annealing process for activating the source and drain is finished. Specifically, for example, a laminated structure of TiN and Al is used.
[0136]
Next, as shown in FIG. 12B, the polysilicon film 154 is removed by the CDE method to form an interlayer insulating film 69 on the entire surface. In order to remove the polysilicon film 154 by the CDE method, a cap of an insulating film layer is used on the gate electrode 68 according to the type of the conductive film used for the gate electrode 68, and then the CMP method or the like is used. This is performed after removing the insulating film on the polysilicon film 154 and exposing the surface. The process after the formation of the interlayer insulating film 69 is the same as that in the first embodiment.
[0137]
In the recessed transistor formed by the above steps, the surface corresponding to the substrate surface 66 in the first embodiment is the epitaxial layer surface 134. The channel surface 65 of the concave transistor structure is the surface of the silicon substrate 61, which is different from the case where the surface of the silicon substrate 61 etched by the RIE method is used as the channel surface 65 in the first embodiment.
[0138]
In the above process, a selective epitaxial region 133 for the source and drain having an inclination of about 50 degrees with respect to the surface of the silicon substrate 61 using the (111) plane by solid phase growth using a dummy gate 132 made of a nitride film. However, instead of this, for example, a (311) plane having a gentler inclination of about 30 degrees can be used. In this case, SiO ₂ A selective epitaxial region is formed by vapor phase growth using a dummy gate formed of a laminated film of 50 nm film and 50 nm nitride film.
[0139]
According to the present embodiment, since the positions of the source and the drain that are inclined in a self-aligned manner with the gate position determined by lithography at the time of manufacturing the dummy gate 132 are determined, Compared to the fact that a separate lithography process is required when forming the gate electrode, there are fewer factors causing variations in channel length.
[0140]
Further, the channel surface 65 is not exposed to the etching by the RIE method, and the surface of the silicon substrate 61 is not damaged during the etching. By using the selective epitaxial region 133, the advantage of suppressing the short channel effect of the concave transistor can be utilized while using the same high-quality silicon surface as that of the planar transistor. By obliquely growing the surface of the portion adjacent to the gate electrode 68 of the epitaxial region 133, the first source diffusion layer 151a and the first drain diffusion layer 151b having an inclination can be formed.
[0141]
In this embodiment, the ion implantation layer 163 for controlling the threshold voltage can be selectively formed in the channel portion under the gate electrode 68. In order to realize the selective epitaxial layer used in this embodiment, in order to selectively grow a silicon layer excluding the region where the gate electrode 68 is provided, Si _Three N _Four A dummy gate 132 using is used. That is, after manufacturing other parts of the transistor using the dummy gate 132, the dummy gate 132 is removed, and the gate electrode 68 is embedded (damascene gate) using a so-called damascene process (inlaid process). By using this damascene gate process, ions can be selectively implanted only into the channel portion.
[0142]
(Fifth embodiment)
13 to 14 are diagrams for explaining a concave MIS transistor according to a fifth embodiment of the present invention. The present embodiment relates to a manufacturing method for realizing a structure having the characteristics of the first concave MIS transistor structure of the present invention shown in FIG. This embodiment is the same as the fourth embodiment up to the middle of the manufacturing process, and a detailed description of the parts common to the fourth embodiment is omitted.
[0143]
In the fourth embodiment, contact holes 73 a and 73 b to the second source diffusion layer 152 a and the second drain diffusion layer 152 b are formed on the epitaxial region 133 apart from the gate electrode 68. In order to prevent a short circuit between the gate and the wiring, the gate electrode 68 and the wirings 70a and 70b are formed when the contact holes 73a and 73b are formed in the interlayer insulating film 69 by lithography and RIE etching. This is because it is necessary to achieve separation of these, and this is realized by taking a sufficient distance. On the other hand, in order to realize miniaturization of the integrated circuit, it is desirable to reduce the distance between the contact holes 73a and 73b and the gate electrode 68.
[0144]
Therefore, in this embodiment, a side wall 191 made of a nitride film is formed on the first source diffusion layer 151a and the first drain diffusion layer 151b having an inclination so that the distance between the gate and the contact on the mask is substantially reduced. As zero, contacts are formed in a self-aligned manner, and the area for transistor production is greatly reduced.
[0145]
A method for manufacturing the concave MIS transistor of this embodiment will be described with reference to FIGS. The steps from forming the second source diffusion layer 152a and the second drain diffusion layer 152b using the dummy gate 132, removing the dummy gate 132 to form the recess 161, and forming the ion implantation layer 163 are as follows. This is the same as the process of FIGS. 7 to 10 shown in the fourth embodiment.
[0146]
After the steps shown in FIGS. 10 to 15, as shown in FIGS. 13 to 18, SiO formed on the bottom and side walls of the recess 161. ₂ The films 131 and 141 are removed, and a gate insulating film 171 is formed in the recess 161 by, for example, thermal oxidation. This gate insulating film 171 is made of SiO. ₂ By forming it thinner than the film 141, a gate end 172 having an inclination with respect to the surface of the silicon substrate 61 is formed.
[0147]
Next, a conductive film is deposited on the entire surface so as to fill the recess 161, and then the conductive film outside the recess is polished and removed by CMP. Thereafter, the upper portion of the gate electrode 68 in the recess 161 is etched by 10 nm by the RIE method, and then a nitride film is deposited. After the nitride film is deposited, the nitride film outside the recess 161 is polished and removed by a CMP method to form a protective nitride film 192 for the gate electrode 68.
[0148]
Next, after the surface of the polysilicon film 154 is cleaned by, for example, hydrofluoric acid treatment, the polysilicon film 154 is removed by the CDE method. Next, Si having a thickness of about 20 nm is formed on the entire surface. _Three N _Four After depositing the film, this Si _Three N _Four The entire surface of the film is etched by the RIE method, so as to leave a sidewall on the first source diffusion layer 151a and the first drain diffusion layer 151b having an inclination. _Three N _Four A side wall 191 is formed. This Si _Three N _Four An active region and a gate electrode formation region which are thickened by the deposition of the film are shown at 194 in FIG.
[0149]
Next, as shown in FIG. 14B, an interlayer insulating film 69 is deposited on the entire surface, and contact holes 201a and 201b are formed by RIE. The mask pattern of the contact holes 201a and 201b of this embodiment is designed such that the distance from the gate electrode 68 is zero or overlaps the gate electrode 68, and RIE for opening contacts on the source and drain is performed. Even if this is performed in the vicinity of the gate electrode 68, the gate electrode 68 is protected by the side wall 191 and the protective nitride film 192, so that the wiring 203 a and 203 b are embedded in the contact hole without short-circuiting the gate electrode 68. Can be formed.
[0150]
In the present embodiment, Si is formed on the outer surface of the gate end portion 172 having the same inclination as the first source diffusion layer 151a and the first drain diffusion layer 151b. _Three N _Four By forming the side wall 191, the parasitic capacitance can be suppressed by increasing the distance between the gate electrode 68 and the source and drain while suppressing the short channel effect in the concave channel MIS transistor. Further, by forming the wirings 203a and 203b using self-aligned contacts, the transistor area can be reduced, and the distance between the channel and the wirings 203a and 203b can be minimized to suppress parasitic resistance.
[0151]
Further, in this embodiment, the insulation of the first source diffusion layer 151a and the first drain diffusion layer 151b connecting the storage layers of the first source diffusion layer 151a and the first drain diffusion layer 151b and the wirings 203a and 203b. Since the surfaces of the films 171 and 191 are linearly formed, the current path can be shortened to further reduce the parasitic resistance, and the transistor can be further reduced in resistance.
[0152]
(Sixth embodiment)
15-19 is a figure for demonstrating 6th Embodiment of this invention. In the present embodiment, the recess is formed by using RIE as in the first embodiment, but the method of forming the source and drain is different.
[0153]
Specifically, in the first embodiment, the source diffusion layer 71a and the drain diffusion layer 71b having an inclination are formed after the formation of the concave portion, the gate insulating film 67, and the gate electrode 68, whereas in the present embodiment, the concave portion is formed. Impurity regions to be the source and drain are formed on the surface of the silicon substrate 61 before formation, and the surface of the silicon substrate 61 is etched with inclined side surfaces, thereby forming inclined source diffusion layers and drain regions. It is that you are. Hereinafter, the manufacturing process of this embodiment will be described with reference to FIGS.
[0154]
First, as shown in FIG. 15B, an element isolation insulating film 64 is formed on the periphery of the active region 62 on a p-type silicon substrate 61. For example, a trench having a depth of about 0.35 μm is dug using a reactive ion etching (RIE) method, and SiO 2 is etched into the trench. ₂ By embedding the insulating film 64, etc., element isolation called STI (Shallow Trench Isolation) is performed. Next, a sacrificial SiO film having a thickness of about 10 nm is formed on the active region 62. ₂ After the film 211 is formed by, for example, a thermal oxidation method, a channel ion implantation layer for adjusting a threshold voltage is formed (not shown), and then a concentration of 3 × 10 10 serving as source and drain impurity regions. ²⁰ cm ^-3 A moderate impurity region 212 is formed using ion implantation.
[0155]
In the case of a so-called CMOS (Complementary Metal-Oxide-Semiconductor) structure in which n-channel and p-channel MIS transistors are formed on the same substrate, a p-type well is formed in the n-channel transistor formation region of the silicon substrate 61. 212 is formed as an n-type impurity region. Hereinafter, in this embodiment, the case of an n-channel transistor will be described. In the case of a p-channel transistor, the impurity type may be reversed. Further, the impurity region 212 to be the source and drain may be formed by a high concentration epitaxial region grown on the entire surface of the active region 62.
[0156]
Next, as shown in FIG. 16B, for example, a mask having the same photoresist pattern as that for forming a gate electrode, for example, as in the case of forming the recess 92 in FIG. 2B of the first embodiment. A recess 221 is formed by using RIE, and RIE damage recovery processing is performed. Following this recovery process, the impurity region 212 is activated by a heat treatment at, for example, about 800 ° C. for about 5 minutes to form the source diffusion layer 212a and the drain diffusion layer 212b.
[0157]
The vicinity of the region where the recess 221 is formed is a region for forming the channel portion of the recessed transistor and the source and drain having an inclination in the active region 62, and is obtained by selectively etching the silicon substrate 61 with an inclination. It is done. The angle between the tapered side surface of the recess 221 and the surface of the silicon substrate 61 is such that the parasitic capacitance between the gate electrode 68 and the source diffusion layer 212a and the gate electrode 68 and the drain diffusion layer 212b to be formed later in FIG. The RIE condition is such that it is large with respect to the vertical plane and small with respect to the horizontal plane so that the effective resistance of the source diffusion layer 212a and drain diffusion layer 212b adjacent to the gate electrode 68 is sufficiently given to reduce the parasitic resistance. For example, it is formed at an angle of 60 ° with respect to a plane perpendicular to the surface of the silicon substrate 61.
[0158]
When forming the concave portion 221 using the mask of the gate electrode 68, the concave portion is also formed in the portion of the element isolation insulating film 64 connected from the gate to the contact, leaving a sufficient thickness of the element isolation insulating film 64. Also good.
[0159]
Next, after forming the gate insulating film 67 as shown in FIG. 17B, the edge of the gate electrode 68 is included inside the recess 221, located outside the region of the channel surface 65, and The gate electrode 68 and the source diffusion layer 212 a and the gate electrode 68 and the drain region 212 b are formed so as to have a region that overlaps with the gate insulating film 67 therebetween.
[0160]
As the gate insulating film 67, a stacked film including an insulating film formed by a low temperature process is used. That is, the gate insulating film 67 is formed by heat treatment, but since the impurity region 212 to be the source and drain is formed before the gate insulating film 67, the junction surface of the impurity region 212 is different from the case of the first embodiment. This is because it is necessary to consider so that the depth does not become deeper than the channel surface 65 toward the silicon substrate 61 side. Specifically, as a material of the gate insulating film 67, for example, CVD-SiO ₂ Film, CVD-SiON film, CVD-Si _Three N _Four A laminated film including a film is used.
[0161]
The gate electrode 68 is patterned so as to have a region that overlaps with the impurity region 212 through the gate insulating film 67 because the source electrode is located shallower than the depth of the channel surface 65 and continues to the channel inversion layer during operation. And a region for forming a drain accumulation layer. If the recess is also formed in the element isolation insulating film 64 when the recess 221 is formed, the thickness of the gate wiring on the element isolation insulating film 64 can be increased by the thickness of the recess. Can be reduced.
[0162]
Next, as shown in FIGS. ₂ After the interlayer insulating film 69 is formed, contact holes 73a and 73b are formed by using the same process as described in the first embodiment to form wirings 70a and 70b, and a passivation film (not shown) is formed on the entire surface. By forming, the transistor partial manufacturing process of the fourth embodiment is completed. The source diffusion layer and the drain region having an inclination in the fourth embodiment are shown by oblique lines in FIG.
[0163]
FIG. 20 is a diagram showing an overall configuration of a concave MIS transistor according to a modification of the present embodiment. FIG. 20 (a) is a top view, and FIGS. 20 (b) to 20 (d) are respectively in FIG. 20 (a). 25A-25A ′ sectional view, 25B-25B ′ sectional view, and 25C-25C ′ sectional view are shown. In the following modified example, the same reference numerals are given to portions common to the first embodiment, and detailed description thereof is omitted.
[0164]
In the case of the first embodiment shown in FIG. 1B, not only the interface between the first source diffusion layer 71a and the first drain diffusion layer 71b adjacent to the gate electrode 68 but the gate insulating film 67, The boundary surface with the silicon substrate 61 is also inclined with respect to the surface of the silicon substrate 61. In this modification, as shown in FIG. 20B, the main surface of the source diffusion layer 111a and the drain diffusion layer 111b. Only the boundary surface portion with the gate insulating film 67 serving as a simple current path is formed with an inclination with respect to the surface of the silicon substrate 61, and the boundary surface portion with the silicon substrate 61 has a junction depth of zero or minus with respect to the channel surface 65. And formed in parallel with the surface of the silicon substrate 61.
[0165]
The main current path during the transistor operation in this modification is the same as that in the present embodiment. Further, the source diffusion layer 111a and the drain diffusion layer 111b are formed above the channel surface 65, and the source diffusion layer 111a and the drain diffusion layer 111b are formed with an inclination with respect to the surface of the silicon substrate 61. As in the present embodiment, the short channel effect can be suppressed and the parasitic resistance and parasitic capacitance can be reduced.
[0166]
This modification differs from the present embodiment in that the source and drain are formed after the formation of the gate electrode 68, as in the first embodiment. Even in this case, substantially the same structure as that of the present embodiment can be realized.
[0167]
(Seventh embodiment)
FIG. 21 is a cross-sectional view showing the overall configuration of a semiconductor device according to the seventh embodiment of the present invention. This embodiment is a modification of the first embodiment, and a description of parts common to the first embodiment is omitted. In the present embodiment, the radius of curvature of the current path is increased by using a curve so that the current path is linear when viewed locally, and the current path is suppressed while suppressing the short channel effect. Form short.
[0168]
The manufacturing process of the semiconductor device according to this embodiment is almost the same as that of the first embodiment. In the present embodiment, when the recesses 92 of FIGS. 2 to 7 of the first embodiment are formed using RIE, the side surface or the channel region having the inclination of the recesses 92 is defined by adjusting the etching conditions. Is formed with roundness.
[0169]
The source and drain are formed not only with the first source diffusion layer 261a and the first drain diffusion layer 261b, but also with a second source diffusion layer 262a and a second drain diffusion layer 262b in order to compensate for the thickness. To do.
[0170]
After forming the gate insulating film 263, the edge of the gate electrode 68 is included in the recess 221, located outside the channel region, and the gate electrode 68 is interposed between the first source through the gate insulating film 263. The diffusion layer 261a and the first drain diffusion layer 261b are formed so as to overlap with each other.
[0171]
This embodiment differs from the conventional concave transistor in the following points. The current path is rounder and shorter than the conventional concave transistor shown in FIG. This is because the etching is performed so that the channel region, the source diffusion layer 261a, and the drain diffusion layer 261b are rounded. Further, by forming the gate insulating film 263 formed on the side surface of the gate electrode 68 with a round shape, the effective thickness of the insulating film between the gate electrode 68 and the source and drain is increased, thereby suppressing parasitic capacitance. ing. Further, the source and drain accumulation layers connected to the channel region are positioned with an inclination on the upper surface of the channel region, thereby suppressing the short channel effect. Accordingly, since the current path from the channel to the storage layer is also formed with a round shape, a reduction in the amount of current can be prevented.
[0172]
In the first embodiment, the carrier distribution is made close to a straight line by changing the angle from an acute angle to an obtuse angle with respect to the corner portions at both ends of the channel surface 65 of the normal concave transistor in FIG. In this embodiment, the obtuse corner portions at both ends of the channel region are made to have a gentle structure without further corners, thereby improving the breakdown voltage of the gate insulating film 263 and preventing the mobility of electrons in the corner portions from deteriorating. Realized.
[0173]
Further, the radius of curvature can be made larger than that of the conventional concave transistor in which the corner portion of the channel is gently formed, and the breakdown voltage can be improved or the mobility deterioration can be prevented more effectively.
[0174]
Further, the advantage of uniformly forming the radius of curvature of the channel region formed inside the recess is the same as that of the second embodiment.
[0175]
(Eighth embodiment)
FIG. 22 is a cross-sectional view showing the overall configuration of the semiconductor device according to the eighth embodiment of the present invention. Description of the parts common to the sixth embodiment in this embodiment is omitted.
[0176]
In this embodiment, the present invention is applied to a so-called buried channel transistor in a planar transistor. The buried channel transistor can be adjusted to a desired value according to the work function of the gate electrode 68 by providing regions of the same type as the source and drain in the channel portion, and is particularly effective in a so-called CMOS circuit. .
[0177]
For example, in the case of an n-type transistor, a gate insulating film 67 and a gate electrode 68 are formed on a p-type silicon substrate 61 via an n-type buried channel 271. In the present embodiment, when the recess 221 in FIG. 16B of the fourth embodiment is formed using RIE, the etching conditions are adjusted so that the etching depth is shallower than the bonding surface of the impurity region 212. The buried channel 271 is formed.
[0178]
In the buried channel type concave transistor of FIG. 22, the edge of the gate electrode 68 is formed so as to be included in the concave portion 221 and on the side surface having the inclination of the concave portion 221. Since it is a buried channel type, the polarity of the source and drain and the polarity of the buried channel 271 are the same. Accordingly, in the case where the conventional recessed transistor of FIG. 29B is used as a buried channel, the inversion layer 47 on the side surface of the recess and the inversion layer 46 on the bottom surface of the recess are respectively replaced with storage layers (not shown).
[0179]
Corresponding current paths are the same as those indicated by arrows in the conventional concave transistor structure of FIG. The current path in this embodiment of FIG. 22 is shown with a dashed-dotted line.
[0180]
The structure of FIG. 22 is superior to the other embodiments in that the threshold voltage can be adjusted as described above. In the structure of another embodiment in which the corner portions at both ends of the channel surface 65 that are not buried channels are exposed, when a channel inversion layer is formed in this corner portion, an electric field diverges in the corner portion, thereby causing a carrier density of the corner portion. Becomes lower than the carrier density at the channel surface 65 and causes a decrease in the current value.
[0181]
In the recessed transistor of FIG. 22, by covering the sharp corners of the corner portions at both ends of the channel surface 65 with the impurity regions without exposing them, the carrier density in the corner portions is increased, and the current caused by the low carrier density in the corner portions. The decline is suppressed.
[0182]
The sixth, seventh, and eighth embodiments are superior to the first embodiment in that the source diffusion layer and the drain diffusion layer are formed using the gate electrode 68 formed in the recess 92 as a mask in the first embodiment. When the misalignment between the concave portion 92 and the gate electrode 68 occurs due to the ion implantation 93 for forming, the second source diffusion layer 72a and the second drain diffusion layer 72b are formed asymmetrically. In the sixth to eighth embodiments, the recess 161 is formed by etching the impurity region formed symmetrically in advance, so that the misalignment between the gate electrode 68 and the impurity region does not occur, and the lower ends of the source and drain are always symmetrical. It is to be formed.
[0183]
The sixth, seventh, and eighth embodiments are superior to the fourth embodiment in that the fourth embodiment uses a dummy gate to form the selective epitaxial region 133 and the process is complicated. On the other hand, in this embodiment, the number of process steps is small and the process is short, so that the cost can be reduced.
[0184]
(Ninth embodiment)
23 to 24 are views for explaining a semiconductor device according to a ninth embodiment of the present invention. This embodiment implements the structure shown in FIGS. 15 to 20 of the sixth embodiment.
[0185]
The semiconductor device according to this embodiment is different from the second embodiment in that the first embodiment has a first source having an inclination due to the epitaxial layer facet after the formation of the selective epitaxial region 133, the gate insulating film 67, and the gate electrode 68. In contrast to the formation of the diffusion layer 151a and the first drain diffusion layer 151b, in this embodiment, the epitaxial regions 281a and 281b are formed as impurity regions serving as the source and drain by containing high-concentration impurities. In other words, the boundary surface with the gate insulating film 171 has an inclination, and the junction surface with the silicon substrate 61 forms a source and a drain with an inclination parallel to the surface of the silicon substrate 61. The source and drain are formed by the same manufacturing process as in the fourth embodiment.
[0186]
Hereinafter, the manufacturing process of the present embodiment will be described in comparison with the second embodiment. First, as shown in FIG. 23A, selective epitaxial layer impurity regions 281a and 281b are formed on the silicon substrate 61 on which the dummy gate 132 is formed. The region where the selective epitaxial layer impurity regions 281a and 281b are formed is the same region as the region where the selective epitaxial region 133 is formed in FIG.
[0187]
In this embodiment, when depositing amorphous silicon on the entire surface, hydrogen gas and SiH _Four In addition to gas, for example arsine AsH _Three Supply 20 sccm of gas. The difference between the selective growth epitaxial region 133 and the selective growth epitaxial layer impurity regions 281a and 281b is that the selective growth epitaxial region 133 is formed as a crystalline silicon layer containing no impurities, whereas the selective growth epitaxial layer impurity region 281a and 281b is a high-concentration impurity under the above conditions, that is, for example, in the case of an n-type concave MOSFET, 3 × 10 ²⁰ cm ^-3 It is formed to include about As.
[0188]
Next, the entire surface of the device is SiO. ₂ The film 141 is formed as a protective film (FIG. 23B). This is the same as FIG. 8B, but in this embodiment, ion implantation 142 and activation annealing are not performed. This is because the selective growth epitaxial layer impurity region has already been formed containing a high concentration of impurities, so that it is not necessary to implant impurities. Next, a polysilicon film 154 exposing the upper layer of the dummy gate 132 is formed (FIG. 23C). This is the same as FIG. 11B.
[0189]
The subsequent processes are performed in the same manner as in the second embodiment, and the completed concave transistor is shown in FIGS. 24A is a top view, and FIGS. 24B to 29D are 29A-29A ′, 29B-29B ′, and 29C-29C ′ sectional views of FIG. 24A, respectively. It is.
[0190]
Compared with the second embodiment, this embodiment omits the ion implantation 142 for activation of the source and drain impurity regions and the activation annealing step thereof, thereby simplifying the process. Further, after the impurity regions 281a and 281b for forming the source and drain having an inclination are formed on the silicon substrate 61 in advance, the gate insulating film 171 and the gate end portion 172 having an inclination are formed, so that the gate electrode 68 can be automatically formed outside the channel from the junction position of the source / drain impurity region having an inclination and on the side surface of the recess including the source and drain having an inclination. The insulating film 171 is automatically formed with a region overlapping with the source and drain with the insulating film 171 interposed therebetween.
[0191]
Similar to the sixth embodiment, the present embodiment has impurity regions 221a and 221b that serve as a source and a drain whose joint surfaces are inclined parallel to the surface of the silicon substrate 61. The advantage of this embodiment compared to the sixth embodiment is that the channel is formed because the selective epitaxial growth using the nitride film on the channel portion as a mask without using RIE to form the recess. The substrate surface to be processed is not damaged during etching, and the substrate surface protected by the nitride film can be used for the channel.
[0192]
In addition, since the source and drain are formed by the impurity regions 281a and 281b having a tilt in a self-aligned manner using selective epitaxial growth, a lithography process is performed at the time of forming the recess and the gate electrode 68 inside the recess in the sixth embodiment, respectively. Compared to the need for high-precision alignment, there are fewer factors causing structural variations.
[0193]
Furthermore, in the sixth embodiment, after the element isolation insulating film 64 of FIG. 15B is formed, the recess 221 is etched so that the side surface of the element isolation insulating film 64 is exposed as shown in FIG. However, depending on the shape of the side surface of the element isolation insulating film 64 such as the inclination of the side surface, the side surface is not exposed and the silicon portion remains, which may affect the element characteristics. In the case of the present embodiment, the source and drain are formed as convex portions using an epitaxial layer selectively formed on the substrate, as shown in FIG. Further, since the channel portion and the inclined source and drain are formed as the concave portion together with the formation of the concave portion, the side surface of the element isolation insulating film 64 in FIG. 23B is not exposed, and this side surface in the sixth embodiment is not exposed. The influence of the shape on the element characteristics can be avoided.
[0194]
(10th Embodiment)
FIG. 25 is a cross-sectional view showing the overall configuration of the semiconductor device according to the tenth embodiment of the present invention. The present embodiment shows a case where the semiconductor device manufacturing method according to the ninth embodiment is applied to a buried channel type concave transistor. Description of parts common to the ninth embodiment will be omitted, and differences from the ninth embodiment will be described below.
[0195]
In the buried channel type concave transistor according to this embodiment, the buried channel impurity region 301 is also formed on the surface of the active region. In other words, an impurity region 301 having the same polarity as the source and drain is formed on the bottom surface of the gate electrode 68 on the surface of the silicon substrate 61 facing the gate insulating film 171. This buried channel type concave transistor is particularly effective in the CMOS circuit as in the eighth embodiment.
[0196]
This embodiment is manufactured by the same manufacturing method as that of the ninth embodiment, but the SiO in FIG. ₂ Before the film 131 is formed, a buried channel impurity region 301 is formed on the active region 62 by, for example, ion implantation, and then a process similar to the process described in the ninth embodiment is performed. As a result, the epitaxial regions 281a and 281b serving as the source and drain can be connected by the region 301 having the same polarity.
[0197]
As described above, according to the present embodiment, it is possible to realize a structure having both the advantages shown in the eighth embodiment and the ninth embodiment.
[0198]
In the above-described embodiment, it is a matter of course that the effects of the present invention can be obtained even if either the source or the drain has the structure shown in the present invention and the other has the conventional structure. .
[0199]
【The invention's effect】
As described above, according to the present invention, the gate electrode and the source and drain have regions facing each other. Therefore, since these opposing regions operate as a storage layer, the spreading resistance is removed, and the channel and the contact are connected by a low-resistivity and short-length current path, so that the parasitic resistance can be reduced.
[0200]
Further, the region operated as the storage layer is formed at a position shallower than the channel region, and it is not necessary to form the region operated as the storage layer in the same plane as the channel region, so that the short channel effect can be suppressed. .
[0201]
In addition, since the source and drain on the side surface of the gate electrode are formed with an inclination with respect to the surface of the semiconductor layer, the distance between the gate electrode and the source and the gate electrode and the drain is increased, and parasitic capacitance can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
3 is a view showing a manufacturing process of the semiconductor device according to the embodiment; FIG.
FIG. 4 is an exemplary cross-sectional view showing the main part of the semiconductor device according to the embodiment;
FIG. 5 is a diagram showing an overall configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing an overall configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a view showing a manufacturing process of the semiconductor device according to the fourth embodiment of the invention.
FIG. 8 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 9 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 10 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 11 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 13 is a view showing a manufacturing process of the semiconductor device according to the fifth embodiment of the invention.
FIG. 14 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 15 is a view showing a manufacturing process of the semiconductor device according to the sixth embodiment of the invention.
FIG. 16 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 17 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 18 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 19 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
FIG. 20 is a diagram showing an overall configuration of a semiconductor device according to a modification of the embodiment.
FIG. 21 is a diagram showing an overall configuration of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 22 is a diagram showing an overall configuration of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 23 is a diagram showing an overall configuration of a semiconductor device according to a ninth embodiment of the present invention.
FIG. 24 is a view showing a manufacturing process of the semiconductor device in the embodiment;
FIG. 25 is a diagram showing an overall configuration of a semiconductor device according to a tenth embodiment of the present invention.
FIG. 26 is a cross-sectional view showing the overall structure of a conventional planar transistor.
FIG. 27 is a diagram showing an electron concentration distribution during operation of a conventional planar transistor.
FIG. 28 is a diagram showing a current density distribution of a conventional planar transistor.
FIG. 29 is a diagram showing an overall configuration of a conventional concave transistor.
FIG. 30 is a cross-sectional view illustrating the entire structure of a conventional transistor including a source region and a drain region having an oblique substrate surface.
[Explanation of symbols]
61 ... Silicon substrate
62 ... Active region
63: Element isolation region
64: Element isolation insulating film
65: Channel surface
66 ... substrate surface
67, 105, 171, 263 ... Gate insulating film
68 ... Gate electrode
69 ... interlayer insulating film
70a-70c, 110a, 110b, 203a, 203b ... wiring
71a, 71b, 106a, 106b, 151a, 151b, 261a, 261b ... first source and drain diffusion layers
72a, 72b, 108a, 108b, 152a, 152b, 262a, 262b ... second source and drain diffusion layers
73a to 73c, 210a, 201b ... contact holes
91,103,131,141 ... SiO ₂ film
92,102,104,161,221 ... recess
93, 142, 162 ... ion implantation
101 ... Si _Three N _Four film
107: Side wall nitride film
109, 192 ... Protective nitride film
94a, 94b, 212, 301 ... impurity regions
132 ... dummy gate
133, 281a, 281b ... epitaxial region
134 ... epitaxial layer surface
171 ... Insulating film
172 ... Gate edge
153 ... CMP
154 ... polysilicon film
163 ... Ion implantation layer
191 ... sidewall
111a, 111b, 212a, 212b ... source and drain diffusion layers
271: Embedded channel

Claims (7)

A semiconductor layer having a recess having a side wall connected to the bottom surface at a gentler angle than a right angle with a bottom surface parallel to the surface of the semiconductor layer, an insulating film formed on the inner surface of the recess, and formed on the insulating film Along the side wall of the recess, the edge is on the side wall of the recess, the gate electrode is opposite to the insulating film, and the bottom is above the channel surface that is the bottom surface of the recess. A first source / drain region formed in the semiconductor layer, and formed outside the first source / drain region with respect to the gate electrode and in contact with the first source / drain region. A second source / drain region formed on the surface of the semiconductor layer, and a wiring contact connected to the second source / drain region,
A MIS type semiconductor device, wherein a region where at least one of the first source / drain regions and the gate electrode face each other with the insulating film interposed therebetween operates as a storage layer.   Of the insulating film formed between the first source / drain region and the gate electrode, a region other than the region where the gate electrode and the first source / drain region are opposed to each other is from the opposite region. The MIS type semiconductor device according to claim 1, wherein the MIS type semiconductor device is formed thick.   2. The MIS type semiconductor device according to claim 1, wherein the first source / drain region is formed of a material having the same conductivity type as a channel region formed between the source / drain regions. The bottom surface of the first source / drain region is inclined with respect to the surface of the semiconductor layer in a direction along the channel length direction, is low on the gate side, and is high on the second source / drain region side. The MIS type semiconductor device according to claim 1.   2. The MIS type semiconductor device according to claim 1, wherein the bottom surface of the first source / drain region is curved in both directions in the channel length direction. Selectively stacking and forming a first insulating film and a dummy gate on the first semiconductor layer;
Forming a second semiconductor layer having sidewalls gentler than a right angle by sandwiching the dummy gate by selectively solid-phase-growing a semiconductor material using the dummy gate as a mask;
Forming a second insulating film so as to cover the surfaces of the second semiconductor layer and the dummy gate;
After depositing a filler on the second insulating film, exposing the dummy gate by planarizing and removing the surface of the filler;
By removing the second insulating film formed on the side wall of the dummy gate together with the dummy gate and the first insulating film, a tapered portion having the same inclination as the side surface of the second semiconductor layer is formed between the bottom surface and the side wall. A step of forming a recess having,
Forming an insulating film on the bottom and side walls of the recess;
A step of embedding and forming a conductive material to be a gate electrode in the recess in which the insulating film is formed using a damascene process;
A method of manufacturing a MIS type semiconductor device, comprising:   The method of manufacturing a MIS type semiconductor device according to claim 6, wherein the solid phase growth is epitaxial growth.

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