JP2000082813A - Mis semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the parasitic resistance and capacity while suppressing the short channel effect. SOLUTION: A MIS semiconductor device is provided with a silicon substrate 61 having a recession with sidewall at least partly making milder angle than right angle, a gate electrode 68 holding a gate insulating film 67 formed on the upper layer of the recession bottom face, the first source and drain diffused layers 71a, 71b and the second source and drain diffused layers 72a, 72b formed holding the gate electrode 67 formed on the side of the gate insulating film 67 as well as wirings 70a, 70b. In such a constitution, the edge of the gate electrode 68 is positioned inside the recession, also the gate electrode 68 and the source diffused layer 71a as well as the gate electrode 68 and the drain diffused layer 71b have opposing regions, thereby making feasible of forming the source and drain in this opposing region filling the role of accumulation layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device and a method for manufacturing the same, and more particularly to a device used for a source region and a drain region.

[0002]

2. Description of the Related Art In order to meet the demand for higher performance due to higher integration based on recent miniaturization, when fabricating a semiconductor integrated circuit, the gate electrode of a transistor is processed in a region near the processing limit of lithography technology. You. For this reason, variations in channel length due to variations in gate electrodes give more and more variations in transistor characteristics, and lower product yield. On the other hand, with the miniaturization of semiconductor integrated circuits, fine transistors and wirings are extremely densely arranged, and wiring distances are long. Therefore, even if the transistor operation speed is increased based on miniaturization,
Due to the parasitic capacitance and the parasitic resistance between the transistor and the wiring, there has been a case where a high-speed circuit operation cannot be realized.

FIG. 26 shows the structure of a conventional planar transistor.
Shown in A gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. Wirings 4 a and 4 b are formed on the side of the gate electrode 3 via an insulating film 9. In the silicon substrate 1, a source diffusion layer 5a and a drain diffusion layer 5b are formed.
The region 6 between a and 5b becomes a channel region. Reference numeral 7 denotes an element isolation insulating film, and reference numeral 8 denotes an interlayer insulating film.

Since the diffusion layers 5a and 5b are distributed in the silicon substrate 1 adjacent to the channel region 6, the distribution weakens the control of the channel region 6 by the gate electrode 3 and causes a so-called short channel effect. The influence of lithography processing variations is increasing.

For comparison when explaining the problems of the recessed transistor and other conventional transistors described later, the current generated when this planar transistor is operated is shown by a dashed line in FIG. The current injected from the wiring 4a enters the source diffusion layer 5a, and its storage layer (the diffusion layer 5a opposed to the gate electrode 3 via the gate insulating film 2).
a, and has a carrier density of several tens of times or more the active impurity concentration of the diffusion layer), and enters the channel region 6.
Flows through the storage layer of the drain diffusion layer 5b and the diffusion layer region outside the drain diffusion layer 5b to the wiring 4b to form a current path.

In the diffusion layer region outside the storage layer, the high carrier concentration region on the surface of the substrate 1 is lost, and the current flows through the diffusion layers 5a and 5a depending on the carrier concentration determined by the active impurity concentration.
Spreads deep inside b, causing so-called spreading resistance,
As shown by the dashed line in FIG. 26, a substantially linear current path is formed.

Usually, the source region and the drain region are formed by introducing an impurity of the opposite conductivity type to the substrate by ion implantation using the gate electrode as a mask and activating or diffusing the impurity by a thermal process. The source region and the drain region connect the current path to the wiring to the channel. In order to make this connection with a sufficiently low resistance value, it is necessary to diffuse a high-concentration and sufficiently deep region.

FIG. 27 shows a drain diffusion layer 5b of the electron concentration distribution during the operation of a planar transistor having a gate length of 0.1 μm.
FIG. 27 is a diagram showing a relationship with the impurity of FIG. 26, which is obtained by device simulation for the vicinity of the gate electrode 3 in FIG. In the figure, only the drain diffusion layer 5b side is shown. In this simulation, 1 is applied to the gate electrode 3.
V, 1 V is applied to the drain diffusion layer 5b.

The bias applied to the source diffusion layer 5a is 0
V, so that the current is strongly dominated by the gate bias near the source diffusion layer 5a. In the vicinity of the drain diffusion layer 5b, the influence of the gate electrode 3 on the surface of the substrate 1 is weaker than that of the source diffusion layer 5a due to the bias applied to the drain diffusion layer 5b. However, since the gate insulating film 2 is extremely thin, the current is strongly controlled by the gate electrode 3 even near the drain diffusion layer 5b. The following mainly describes the drain diffusion layer 5b, but the relationship between the electron concentration or current concentration distribution and the position of the gate electrode 3 or the diffusion layer impurity distribution is basically the same for the source diffusion layer 5a.

The drain diffusion layer 5b is distributed below or inside the edge of the gate electrode 3 for connection with the channel, and forms a pn junction with channel impurities. This pn junction position is indicated by a thick line in FIG. At the junction position, impurities of the opposite conductivity type cancel each other out, and the net impurity concentration becomes zero.

That is, as shown by the broken line in FIG.
For example, 1 × 10 ²⁰cm^-3About high concentration
Even if impurities are introduced to a certain degree,
The impurity concentration is generally reduced by diffusion,
At the center side of the channel region 6 from the junction, as it approaches the junction
As a result, the impurity concentration is further reduced. Depletion layer around the junction
Formed, and the carrier concentration (electron concentration) becomes extremely low.
The source diffusion layer 5a or the drain diffusion layer 5b
It is electrically separated from the mold substrate 1. Therefore, FIG.
In 7, the log_Ten(Electron concentration) = electron concentration where 18
Degree distribution curve is log_Ten(Impurity concentration) = 18
Is it far from the joint surface compared to the material concentration distribution curve?
As can be seen from FIG.
Carrier concentration near the junction (electron concentration
Degree) is lower than the impurity concentration.

During operation of the transistor, an inversion layer is formed on the surface of the substrate 1 in the channel region 6 by the voltage applied to the gate electrode 3. The region having a high electron concentration on the surface of the channel region 6 in FIG. 27 is the inversion layer. On the other hand, substrate 1
An accumulation layer is formed on the drain diffusion layer 5b side near the junction near the surface, and is joined near the junction with the inversion layer formed on the channel region 6 side to form a current path.

In FIG. 27, the portion where the electron concentration of the drain diffusion layer 5b near the surface of the substrate 1 and near the junction surface is higher than the impurity concentration is this accumulation layer. In a region of the drain diffusion layer 5b having a high impurity concentration away from the edge of the gate electrode 3, the electron concentration matches the impurity concentration.

FIG. 28 shows the relationship between the current density distribution and the position of the gate electrode 3 or the impurity concentration distribution when the same bias is applied to the same MOS transistor as in FIG.
Inside the edge of the gate electrode 3, the channel region 6
Due to the inversion layer formed on the surface or the accumulation layer formed on the surface of the impurity region, a region having a high current density is distributed near the surface of the substrate 1. However, outside the edge of the gate electrode 3, the electric field by the gate electrode 3 suddenly weakens.
The region having a high current density biased on the surface of the substrate 1 is lost, and the current density is distributed at a low value to the far side of the substrate 1 along the region where the electron concentration of the drain diffusion layer 5b is high.

Therefore, in a region outside the edge of the gate electrode 3 where the influence of the gate bias is small, a sufficient storage layer can be induced by the gate bias to reduce the parasitic resistance. Therefore, it is necessary to sufficiently increase the carrier concentration determined by the above and to distribute the resistance to a depth of the substrate 1 in accordance with the concentration to lower the resistance.
That is, it is essential that the impurity concentration beneath the edge of the gate electrode 3 be sufficiently high and distributed deep in the substrate 1 in order to reduce the parasitic resistance in a region outside the edge.

The results shown in FIGS. 27 and 28 are for an example of a typical planar MIS transistor. Depending on the impurity distribution in the drain diffusion layer, the position of the edge of the gate electrode and the vicinity of the edge are shown. Depending on the shape of the gate electrode and the like, the electron concentration distribution and the current density distribution change.For example, the peak position in one or both of the drain diffusion layers may be located not on the substrate surface but deep in the substrate. Even in such a case, the situation is the same that the accumulation layer is formed on the surface of the diffusion layer region by the electric field of the gate electrode to lower the parasitic resistance of the diffusion layer region below the edge.

The impurity region inside the edge of the gate electrode 3 is indispensable to distribute the impurity concentration immediately below the edge of the gate electrode 3 high and sufficiently deep. However, due to recent miniaturization, the length of the gate electrode 3 has become extremely short, and the electric field given to the channel region 6 by the impurity distribution of the diffusion layer 5a or 5b weakens the dominance of the electric field given to the channel region 6 by the gate electrode 3. This causes a so-called short channel effect, which further deteriorates product yield.

In order to suppress the short channel effect, efforts have been made to reduce the junction depth of the diffusion layer 5a or 5b. However, as described above, in order to connect the channel region 6 and the high impurity concentration region of the drain diffusion layer 5b with a sufficiently small parasitic resistance, the impurity concentration below the edge of the gate electrode 3 must be increased and distributed sufficiently deep. And this is inconsistent with achieving the goal of suppressing short channel effects.

A structure proposed to solve this contradiction is a concave transistor. (For example, Nishimatsu et al., Groove Gate MOSFET, 8th Conf. On Solid State D
evice, pp. 179-183, 1976). FIG. 29A shows a sectional view of a conventional concave transistor structure. 26 are given the same reference numerals. In the conventional concave transistor, the source diffusion layer 45a and the drain diffusion layer 45b are made higher than the surface of the concave bottom channel region,
The influence of the impurity distribution of the diffusion layers 45a and 45b on the ability of the gate electrode 43 to electrically control the channel region is suppressed. In the concave transistor, the source and the drain can be made thicker (deeper) while keeping the distance from the concave bottom channel region, and the short channel effect is suppressed, and the parasitic resistance per unit length of the source and drain diffusion layers is reduced. Can be lowered.

However, the following problems occur in the ordinary concave transistor. FIG. 29B is an enlarged view of a main part of the concave transistor of FIG. An inversion layer 46 is formed on the bottom surface of the concave portion of the silicon substrate 1, an inversion layer 47 is formed on the side surface of the concave portion, and an accumulation layer 48 is formed on the side surface of the concave portion and in contact with the gate insulating film 42 in the diffusion layer 45a. You. The inversion layer 46 at the bottom of the recess corresponds to the inversion layer formed on the surface portion of the channel region 46 of the planar transistor in FIG.

As described above, in an ordinary concave transistor, in addition to the inversion layer 46 on the bottom surface of the concave portion, the side surface channel portion and the source diffusion layer 45a and the drain diffusion layer 45b connected to the side channel portion also form the gate insulating film 42 on the side surface of the concave portion. And has a portion parallel to the gate electrode 43 through the gate electrode 43. In the portion of the concave side surface parallel to the gate electrode 43, the concave side surface inversion layer 47 or the concave side surface accumulation layer 48 is formed in parallel with the side surface of the gate electrode 43, and serves as a current path, thereby generating a large parasitic capacitance.

On the other hand, comparing the current paths of the planar transistor shown in FIG. 26 and the concave transistor shown in FIG. 29, the current path of the planar transistor is linear, while the current path of the concave transistor is The angles formed by the current paths of the bottom surface of the concave portion and the side surfaces of the concave portion are close to acute angles, and the distance of the current path to the wirings 4a and 4b connected to the diffusion layers 45a and 45b is increased.

Further, usually, in order to suppress the parasitic capacitance between the gate electrode 43 or the wiring connected to the gate electrode 43 and the wirings 4a and 4b, or to suppress the leak current generated between them, And the diffusion layer 45a,
In many cases, a non-conductive film region, that is, a sidewall insulating film 49 is provided so as to increase the distance between the wirings 4a and 4b to the wiring 45b or to contact the gate side surface on the substrate 1.

In the case of a normal concave transistor in which the bottom surface of the side wall insulating film 49 is formed parallel to the bottom surface of the concave portion, the side wall insulating film 4 passes through the inversion layer 47 or the accumulation layer 48 on the side surface of the concave portion.
Since the current path is formed through a path near an acute angle between the plane having the step between the bottom surface of the base 9 and the bottom surface of the concave portion, the current path is longer than that of the above-described planar transistor,
This increases the parasitic resistance.

The carrier distribution peak around the channel is distributed in a very thin region of 0.01 μm or less along the surface of the channel. Therefore, when the current path near the acute angle, that is, the traveling path of the electrons is in a region near the bottom of the channel, extra work is required for carriers to follow the sharp distribution of the carrier distribution peak, and the current value decreases. .

On the other hand, as a conventionally known structure in the case of a p-type planar transistor, a transistor structure having a source region and a drain region having an oblique substrate surface has been known as an "Ultra-Shallow in-situ-doped raised source / drain
structure for sub-tenth micron CMOS ", Y.Nakahara e
t al., pp. 174-175,1996 Symposium on VLSI Technolog
y It is disclosed in Digest of Technical Papers. This structure is shown in FIG. In the case of the structure of FIG. 30, unlike the concave transistor shown in FIG. 29, the channel region and the source and the drain are formed in a plane. Further, the current is applied to the shallow diffusion layer 55 formed on the same plane as the channel region.
a and 55b and the wiring (not shown) to the source and drain via the deep and deep diffusion layers 55c and 55d.

That is, in the concave transistor shown in FIG. 29, the accumulation layer 48 connected to the inversion layer in the channel region is located at a position shallower than the depth of the channel bottom surface.
While the short channel effect is reduced by separating a and 45b from the channel bottom surface, the structure of FIG.
The storage layers formed in the source diffusion layer and the drain diffusion layer connected to the channel inversion layer are formed on the same plane as the channel region inversion layers at the ends of the shallow diffusion layers 55a and 55b adjacent to the channel region. Therefore, the shallow diffusion layers 55a and 55b in FIG. 30 are distributed inside the silicon substrate 1 adjacent to the channel inversion layer, and a short channel effect is generated depending on the thickness.

Therefore, in order to suppress the short channel effect,
Using silicon, a shallow source diffusion layer 55a and a shallow drain diffusion layer 55b are formed to be extremely shallow adjacent to the channel region. In order to compensate for the thickness of the diffusion layers 55a and 55b, an epitaxial source diffusion layer 55e and a drain diffusion layer 55f are formed on the silicon substrate 1. Here, the edge of the gate electrode 53 corresponds to the epitaxial diffusion layer 55e,
55f and shallow source diffusion layers 55a and drain diffusion layers 5
5b.

With such a structure, the influence of the electric field of the gate electrode 53 on the current path formed in the epitaxial diffusion layers 55e and 55f during the operation of the transistor is small. Therefore, although the current flows in a wide area in the epitaxial diffusion layers 55e and 55f and has spreading resistance, a current path is supplied in parallel to the diffusion layers 55a and 55b, respectively, thereby lowering the parasitic resistance of the entire source and drain.

That is, the effect of the epitaxial diffusion layers 55e and 55f in the structure shown in FIG. 30 is that the high resistance of the shallow diffusion layers 55a and 55b reaching the deep and deep diffusion layers 55c and 55d on the same plane as the channel bottom surface is reduced. It is to reduce by making up.

The epitaxial diffusion layers 55e, 55e,
By forming the surface of 55f obliquely, a thick oxide film sidewall 57 can be formed between the gate electrode 53 and the surface of the source diffusion layer / drain diffusion layer via the nitride film sidewall 56, thereby reducing parasitic capacitance. Has been reduced.

However, in the case of this transistor structure, since it is still a planar transistor, the short channel effect cannot be sufficiently suppressed only by controlling the thickness of the shallow diffusion layers 55a and 55b.

[0033]

As described above, when the conventional semiconductor device is used, it is difficult to suppress the short channel effect, reduce the parasitic capacitance and the parasitic resistance, and reduce the resistance of the current path. could not.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor device which reduces a parasitic resistance and a parasitic capacitance and suppresses a short channel effect, and a method of manufacturing the same. It is in.

[0035]

According to the present invention, there is provided an MIS type semiconductor device having a semiconductor layer having a concave portion having at least a portion having a side wall which is gentler than a right angle, and a gate insulating film interposed between the semiconductor layer and the bottom surface of the concave portion. Gate electrode, and a source region and a drain region formed on the side surface of the gate electrode with an insulating film interposed therebetween, and a boundary surface with the insulating film is formed in the semiconductor layer with an inclination with respect to the semiconductor layer surface, A wiring contact connected to the surface of the semiconductor layer, wherein the edge of the gate electrode is located inside a concave portion provided in the semiconductor layer, and at least the gate electrode and the source region or at least the gate electrode and the drain region. By having one of the opposed regions, it is determined that at least one of the source region and the drain region in the opposed region operates as a storage layer. And butterflies.

Here, the edge of the gate electrode means a position where the side wall of the gate electrode not in contact with the gate insulating film intersects the gate insulating film. Further, the gate insulating film refers to a region between the region where the gate electrode and the source region face each other and the region between the gate electrode and the drain region where the gate electrode faces each other.
An insulating film formed between a gate electrode and a source or drain region.

The fact that the edge of the gate electrode is located inside the concave portion also includes the case where the edge of the gate electrode is located at the boundary point between the concave portion and the region outside the concave portion. Further, the present invention includes a case where the junction position between the source region and the channel region or the junction position between the drain region and the channel region near the gate insulating film is located immediately below the edge of the gate electrode.

Preferably, in the insulating film formed between the source or drain region and the gate electrode, a region other than the region where the gate electrode and the source region or the region where the gate electrode and the drain region are opposed to each other. It is formed thicker than the region.

Further, another MIS type semiconductor device according to the present invention is formed so that at least a part thereof has a semiconductor layer having a concave portion having a side wall which is gentler than a right angle, and a gate insulating film interposed between the semiconductor layer and the bottom surface of the concave portion. A gate electrode, a source region and a drain region formed in the semiconductor layer with an insulating film interposed between the side surfaces of the gate electrode, and a boundary surface with the insulating film inclined with respect to the surface of the semiconductor layer; And a channel region formed under the bottom surface of the concave portion. The source region and the gate electrode have a first opposed region at a first junction position of the source region and the channel region near the gate insulating film. And at a second junction position between the drain region and the channel region near the gate insulating film, the drain region and the gate electrode have a second opposed region, and the first or the second The source region or the drain region of at least one of the regions operates as a storage layer, and the first or second insulating film formed between at least one of the source region or the drain region and the gate electrode. The insulating film in a region other than the two opposing regions is formed to be thicker than the first or second opposing region.

Preferred embodiments of the present invention will be described below.

(1) The height of the gate insulating film continuously increases from the vicinity of the center of the channel region to at least one of the source region and the drain region.

(2) The gate insulating film between the channel region and the gate electrode is formed in a straight line.

(3) On the surface of the source region and the drain region, a contact formed apart from the gate electrode is provided, and a gate insulating film is formed between the source region and the contact and between the drain region and the contact. And a current path is formed along the boundary surface, and the distance between the contact and the gate electrode is formed shorter than 1.5 times the gate width.

(4) In (3), at least one of the surfaces of the source region and the drain region in a region closer to the contact than the first and second opposing regions is formed to be inclined with respect to the semiconductor layer surface. Be done.

(5) At least one of the lower surfaces of the source region and the drain region in the vicinity of the first or second opposed region is formed higher than the height of the channel region. (6) In (3) , The source region and the drain region are formed of a material having the same conductivity type as a channel region formed between the source region and the drain region.

(7) The gate insulating film between the channel region and the gate electrode is formed in a linear shape, and is provided between both ends of the linear gate insulating film and the side wall which is gentler than a right angle. It has a corner portion, and at least one of the first and second joining positions is located between the corner portions.

(8) The impurity concentration of the source region or the drain region at one end located under the edge of at least one of the first and second opposing regions is 1 × 10 ^13.
cm ^-2 or more.

(9) The source region and the drain region are formed at positions shallower than the interface between the channel region and the gate insulating film.

Here, the junction position between the source or drain region and the channel region refers to the boundary position of the junction formed by the source or drain region and the channel region.

In the method of manufacturing a MIS type semiconductor device according to the present invention, a step of forming a concave portion having a gentler side wall than a right angle in a semiconductor layer by an RIE method, and a step of forming a gate insulating film so as to cover the surface of the semiconductor layer Forming a conductive film on the gate insulating film including the concave portion, and forming a gate electrode by patterning the conductive film using lithography so that the side wall is positioned on the side surface of the concave portion. And a process.

Preferred embodiments of the present invention will be described below.

(1) The side surface of the recess has an angle of about 45 degrees with respect to the surface of the semiconductor layer.

(2) forming a source region and a drain region in the semiconductor layer with the gate electrode interposed therebetween, and forming an interlayer insulating film on the semiconductor layer so as to cover the gate electrode, the source region and the drain region; Forming a contact hole for connecting a wiring to at least one surface of the source region or the drain region by selectively removing the interlayer insulating film using reactive ion etching, and forming a contact hole. By using an insulating film that protects the side wall and surface of the gate electrode as a mask,
The gate electrode is formed in a self-aligned manner.

In another method of manufacturing a MIS semiconductor device according to the present invention, a step of selectively laminating a first insulating film and a dummy gate on a first semiconductor layer, and using the dummy gate as a mask By selectively growing the semiconductor material in a solid phase, the second
Forming a semiconductor layer with the dummy gate interposed therebetween;
Removing the first insulating film and the dummy gate;
Selectively forming a gate insulating film and a gate electrode sequentially in a region where the insulating film and the dummy gate have been formed.

Preferred embodiments of the present invention will be described below.

(1) After the formation of the second semiconductor layer, a step of forming a second insulating film so as to cover the surfaces of the second semiconductor layer and the dummy gate, and a step of forming a filler on the second insulating film. A step of exposing the dummy gate by flattening and removing the surface of the filler, and removing the first and second insulating films formed on the side walls of the dummy gate together with the dummy gate to form a bottom surface Forming a concave portion having a tapered portion having the same inclination as the side surface of the second semiconductor layer between the side walls, and forming a gate insulating film on the bottom surface of the formed concave portion;
Embedding and forming a conductive material in a recess in which the gate insulating film is formed by using a damascene process.

(2) The angle of at least one side wall of the second semiconductor layer is approximately 50 degrees with respect to the surface of the first semiconductor layer.
It has an angle of degrees or 30 degrees.

(3) Solid phase growth is epitaxial growth.

(4) A step of forming a source region and a drain region on the surface of the second semiconductor layer, and a step of forming an insulating film for protecting the gate electrode on the side wall and the surface of the gate electrode after forming the gate electrode And the first so as to cover the insulating film.
A step of forming an interlayer insulating film on the semiconductor layer, and using the insulating film as a mask, by selectively removing the interlayer insulating film by reactive ion etching, to at least one surface of the source region or the drain region, A contact hole connected to the wiring is formed in the gate electrode in a self-aligned manner.

(5) After the formation of the semiconductor layer, impurities are diffused only to a desired thickness on the surface of the semiconductor layer.

(6) After forming the gate insulating film and the gate electrode, ions are implanted using the gate electrode as a mask to diffuse impurities, and a source region and a drain region are formed in the semiconductor layer on the side surfaces of the gate electrode. .

(Operation) In the MIS type semiconductor device of the present invention, the edge of the gate electrode is located on the side wall of the concave portion including the inclined region of the source region and the drain region, and the gate electrode and the source region or the gate electrode and the drain region Has a region facing each other via the gate insulating film. An accumulation layer is formed on the surfaces of the source region and the drain region in the opposing regions during operation. One end (hereinafter, referred to as a first end) of the accumulation layer is a portion where the source region or the drain region forms a junction with the channel region, and has a low net impurity concentration. Therefore, although the carrier density determined by the impurity concentration is low, carriers having a concentration of several tens of times or more the carrier density in a case where the carrier region is not formed are accumulated in the accumulation layer, and the source region and the drain region are formed in the channel region. The resistance in a region close to a region where a junction is formed with the region is reduced.

The other end of the accumulation layer (hereinafter, referred to as a second end) is located away from the junction of the source region or the drain region with the channel region and has a sufficiently high impurity concentration. Can be located. Further, since the second end is located shallower than the channel surface, even if impurities are distributed from this position to a deeper position and the resistance outside the gate edge is reduced, the short channel effect does not occur.

Further, since this accumulation layer is formed along the inclined side wall, the current path from the channel surface to the wiring is made close to a straight line to shorten the distance. In this manner, the channel surface and the wiring are connected by a low-resistance and short current path, so that the parasitic resistance can be reduced.

Further, the source region and the drain region on the side surface of the gate electrode are formed to be inclined with respect to the surface of the semiconductor layer. Accordingly, the distance between the gate electrode and the source region or the distance between the gate electrode and the drain region is widened, and the parasitic capacitance can be reduced.

Also, unlike the planar transistor, the gate electrode and the source region or the region where the gate electrode and the drain region face the gate electrode are formed at a position shallower than the interface between the channel region and the gate insulating film. Therefore, there is no need to form a diffusion layer near the channel region,
The short channel effect can be suppressed.

Even when the source region and the drain region have a region protruding below the interface between the channel region and the gate insulating film, by controlling the protruding region to a thickness enough to operate as an inversion layer. The same effect as described above is achieved.

In the method of manufacturing a semiconductor device according to the present invention, the semiconductor layer is provided with a recess in the side wall which is gentler than a right angle.
The conductive film is formed on the semiconductor layer including the concave portion by the method E, and the conductive film is patterned by lithography so that the side wall is located on the side surface of the concave portion. This makes it possible to realize a MIS semiconductor device in which the short channel effect is suppressed and the parasitic capacitance and the parasitic resistance are reduced.

Further, a source region and a drain region are formed by solid phase growth of the MIS type semiconductor device using a dummy gate as a mask, and a gate electrode is formed in a concave portion from which the dummy gate has been removed. , The gate electrode can be formed in a self-aligned manner, and no displacement occurs.

Further, by removing the insulating film previously formed on the side wall of the dummy gate together with the removal of the dummy gate, a concave portion having a tapered portion between the bottom surface and the side wall having the same inclination as the side surface of the second semiconductor layer is formed. Can be formed, so that a region where the gate electrode and the second semiconductor layer operating as a source region or a drain region face each other can be formed.

Further, by forming the gate electrode by the damascene process, it is possible to selectively perform ion implantation into the first semiconductor layer on the bottom surface of the concave portion that operates as a channel region.

[0072]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 4 are views for explaining a semiconductor device (recessed MIS transistor) according to a first embodiment of the present invention. FIGS. FIG. 2 illustrates a configuration of such a semiconductor device.
And FIG. 3 is a process sectional view showing a method for manufacturing the semiconductor device. FIG. 1A is a view of the present semiconductor device as viewed from above.
FIG. 1A is a sectional view taken along the line 6A-6A 'in FIG.
FIG. 1B is a cross-sectional view of 6B-6B ′, and FIG.
FIG. 1D is a cross-sectional view taken along the line 6C ′. In the following embodiments, an n-channel MIS transistor will be described. In the case of a p-channel MIS transistor, the conductivity type of each component may be reversed.

In FIG. 1B, reference numeral 61 denotes a p-type silicon substrate using a (100) plane, which has an impurity concentration of 5.times.
It is about 10 ¹⁵ cm ^-3 . As shown in FIG. 1A, an active region 62 and an active region 6 are formed on the silicon substrate 61.
The element isolation region 63 is formed so as to surround the element 2, and an element isolation insulating film 64 is formed in the element isolation region 63.

The active region 62 is a portion surrounded by a broken line in FIG. 1A. In order to adjust a threshold voltage (V _th ), a channel ion (not shown) having an impurity concentration of about 5 × 10 ¹⁷ cm ^{−3 is used.} An injection layer is formed. This active area 6
A gate electrode 68 is formed on the silicon substrate 61 in the gate electrode 2 via a gate insulating film 67, and wirings 70 a and 70 b are provided on both sides of the gate electrode 68 via an interlayer insulating film 69. These wirings 70a and 70b are connected to the source region and the drain region. The source region includes a first source diffusion layer 71a and a second source diffusion layer 72a, and the drain region includes a first drain diffusion layer 71b and a second drain diffusion layer 72b. Gate insulating film 67
Is, for example, a thermal oxide film having a thickness of about 3.0 nm.

In FIG. 1B, the channel surface 6
5 is located deeper than the substrate surface 66. Silicon substrate 6
1, a concave portion having the channel surface 65 as a bottom surface is formed, and the side wall of the concave portion forms an inclined surface having a gentler angle than a right angle to the channel surface 65, and the entire concave portion is covered with the gate insulating film 67. Here, the channel surface 65 refers to an interface between the channel region and the gate insulating film 67. The channel region is formed on the bottom of the concave portion below the channel surface 65.

Further, a gate electrode 68 is buried in the concave portion of silicon substrate 61 with a gate insulating film 67 interposed therebetween, facing the channel region. Thus, a concave transistor structure having a channel region embedded in the substrate 61 is formed.

The first plane having a step between the channel surface 65 and the substrate surface 66 is formed along the inclined side wall of the gate insulating film 67 and has an inclination with respect to the surface of the silicon substrate 61.
Source diffusion layer 71a and first drain diffusion layer 71b
(Indicated by oblique lines), they are connected by an n-type second source diffusion layer 72a and a second drain diffusion layer 72b connected thereto (hereinafter, the source and drain are simply referred to as 71a, 71b, 72a, 72b together). Call).

The first source diffusion layer 71a and the drain diffusion layer 71b are formed toward the channel surface 65, and
The source diffusion layer 72a and the drain diffusion layer 72b are thick diffusion layers formed in parallel with the channel surface 65.

Here, the diffusion depth and impurity concentration of the second source diffusion layer 72a and the second drain diffusion layer 72b are
Each is about 0.05 μm and about 5 × 10 ²⁰ cm ⁻³ .

A contact hole 73 is formed in the interlayer insulating film 69.
a to 73c are opened.
The wirings 70a to 70c are n-type second via the 3a to 73c.
Source diffusion layer 72a and second drain diffusion layer 72b
And the gate electrode 68. The interlayer insulating film 69 is made of, for example, a SiO ₂ film,
70c are formed of, for example, an Al film. This wiring 7
0a to 70c are the wirings 70a and 70b and the gate electrode 68
Is shorter than 1.5 times the gate width. Further, the first source diffusion layer 71a and the first drain diffusion layer 71b inclined with respect to the surface of the silicon substrate 61 have a region opposed to the gate electrode 68 at the tip, and include a wiring including this region. It is formed so as to be inclined with respect to the surface of the silicon substrate 61 up to the vicinity of 70a and 70b (with deletion). Note that, in FIG.
The gate electrode formation region indicated by a cross “4” is a region where the first source diffusion layer 71a and the drain diffusion layer 71b having an inclination overlap with the gate electrode 68, and the region indicated by hatching 75 is the first source diffusion layer. 7 shows a region where a drain diffusion layer 71b is formed.

Next, a method of manufacturing the concave MIS transistor according to the present embodiment will be described with reference to FIGS.
2A is a top view, and FIG. 2B is a view 7A of FIG. 2A.
FIG. 2 (c) is a cross-sectional view of FIG.
FIG. 2D is a sectional view taken along the line B ′, and FIG. 2D is a sectional view taken along the line 7C-7C ′ in FIG.
3 (a) is a top view, FIG. 3 (b) is a sectional view taken along the line 8A-8A 'of FIG. 3 (a), and FIG. 3 (c) is a sectional view of FIG.
FIG. 3A is a sectional view taken along the line 8B-8B ′, and FIG.
(A) is an 8C-8C ′ cross-sectional view.

First, an active region 62 is formed on a silicon substrate 61.
Inside, a SiO ₂ film 91 having a thickness of 0.02 μm is formed.
Next, for example, using a desired photoresist pattern (not shown) as a mask, the SiO ₂ film 91 formed in the region where the first source diffusion layer 71a and the first drain diffusion layer 71b having the channel and the inclination are to be formed; By etching the silicon substrate 61 by RIE (Reactive Ion Etching), the bottom surface is set at 0.
A recess 92 having a depth of about 1 μm is formed. At this time,
By selecting the RIE condition, as shown in FIG. 2B, the side surface of the concave portion is formed obliquely at an angle of 45 degrees with respect to the bottom surface of the concave portion.

Next, a not-shown port generated at the time of etching is used.
Limmer layer and SiO_TwoAfter removing the film 91, the silicon substrate 6
The surface of the active region 62 is exposed, for example, at 950 ° C.
By performing a heat treatment for about 2 minutes in a hydrogen atmosphere, the RI
The damage recovery processing in the concave portion 92 caused by E is performed.
U. Next, a thickness of 5 nm is formed on the exposed surface of the silicon substrate 61.
Not shown sacrificial SiO_Two The membrane can be
Formed. Then, an element isolation insulating film 64 or the like or illustrated
Include recesses 92 using photoresist not to be mask
A threshold voltage control is applied to the lower silicon substrate 61 of the active region 62.
Channel ion implantation for control and the like is performed. n-type transistor
In the case of a transistor, for example, a threshold voltage (V_th)
Is set, for example, at an acceleration voltage of 5 keV and a dose of 2
× 10¹²cm ^-2Boron (B⁺) Ion implantation
To form a p-type channel ion implanted layer in the channel region
(Not shown).

Next, after the sacrificial SiO ₂ film (not shown) is peeled off, as shown in FIG.
A gate insulating film 67 is formed on the surface of the silicon substrate 61 including the bottom surface of FIG. Here, a film obtained by thermally nitriding the surface of an oxide film may be used for the gate insulating film 67.
Also, a CVD-SiO ₂ film, a CVD-SiON film, a CV
A stacked film including a D-Si ₃ N ₄ film may be used for the gate insulating film 67.

Next, so that the inside of the concave portion 92 is filled,
A conductive layer serving as a gate electrode 68 is formed on the gate insulating film 67, and the surface of the conductive layer is polished and smoothed by a CMP method (Chemical Mechanical Polishing). As the conductive layer to be the gate electrode 68, for example, a polysilicon layer doped with an n-type impurity is used.

Next, as shown in FIG. 3B, by using lithography technology, both ends of the conductive layer are included in the recess 92, and the ends of the conductive layer on the source and drain sides are formed. The gate electrode 68 is formed by patterning so as to be located outside the bottom of the channel. Next, ion implantation 93 is performed on the silicon substrate 61 using the gate electrode 68, the element isolation insulating film 64, the photoresist, and the like as a mask.
Is performed, and the first source diffusion layer 71a, the first drain diffusion layer 71b, the second source diffusion layer 72a, and the second
Is formed. The conditions for ion implantation are, for example, about 30 KeV for an acceleration voltage and about 5 × 10 ¹⁵ cm ⁻² for an arsenic (As) ion implantation.

The reason why the surface of the conductive layer is smoothed by the CMP method at the time of patterning the conductive layer is that the distortion of the gate pattern position of the lithography technique is suppressed by the smoothing, and the first source diffusion layer 71a and the first This is because the edge of the gate electrode 68 is accurately included in the recess 92 in order to easily form the drain diffusion layer 71b. That is, using the gate electrode 68 as a mask, the first source diffusion layer 71a and the first drain diffusion layer 71a
b and ion implantation 93 for forming the second source diffusion layer 72a and the second drain diffusion layer 72b.
This is because the formation region of the second source diffusion layer 72a and the second drain diffusion layer 72b varies depending on the formation position of the gate electrode 68 serving as a mask. The gate electrode 68
Edge means a position where the side wall of the gate electrode 68 not in contact with the gate insulating film 67 intersects the gate insulating film 67.

The first source diffusion layer 71a and the first drain diffusion layer 71b need to be formed so that no accumulation layer is formed on the channel surface 65 in order to suppress the short channel effect. Therefore, by forming the gate electrode 68 such that the edge is located on the tapered side wall of the concave portion 92, the regions 71a and 71b extend from the tapered side wall to near both ends of the channel surface 65, and are the same as the channel region. A structure in which the regions 71a and 71b do not spread to a plane can be obtained.

As shown in FIG. 3B, the edge of the gate electrode 68 is formed outside the bottom of the concave portion 92 so as to include only a part of the inclined side surface.
The bonding surface with the gate insulating film 67 near the edge of the gate electrode 68 can be formed obliquely in accordance with the inclination of the gate insulating film 67.

After the ion implantation 93 for source and drain formation, RTA (Rapi (Rapi)
d Thermal Anneal) to activate the impurities by heat treatment at 900 ° C. for about 10 seconds. Here, the source and the drain may be formed by solid phase diffusion using the gate electrode 68 or the like as a mask after forming the gate electrode 68 without using the ion implantation 93.

Next, as shown in FIG. 1B, after an interlayer insulating film 69 made of SiO ₂ is formed on the entire surface, a part of the second source diffusion layer 72a and the second drain diffusion layer 72b and the gate are formed. Contact holes 73a to 73c are formed in interlayer insulating film 69 so that a part of electrode 68 is exposed. Next, a metal such as an Al film or an Al-Cu film is formed on the entire surface so as to fill the contact holes 73a to 73c,
This metal is patterned to form wiring 7 according to the circuit design.
0a to 70c (only some are shown) are sequentially formed. next,
A passivation film (not shown) is deposited on the entire surface to complete the transistor part manufacturing process.

FIG. 4 is an enlarged sectional view showing the vicinity of the first drain diffusion layer 71b having the inclination of the concave MIS transistor formed by the above-described steps, together with the current path. According to the MIS transistor having the concave channel structure configured as described above, there is a step having a step between the channel surface 65 and the substrate surface 66 via the inversion layer and the storage layer formed along the side surface having the inclination of the concave portion. The current path connecting the two planes forms an obtuse angle with the traveling direction of the current path passing from the channel surface 65 to the vicinity of the substrate surface 66.

The first source diffusion layer 71 having an inclination
The surface of the region where a and the first drain diffusion layer 71b face the gate electrode 68 operates as a storage layer. One end of the accumulation layer is a portion where the source or the drain forms a junction with the channel region, and has a low net impurity concentration. Therefore, although the carrier density determined by the impurity concentration is low, carriers having a concentration of several tens of times or more the carrier density in the case where the carrier is not formed are accumulated in this accumulation layer, so that the first source diffusion layer 71a or The carrier density near the junction of the first drain diffusion layer 71b is supplemented, and the resistance generated in the first source diffusion layer 71a and the first drain diffusion layer 71b is eliminated. This accumulation layer is formed along the side walls of the first source diffusion layer 71a and the first drain diffusion layer 71b having an inclination. Therefore, as shown by the dashed line in FIG. 4, the current path from the channel surface 65 to the contact on the surface of the silicon substrate 61 can be shortened by making the current path close to a straight line, thereby reducing the parasitic resistance.

One end of the storage layer, that is, the end of the storage layer passing through the gate edge and intersecting the normal to the surface of the gate insulating film 67 in contact with the edge is located shallower than the channel bottom and has a sufficiently high impurity. It can be located at a point with density. Therefore, without causing the short channel effect,
The impurity distribution depth a at this position is made deeper, and at the same time, the impurity distribution depth of the region outside the gate edge is made deeper, so that the resistance of this region can be reduced. Here, the impurity depth is the first
Source diffusion layer 71a or first drain diffusion layer 71b
Is the depth of impurity distribution in the normal direction to the surface. In order to lower the resistance, it is desirable that the impurity concentration integrated in the direction of the impurity distribution depth a is 1 × 10 ¹³ cm ⁻² or more. Further, since the end portion of the accumulation layer is located shallower than the channel bottom surface, even if the impurity is distributed deep from this position and the resistance of the region outside the gate edge is lowered, the short channel effect does not occur. .

In addition, since the distance between the first source diffusion layer 71a and the gate electrode 68 and the distance between the first drain diffusion layer 71b and the gate electrode 68 can be increased in regions other than the region serving as the storage layer, the parasitic capacitance can be reduced. Further, since the first source diffusion layer 71a and the first drain diffusion layer 71b have a concave transistor structure formed at a position shallower than the channel surface 65, the source and the drain are formed on the same plane as the channel. The resulting short channel effect can be suppressed. In addition, in this concave transistor structure, the lower surfaces of the source and the drain are located higher than the channel especially in the vicinity of the region where the first source diffusion layer 71a and the first drain diffusion layer 71b are opposed to the gate electrode 68. The short channel effect can be suppressed.

If the lower end of the gate electrode 68 adjacent to the source and the drain is formed linearly with a slope as shown in FIG. 4 or rounded, the inversion generated near the source and the drain at both ends of the gate due to the electric field of the gate. The carrier concentration of the layer or the storage layer can be increased, and the resistance in the channel region near both ends of the gate and the ends of the source and drain can be reduced. In addition, the current distribution from the channel surface 65 to the source and the drain is formed at an obtuse angle by the carrier distribution, so that work lost when electrons travel on an acute path can be reduced, and the decrease in the current value can be reduced. Can be.

The first source diffusion layer 71 having an inclination
If the depth of the junction between the second source diffusion layer 72a and the second drain diffusion layer 72b is increased while the depth of the junction between the second source diffusion layer 72a and the second drain diffusion Further, the resistance of the drain can be further reduced.

The regions where the first source diffusion layer 71a and the gate electrode 68 and the first drain diffusion layer 71b and the gate electrode 68 face each other are not necessarily the silicon substrate 61.
Does not need to be formed with a gentler inclination than at right angles. For example, near the bottom of the gate electrode 68, the gate insulating film 67 and the gate insulating film 67 are formed substantially perpendicular to the surface of the silicon substrate 61, and the distance from the bottom of the gate electrode 68 to the gate electrode 68 gradually increases from a predetermined distance. As described above, even in the structure where the surfaces of the first source diffusion layer 71a and the first drain diffusion layer 71b are formed,
The same effects as those of the present invention can be obtained.

Although the present embodiment has shown the case where the edge of the gate electrode 68 is located inside the concave portion 92, the gate electrode 68 is located at the boundary between the concave portion 92 and the region outside the concave portion 92.
May be located. Further, the junction between the source and the channel region or the junction between the drain and the channel region near the gate insulating film 67 may be located immediately below the edge of the gate electrode 68. The same applies to the following embodiments.

(Second Embodiment) FIG. 5 is a process sectional view showing an embodiment for realizing the transistor structure of the present invention having a channel region having a curvature. Here, the distance between the gate electrode and the contact on the mask is zero, and the contact is formed on the inclined source or drain in a self-aligned manner with the gate electrode.

Hereinafter, a method for manufacturing the concave MIS transistor according to this embodiment will be described.

First, a 0.02 μm thick SiO ₂ film 91 is formed on the silicon substrate 61 in the active region. Next, an Si ₃ N ₄ film 101 is deposited to a thickness of 0.5 μm, and an opening of the Si ₃ N ₄ film 101 is formed using, for example, a desired photoresist pattern (not shown) as a mask. Next, FIG.
As shown in FIG. 3A, a recess 102 is formed by etching the silicon substrate 61 by RIE using the Si ₃ N ₄ film 101 as a mask. With the configuration of the concave portion 102 as shown in FIG. 11, the source region and the drain region connected to the contact can be formed higher than the channel region.

Next, the SiO 2 is filled so as to fill the recess 102.
₂ film 103 is deposited and planarized by CMP using the Si ₃ N ₄ film 101 as a stopper. Then, lithography using a photoresist is used to form a gate electrode by RIE using the resist pattern as a mask.
_{The second} film 103 is opened by etching. Further, FIG.
As shown in (b), the silicon substrate 61 at the bottom of the opening is etched to form a recess 104 in the channel region. At this time, by adjusting the etching conditions, the concave portion 1 is formed.
04 is formed to have a substantially uniform curvature. Next, the polymer layer (not shown) generated at the time of etching is removed to expose the surface of the silicon substrate 61, and a heat treatment is performed in, for example, a hydrogen atmosphere at 800 ° C. for about 2 minutes to perform RIE.
A damage recovery process in the concave portion 104 caused by this is performed. At this time, for example, by performing a heat treatment in a hydrogen atmosphere at 950 ° C. and 10 Torr for about 1 minute, silicon atoms on the surface of the concave portion 104 can be moved by the balance of surface energy, and the curvature of the concave portion can be made more uniform.
Next, if necessary, a sacrificial SiO ₂ film (not shown) having a thickness of about 5 nm is formed on the exposed surface of the silicon substrate 61 by, for example, a thermal oxidation method, and channel ion implantation for controlling a threshold voltage or the like is performed.

Next, the sacrificial SiO ₂ film is peeled off, and as the gate insulating film 105, for example, a SiO ₂ film having a thickness of about 3 nm is used.
_Two films are formed by a thermal oxidation method.

Next, the concave portion 1 surrounded by the SiO ₂ film 103
A conductive film is deposited so as to fill the inside of the substrate. As the conductive film, for example, polysilicon doped with phosphorus at a high concentration is used. Next, CMP is performed using the Si ₃ N ₄ film 101 as a stopper.
And the gate electrode 6 is flattened as shown in FIG.
8 is formed. Next, by hot phosphoric acid treatment, Si ₃ N ₄
The film 101 is removed, and then the SiO ₂ film 103 is removed by hydrofluoric acid treatment to expose the surface of the silicon substrate 61 which is the surface of the source and drain regions adjacent to the gate electrode 68. Next, using the gate electrode 68 as a mask, a first source diffusion layer 106a and a first drain diffusion layer 106b are formed in a self-aligned manner at the gate end by ion implantation.
Next, annealing for activating the impurities in the first source diffusion layer 106a and the first drain diffusion layer 106b is performed.

Next, as shown in FIG. 5D, after depositing a Si ₃ N ₄ film of, for example, about 0.04 μm on the surface, the RI
By E, the Si ₃ N ₄ film is partially removed by a so-called side wall leaving process, and a side wall nitride film 107 is formed on the side surface of the gate electrode 68. The thickness of the sidewall nitride film 107 is formed such that one end of the sidewall not in contact with the gate electrode 68 is included in the recess 102.

Next, using the sidewall nitride film 107 as a mask, a second source diffusion layer 108a and a second drain diffusion layer 108b are formed by ion implantation. Thereby, the resistance of the source and the drain can be reduced. First source diffusion layer 106a and first drain diffusion layer 106b
If the resistance of the second source diffusion layer 1 is sufficiently low,
08a or the second drain diffusion layer 108b may not be formed.

Next, an interlayer insulating film 6 of SiO ₂ is formed on the entire surface.
9 is deposited, and is planarized by CMP using the gate electrode 68 as a stopper. Next, the gate electrode 68 is formed by CDE.
Then, a Si ₃ N ₄ film is deposited so as to fill the trench above the recessed gate electrode 68 and planarized by CMP to form a protective nitride film 109. Next, contact holes to the first source diffusion layer 107a and the first drain diffusion layer 107b are formed by RIE.
To open. Sidewall nitride film 107 and protective nitride film 10
9, the gate electrode 68 on the mask is formed.
It is possible to perform RIE with the distance to zero as zero.

Next, a conductive material, for example, polysilicon is filled into the opened contact holes to form wirings 110a and 110b. To reduce contact resistance,
Ti or the like may be deposited on the surface of the silicon substrate 61 on the bottom surfaces of the wirings 110a and 110b, and may be silicided.

When the contact resistance of the source and the drain is reduced by silicidation, the surface of the silicon substrate 61 is silicided, so that the bottom surface of the silicided portion is close to the junction of the diffusion layer, and the leakage current increases. There is. Therefore, it is necessary to form a sufficiently deep diffusion layer in order to perform silicidation, and it is generally difficult to satisfy this need if a shallow junction is formed to reduce the short channel effect. In the present invention, since the source and the drain are positioned higher than the channel region with an inclination, the diffusion layer of the source or the drain can be deepened, and the contact resistance can be easily reduced by silicidation.

As described above, according to the present embodiment, by forming the concave portion defining the interface between the channel region and the gate insulating film in a curved line, the current path becomes linear when viewed locally. Formed. Therefore, the current path can be formed short, and the withstand voltage of the gate insulating film 105 can be improved and the mobility of electrons can be prevented from being deteriorated, as compared with a structure having a current path having corners.

In addition, since the source and drain accumulation layers connected to the channel region are positioned with an inclination above the channel region, the short channel effect is suppressed.

Next, the advantage obtained by forming the radius of curvature of the channel region formed inside the concave portion to be uniform will be described.

When a portion having a smaller radius of curvature in the channel than the peripheral portion is present in the channel, the electric field by the gate electrode diverges in this portion than in the peripheral portion having a large radius of curvature, and carriers induced in the inversion layer are reduced. Decreases and the resistance increases. With a uniform radius of curvature throughout the channel, this carrier loss occurs throughout the channel,
By lowering the substrate concentration throughout the channel, the carrier can be increased overall. That is, a concave transistor having a uniform radius of curvature can have a lower resistance and a lower substrate concentration than a concave transistor having a small radius of curvature or having a corner portion. A low substrate concentration has the advantage that the junction leakage current with the drain diffusion layer can be suppressed.

Further, in the present embodiment, by making the distance between the gate and the contact on the mask zero, and forming the contact in a self-aligned manner, it is possible to greatly reduce the area for forming the transistor. Becomes

(Third Embodiment) FIG. 6 is a sectional view showing an overall configuration of a semiconductor device according to a third embodiment of the present invention.
The semiconductor device according to the present embodiment is a modification of the first embodiment, and the ion implantation 9 of the first embodiment shown in FIG.
By adjusting the condition of the third or subsequent activation annealing, impurity regions 94a and 94b are added to the first source diffusion layer 71a and the first drain diffusion layer 71b.

As shown in FIG. 6, the first source diffusion layer 7
The lower ends of the drain diffusion layer 1a and the first drain diffusion layer 71b are formed so as to cover the corners at the ends of the channel surface 65, and impurity regions 94a and 94b that cover the corners are formed.
In this structure, the carrier density in the corner portion at the end of the channel surface 65 also increases after the accumulation layer formed at the portion corresponding to the gate end of the first source diffusion layer 71a and the first drain diffusion layer 71b. In addition, the value of the current flowing during the operation of the transistor can be further increased.

Impurity region 94a for channel surface 65
And 94b have a junction depth of about the thickness of the inversion layer, for example, 0.1 mm.
It may be formed to a thickness of 01 μm or less. The inclined impurity regions 94a and 94b are provided on the surface of the portion facing the gate electrode 68 via the gate insulating film 67 during operation.
Sufficient carriers are induced by the electric field 8 to form a storage layer, and a current path with low resistance is formed. For this reason, for example, in the case of the conventional planar transistor shown in FIG.
Unlike the case where a junction depth of about m is assumed, the junction depth of the impurity regions 94a and 94b with respect to the channel surface 65 can be formed shallow, so that the current value can be increased while suppressing the short channel effect. .

As described above, a very shallow, inversion layer thickness is formed to cover the corner portions formed at both ends of the channel region and connected to the inclined first source diffusion layer 71a and first drain diffusion layer 71b. By further forming the n-type impurity regions 94a and 94b, the same effect as in the first embodiment can be obtained, and the carrier density in the corner portion can be increased as compared with the case of the first embodiment. Even higher current values can be obtained.

(Fourth Embodiment) FIGS. 7 to 12 are views showing a process of manufacturing a semiconductor device (concave MIS transistor) according to a fourth embodiment of the present invention. In the present embodiment, FIG.
The present invention relates to a manufacturing method for realizing a structure having the features of the concave transistor structure of the first embodiment shown in FIG.
This embodiment is different from the first embodiment in that the active region 62
Among them, on the silicon substrate 61 not covered with the bottom surface of the gate electrode 68, a single-crystal silicon selectively epitaxially grown with a tapered surface inclined with respect to the side surface of the gate electrode 68 is formed. An epitaxial region is provided, and a portion having an inclined surface of the epitaxial region is used as a source and a drain having an inclination.

Hereinafter, a method of manufacturing the concave MIS transistor according to the present embodiment will be described with reference to FIGS. FIG.
12A to 12A are views of the semiconductor device as viewed from above, and 12A-12A ′ to 17A-17 in FIG.
The cross section taken along the line A 'is shown in FIG.
FIG. 7C is a cross-sectional view of 7B ′, showing 12C-12C ′ to 17C-
17D 'cross-sectional views are shown in FIG.

As shown in FIG. 7B, an SiO ₂ film 131 is formed on the entire surface of the active region 62 by, for example, a thermal oxidation method, and then the gate electrode 6 is formed by lithography.
The dummy gate 13 made of a SiN ₄ film is formed in a region where
Form 2 Next, the oxide film in a region of the active region 62 not covered by the dummy gate 132 is removed by, for example, diluted hydrofluoric acid. In FIG. 7B, reference numeral 131 denotes an SiO ₂ film remaining after being located below the dummy gate 132.

Next, on the active region 62, the dummy gate 1
A crystalline silicon layer is selectively epitaxially grown using the silicon substrate 61 as a nucleus using the mask 32 as a mask. When solid phase growth is performed on a surface on which a substance that blocks distribution of a silicon crystal serving as a nucleus, such as the dummy gate 132, is not continuously grown directly on the edge of the silicon region but grows. A surface with so-called facets appears. In the case of the present embodiment, (1)
By utilizing the fact that the surface energy is the smallest and the growth rate is the slowest on the (11) plane, the silicon substrate 61 on the (111) plane is utilized.
Use facets that make an angle of about 50 degrees with the surface.

More specifically, first, in the LPCVD apparatus, the surface of the silicon substrate 61 in the exposed active region 62 is annealed for 180 seconds in a hydrogen atmosphere at 900 ° C., for example, to remove the natural oxide film on the substrate surface. Continuously in the same chamber, for example, at 600 ° C. and 100 ° C.
At Torr, amorphous silicon is deposited on the entire surface for 28 seconds at a flow rate of 10 slm of hydrogen gas and 1 slm of SiH ₄ gas.

Further, when single-crystal silicon is continuously annealed in the same chamber at 600 ° C. in an H ₂ atmosphere for 80 seconds to perform solid phase growth, the silicon single crystal on the substrate surface becomes a nucleus and amorphous silicon is formed. Convert to single crystal silicon. At this time, the SiO ₂ film 131
The portion in contact with the surface of the dummy gate 132 is not monocrystallized, and a side wall having an angle of 50 degrees with respect to the surface of the silicon substrate 61 is formed using the SiO ₂ film 131 and the dummy gate 132 as one end.

In this manner, an epitaxial silicon region which is inclined with respect to the silicon substrate 61 in a self-aligned manner with respect to the formation region of the dummy gate 132 is selectively formed on the surface of the silicon substrate 61. Next, portions remaining as amorphous silicon without being single-crystallized are removed with hydrofluoric nitric acid to form a selective growth epitaxial region 133 shown in FIG. 7B.

Next, as shown in FIG. 8 (b), on the selective growth epitaxial region 133 and on the dummy gate 132
And a 10 nm-thick SiO ₂ film 141 formed by CVD, for example.
It is formed by a method. The SiO ₂ film 141 formed on the epitaxial region 133 functions as a protective film for ion implantation 142 in the next step. On the other hand, the SiO ₂ film 141 on the region where the lower end of the side surface of the dummy gate 132 is in contact with the end of the epitaxial region 133 is formed on the source and drain sides of the gate electrode 68 to be formed later based on the difference between the thickness of the gate insulating film 171. Are formed on the inclined source and drain, and the shape of the inclined gate end 172 shown in FIG. 11B will be determined later. The active region and the gate electrode forming region which are thickened by the deposition of the SiO ₂ film 141 are shown by 143 in FIG.

Next, ion implantation 142 of an n-type impurity is performed. After the ion implantation 142, for example, thermal diffusion annealing combined with activation by RTA at 900 ° C. for 30 seconds is performed.
The implanted impurity is diffused to a region opposed to a gate end 172 having a slope shown in FIG.
The second source diffusion layer 152a shown in FIG.
Is formed. Ion implantation 1 on the inclined surface of selective growth epitaxial region 133
42, the epitaxial region 13
A first source diffusion layer 151a and a first drain diffusion layer 151b having an inclination due to an epitaxial layer facet are formed on a surface having an inclination of 3. Ion implantation 142
May be the same as in the first embodiment, for example.

Next, after depositing polysilicon on the entire surface of the device, the upper layer polysilicon is removed using CMP 153 with the dummy gate 132 as a stopper, and a polysilicon film 154 exposing the upper end of the dummy gate 132 is formed. . The material deposited on the entire surface of the device is not limited to polysilicon, but can be variously changed according to the material of the dummy gate 132 such as TEOS.

Next, as shown in FIG. 10B, the dummy gate 132 is removed by using hot phosphoric acid to form a concave portion 161 corresponding to the gate electrode portion. This recess 161
Is a region where the gate insulating film 171 and the gate electrode 68 are buried.

Prior to the formation of the gate electrode 68, channel ions 162 for _Vth control are selectively implanted into the recesses using the polysilicon film 154 and a photoresist as a mask, if necessary. By performing the channel ion implantation 162 at this stage, the ion implantation layer 163 can be selectively formed in the channel region. According to this method, the impurity concentration in the region where the second source diffusion layer 152a and the second drain diffusion layer 152b are formed can be reduced as compared with the case where non-selective channel ion implantation is used. The junction leakage current of the source and the drain can be reduced, and the junction capacitance can be reduced.

Next, the SiO ₂ films 131 and 141 formed on the bottom and side walls of the recess 161 are removed. The concave portion 161 after the removal has a second source diffusion layer 152a and a second drain diffusion layer 152b between the bottom surface and the side wall.
The tapered portion has the same inclination as that of the side surface. That is, the concave portion 1
Sidewall of by the thickness of the recess 161 of the SiO ₂ film 141 was formed on the side wall 61 extends, but since the SiO ₂ film 141 is formed on a side surface having a slope of epitaxial region 133, SiO ₂ film 141 Is removed and a part of the inclined epitaxial region 133 is exposed.

Next, as shown in FIG.
A gate insulating film 171 is formed in 61 by, for example, thermal oxidation. Note that the gate insulating film 171 is formed by CVD-
SiO ₂ film, CVD-SiON film, CVD-Si ₃ N ₄
A stacked film including a film may be used. This gate insulating film 17
1 is thinner than the SiO ₂ film 141, and is formed of, for example, a 3.5 nm SiO ₂ film. Thus, the SiO ₂ film 1
By forming the gate insulating film 171 thinner than 41, the gate insulating film 171 and the first source diffusion layer 151 are formed.
a and the boundary surfaces of the gate insulating film 171 and the first drain diffusion layer 151b with the regions 151a and 151a.
A gate end 172 having the same inclination as the side surface of b can be obtained.

Next, in order to form the gate electrode 68, a conductive film is deposited on the entire surface so as to fill the recess 161. Thereafter, the conductive film outside the recess 161 is polished and removed by the CMP method. Gate end 1 having both ends of gate electrode 68 inclined
The first source diffusion layer 151a and the first drain diffusion layer 151b facing 72 function as a storage layer. As a conductive film for forming the gate electrode 68, a metal film can be used. This is because the gate electrode 68 is not affected by the high-temperature process because the high-temperature annealing process for activating the source and the drain has been completed. Specifically, for example, a laminated structure of TiN and Al is used.

Next, as shown in FIG.
The polysilicon film 154 is removed by the method and the interlayer insulating film 6 is removed.
9 is formed on the entire surface. Polysilicon film 1 by CDE method
In order to remove 54, a cap of an insulating film layer is used on the gate electrode 68 according to the type of the conductive film used for the gate electrode 68, and then the polysilicon film 154 is removed by a CMP method or the like. This is performed after removing the insulating film and exposing the surface. The steps after forming the interlayer insulating film 69 are the same as those in the first embodiment.

In the concave transistor formed by the above steps, the surface corresponding to the substrate surface 66 in the first embodiment is the epitaxial layer surface 134. The channel surface 65 of the concave transistor structure is the surface of the silicon substrate 61, which is different from the case where the surface of the silicon substrate 61 etched by the RIE method is used as the channel surface 65 in the first embodiment.

In the above steps, the dummy gate 132 made of a nitride film is used to perform selective epitaxial growth for the source and drain having an inclination of about 50 degrees with the surface of the silicon substrate 61 by using the (111) plane by solid phase growth. Area 1
Although 33 is formed, a (311) plane having a gentler inclination of about 30 degrees can be used instead. In this case, a selective epitaxial region is formed by vapor phase growth using a dummy gate of a laminated film of a 50 nm SiO ₂ film and a 50 nm nitride film.

According to the present embodiment, the dummy gate 132
In the case of the first embodiment, separate lithography processes are required at the time of forming the concave portion and at the time of forming the internal gate electrode because the positions of the source and the drain having inclinations are determined in a self-alignment manner with the gate position determined by lithography at the time of manufacturing. In comparison with the above, there are fewer causes of channel length variation.

Further, the channel surface 65 is not exposed to the etching by the RIE method, and the surface of the silicon substrate 61 is not damaged during the etching. By using the selective epitaxial region 133, the advantage of suppressing the short channel effect of the concave transistor can be utilized while using the same high quality silicon surface as the planar transistor. By growing the surface of the portion of the epitaxial region 133 adjacent to the gate electrode 68 obliquely, the first source diffusion layer 151a and the first drain diffusion layer 151b having an inclination can be formed.

In this embodiment, the ion implantation layer 163 for controlling the threshold voltage can be selectively formed in the channel portion below the gate electrode 68. In order to realize the selective epitaxial layer used in the present embodiment, the dummy gate 1 using Si ₃ N ₄ is used to selectively epitaxially grow the silicon layer except for the region where the gate electrode 68 is provided.
32 is used. That is, after another portion of the transistor is manufactured using the dummy gate 132, the dummy gate 13
2 is removed, and the gate electrode 68 is buried (damascene gate) using a so-called damascene process (inlaid process). By using this damascene gate process, ion implantation can be selectively performed only on the channel portion.

(Fifth Embodiment) FIGS. 13 and 14 are views for explaining a concave MIS transistor according to a fifth embodiment of the present invention. This embodiment relates to a manufacturing method for realizing the structure having the features of the first concave MIS transistor structure of the present invention shown in FIG. 1B. This embodiment is the same as the fourth embodiment up to the middle of the manufacturing process, and a detailed description of the parts common to the fourth embodiment is omitted.

In the fourth embodiment, the second source diffusion layer 1
Contact holes 73a and 73b to 52a and the second drain diffusion layer 152b are formed on the epitaxial region 133 separated from the gate electrode 68. This is because, in order to prevent a short circuit between the gate and the wiring, the interlayer insulating film 69 is etched by lithography and RIE.
When the contact holes 73a and 73b are opened, it is necessary to separate the gate electrode 68 from the wirings 70a and 70b, and this is realized by providing a sufficient distance. On the other hand, in order to realize the miniaturization of the integrated circuit, it is desirable to reduce the distance between the contact holes 73a and 73b and the gate electrode 68.

Therefore, in the present embodiment, the first source diffusion layer 151a and the first drain diffusion layer 151 having an inclination are provided.
forming a side wall 191 of a nitride film on the mask b to make the distance between the gate and the contact on the mask substantially zero;
The contact is formed in a self-aligned manner, and the area for forming the transistor is significantly reduced.

A method of manufacturing the concave MIS transistor according to the present embodiment will be described with reference to FIGS. A second source diffusion layer 152a and a second drain diffusion layer 152b are formed using the dummy gate 132, and the dummy gate 132 is removed to form a recess 161.
The steps up to the formation of 63 are the same as the steps of FIGS. 7 to 10 shown in the fourth embodiment.

After the steps shown in FIGS.
As shown in FIG. 18, the SiO ₂ films 131 and 141 formed on the bottom surface and the side wall of the concave portion 161 are removed, and the concave portion 161 is removed.
A gate insulating film 171 is formed therein by, for example, thermal oxidation or the like. By forming this gate insulating film 171 thinner than the SiO ₂ film 141, a gate end 172 inclined with respect to the surface of the silicon substrate 61 is formed.

Next, a conductive film is deposited on the entire surface so as to fill the inside of the concave portion 161, and then the conductive film outside the concave portion is polished and removed by the CMP method. After that, the upper portion of the gate electrode 68 in the concave portion 161 is etched by 10 nm by RIE, and then a nitride film is deposited. Then, after depositing this nitride film,
The nitride film outside the concave portion 161 is polished and removed by the CMP method, and a protective nitride film 192 for the gate electrode 68 is formed.

Next, after cleaning the surface of the polysilicon film 154 by, for example, hydrofluoric acid treatment, the polysilicon film 154 is removed.
4 is removed by CDE. Next, after depositing a the Si ₃ N ₄ film about the whole surface, for example a thickness of 20 nm, the Si ₃
By etching the entire surface of the N ₄ film by the RIE method, so-called sidewalls are left, and sidewalls 191 made of Si ₃ N ₄ are formed on the inclined first source diffusion layer 151a and first drain diffusion layer 151b. This Si ₃
The active region and the gate electrode formation region which are thickened by the deposition of the N ₄ film are shown at 194 in FIG.

Next, as shown in FIG. 14B, an interlayer insulating film 69 is deposited on the entire surface, and contact holes 201a and 201b are formed by RIE. The mask pattern of the contact holes 201a and 201b of the present embodiment is designed so that the distance to the gate electrode 68 is zero or overlaps with the gate electrode 68, and RIE for opening the contact on the source and drain is performed. Is performed in the vicinity of the gate electrode 68, since the gate electrode 68 is protected by the side wall 191 and the protective nitride film 192, the wirings 203a and 203b are buried in the contact holes without being short-circuited to the gate electrode 68. Can be formed.

In this embodiment, the first source diffusion layer 15
Si ₃ N ₄ sidewalls 19 are formed on the outer surface of the gate end 172 having the same inclination as that of the first drain diffusion layer 151 b.
By forming 1, the parasitic capacitance can be suppressed by increasing the distance between the gate electrode 68 and the source and drain while suppressing the short channel effect in the concave channel MIS transistor. Further, the wiring 203
By forming the transistors a and 203b using self-aligned contacts, the transistor area can be reduced, and the distance between the channel and the wirings 203a and 203b can be minimized to suppress the parasitic resistance.

In the present embodiment, the first source diffusion layer 151a and the first drain diffusion layer connecting the storage layers of the first source diffusion layer 151a and the first drain diffusion layer 151b to the wirings 203a and 203b are provided. Since the surface of the insulating film 151b with the insulating films 171 and 191 is formed linearly, the current path can be shortened, the parasitic resistance can be further reduced, and the resistance of the transistor can be further reduced.

(Sixth Embodiment) FIGS. 15 to 19 are views for explaining a sixth embodiment of the present invention. In the present embodiment, the recess is formed by using RIE as in the first embodiment, but the method of forming the source and the drain is different.

More specifically, the first embodiment forms the inclined source diffusion layer 71a and the drain diffusion layer 71b after the formation of the recess, the gate insulating film 67, and the gate electrode 68. Then, an impurity region serving as a source and a drain is formed on the surface of the silicon substrate 61 before the concave portion is formed, and the surface of the silicon substrate 61 is etched along with the inclined side surface, thereby forming the inclined source diffusion layer and the drain region. It is forming. Hereinafter, the manufacturing process of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 15B, an element isolation insulating film 64 is formed on a p-type silicon substrate 61 at a peripheral portion of an active region 62. For example, a trench having a depth of about 0.35 μm is dug by using a reactive ion etching (RIE) method, and an insulating film 64 such as SiO ₂ is buried in the trench to form an STI (Shallow TrenchIs).
olation). Next, after a sacrificial SiO ₂ film 211 having a thickness of about 10 nm is formed on the active region 62 by, for example, a thermal oxidation method, a channel ion implantation layer for adjusting a threshold voltage is formed (not shown). ,
Concentration of 3 × 10 ²⁰ to be impurity regions of source and drain
An impurity region 212 of about cm ^-3 is formed by ion implantation.

A so-called CMOS for forming n-channel and p-channel MIS transistors on the same substrate
In the case of the (Complementary Metal-Oxide-Semiconductor) structure, a p-type well is formed in the n-channel transistor formation region of the silicon substrate 61, and then 212 is formed as an n-type impurity region. Hereinafter, in the present embodiment, the case of an n-channel transistor will be described. In the case of a p-channel transistor, the types of impurities may be reversed. Further, the impurity region 212 serving as a source and a drain may be formed by a high-concentration epitaxial region grown on the entire surface of the active region 62.

Next, as shown in FIG. 16B, the same photoresist pattern as that for forming the gate electrode, for example, as in the case of forming the recess 92 in FIG. 2B of the first embodiment, for example. 22 using a mask having
Then, RIE damage recovery processing is performed. Following this recovery process, the activation of the impurity region 212
The heat diffusion is performed at 0 ° C. for about 5 minutes to form the source diffusion layer 212.
a and the drain diffusion layer 212b are formed.

The vicinity of the region where the concave portion 221 is formed is a region for forming a channel portion of the concave transistor and a source and a drain having an inclination in the active region 62.
It is obtained by selectively etching the silicon substrate 61 with an inclination. The angle formed by the tapered side surface of the concave portion 221 with the surface of the silicon substrate 61 is determined by the angle shown in FIG.
8 is large with respect to the vertical plane so that the parasitic capacitance between the gate electrode 68 and the source diffusion layer 212a and between the gate electrode 68 and the drain diffusion layer 212b is small, and the source diffusion layer 212a and the drain adjacent to the gate electrode 68 are small. The RIE condition is adjusted so that the effective thickness of the diffusion layer 212b is sufficiently reduced and the parasitic resistance is reduced with respect to the horizontal plane so that the parasitic resistance is reduced. Formed at an angle of 60 °.

When forming the recess 221 using the mask of the gate electrode 68, the recess is also formed in the portion of the element isolation insulating film 64 that is continuous from the gate to the contact, leaving a sufficient thickness of the element isolation insulating film 64. It may be formed.

Next, as shown in FIG. 17B, after the gate insulating film 67 is formed, the edge of the gate electrode 68 is included in the recess 221 and located outside the channel surface 65 region. And the gate electrode 68 and the source diffusion layer 212a, and the gate electrode 68 and the drain region 21
2b is formed so as to have a region overlapping with the gate insulating film 67 interposed therebetween.

As the gate insulating film 67, a laminated film including an insulating film formed by a low-temperature process is used. That is, although the gate insulating film 67 is formed by heat treatment, the impurity region 212 serving as a source and a drain is formed earlier than the gate insulating film 67. This is because it is necessary to take into account that the depth does not become deeper than the channel surface 65 on the silicon substrate 61 side. Specifically, as the material of the gate insulating film 67, for example, a CVD-SiO ₂ film, a CVD-SiON film, a CVD
A laminated film containing -Si ₃ N ₄ film.

The gate electrode 68 is formed of a gate insulating film 67.
Is patterned so as to have a region that overlaps with the impurity region 212 through the region. The region that is located shallower than the depth of the channel surface 65 and that forms the source and drain accumulation layers connected to the channel inversion layer during operation is formed. It is for forming. If a recess is also formed in the element isolation insulating film 64 when the recess 221 is formed, the element isolation insulating film 64 can be formed.
The thickness of the upper gate wiring can be increased by the thickness of the recess, and the resistance of the gate wiring can be reduced.

Next, as shown in FIGS. 18 to 19, after an interlayer insulating film 69 made of SiO ₂ is formed on the entire surface, the first
Using the same process as that described in the embodiment, the contact holes 73a and 73b are provided and the wiring 70 is formed.
By forming a and 70b and forming a passivation film (not shown) on the entire surface, the transistor part manufacturing process of the fourth embodiment is completed. The inclined source diffusion layer and the drain region in the fourth embodiment are shown by oblique lines in FIG.

FIG. 20 shows a concave M according to a modification of the present embodiment.
FIG. 20 is a diagram showing the overall configuration of an IS transistor, and FIG.
20A is a top view, and FIGS. 20B to 20D are cross-sectional views of 25A-25A ′ in FIG.
25B ′ cross-sectional view and 25C-25C ′ cross-sectional view are shown. In the following modified examples, portions common to the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

In the case of the first embodiment shown in FIG. 1B, the first source diffusion layer 71 adjacent to the gate electrode 68 is formed.
a and the gate insulating film 67 of the first drain diffusion layer 71b
Not only the interface with the silicon substrate 61 but also the interface with the silicon substrate 61 is formed with an inclination with respect to the surface of the silicon substrate 61. In this modification, as shown in FIG. Of the drain diffusion layer 111b, only the interface with the gate insulating film 67, which is the main current path, is formed with an inclination to the surface of the silicon substrate 61,
The boundary surface portion with the silicon substrate 61 is formed in parallel with the surface of the silicon substrate 61 while keeping the junction depth at zero or minus with respect to the channel surface 65.

The main current path at the time of the transistor operation in this modification is the same as that of the present embodiment. Also,
The source diffusion layer 111a and the drain diffusion layer 111b are formed above the channel surface 65, and the source diffusion layer 111a and the drain diffusion layer 111b are formed to be inclined with respect to the surface of the silicon substrate 61. As in the present embodiment, the channel effect can be suppressed and the parasitic resistance and the parasitic capacitance can be reduced.

This modified example is different from the present embodiment in the first embodiment.
As in the embodiment, the source and the drain are connected to the gate electrode 6.
8 is formed after the formation. Even in this case, almost the same structure as the present embodiment can be realized.

(Seventh Embodiment) FIG. 21 is a sectional view showing the overall configuration of a semiconductor device according to a seventh embodiment of the present invention. This embodiment is a modification of the first embodiment, and the description of the parts common to the first embodiment will be omitted. In the present embodiment, by increasing the radius of curvature of the current path using a curve, the current path is formed to be linear when viewed locally, and the current path is formed while suppressing the short channel effect. Form short.

The manufacturing process of the semiconductor device according to this embodiment is almost the same as that of the first embodiment. In the present embodiment, the first
When the recess 92 of the embodiment shown in FIGS. 2 to 7 is formed by RIE, the etching conditions are adjusted so that the inclined side surface of the recess 92 or the surface defining the channel region is rounded.

The source and the drain are not only the first source diffusion layer 261a and the first drain diffusion layer 261b, but also the second source diffusion layer 262a and the second drain diffusion layer 262a to supplement the thickness. 262b is formed.

After the gate insulating film 263 is formed, the edge of the gate electrode 68 is included in the recess 221 so as to be located outside the channel region, and the gate electrode 6 is formed.
8 is a first source diffusion layer 2 with a gate insulating film 263 interposed therebetween.
61a and the first drain diffusion layer 261b.

The present embodiment differs from the conventional concave transistor in the following points. The current path is rounder and shorter than the conventional concave transistor shown in FIG. This is because, by adjusting the etching conditions, the channel region is formed to be round from the channel region to the source diffusion layer 261a and the drain diffusion layer 261b. Further, by forming the gate insulating film 263 formed on the side surface of the gate electrode 68 with roundness, the effective film thickness of the insulating film between the gate electrode 68 and the source and drain is increased, thereby suppressing the parasitic capacitance. ing. Further, the source and drain accumulation layers connected to the channel region are located at an upper surface than the channel region with an inclination, thereby suppressing the short channel effect. Therefore, since the current path from the channel to the storage layer is also formed round,
It is possible to prevent a decrease in the amount of current.

In the first embodiment, the carrier distribution is made closer to a straight line by changing the angle from the acute angle to the obtuse angle with respect to the corner portions at both ends of the channel surface 65 of the ordinary concave transistor of FIG. In the present embodiment, however, the obtuse corners at both ends of the channel region are formed to have a gentle structure with no more corners, so that the gate insulating film 2 is formed.
This realizes an improvement in the withstand voltage of 63 and prevention of electron mobility deterioration at the corners.

Further, the radius of curvature can be made larger than that of a conventional concave transistor in which the corner portion of the channel is formed gently, so that the withstand voltage can be improved or the mobility can be prevented more effectively.

The advantage of making the radius of curvature of the channel region formed inside the concave portion uniform is the same as that of the second embodiment.

(Eighth Embodiment) FIG. 22 is a sectional view showing the overall configuration of a semiconductor device according to an eighth embodiment of the present invention. Descriptions of the present embodiment that are common to the sixth embodiment will be omitted.

In the present embodiment, the present invention is applied to a so-called buried channel type transistor in a planar transistor. In the buried channel transistor, a threshold voltage can be adjusted to a desired value according to the work function of the gate electrode 68 by providing a region having the same type as the source and the drain in the channel portion.
This is particularly effective in the S circuit.

For example, in the case of an n-type transistor, an n-type buried channel 271 is formed on a p-type silicon substrate 61.
, A gate insulating film 67 and a gate electrode 68 are formed. In this embodiment, when the recess 221 of FIG. 16B of the fourth embodiment is formed by RIE, the etching condition is adjusted to make the etching depth shallower than the junction surface of the impurity region 212. , Buried channel 27
1 are formed.

In the buried channel type recessed transistor of FIG. 22, the edge of the gate electrode 68 is formed so as to be included in the inside of the recess 221 and to be located on the inclined side surface of the recess 221. Because it ’s an embedded channel,
The polarity of the source and the drain is the same as the polarity of the buried channel 271. Therefore, when the conventional concave transistor of FIG. 29B is used as a buried channel, the inversion layer 47 on the side surface of the recess and the inversion layer 46 on the bottom surface of the recess are respectively replaced with storage layers (not shown).

The corresponding current paths are the same as those indicated by arrows in the conventional concave transistor structure of FIG. The current path in the present embodiment in FIG. 22 is indicated by a chain line.

The structure of FIG. 22 is different from the other embodiments in that
An advantage that the threshold voltage can be adjusted as described above, as well as advantages, will be described. In the structure of another embodiment in which the corner portions at both ends of the channel surface 65 that are not the buried channel are exposed, when the channel inversion layer is formed in this corner portion, the electric field diverges in the corner portion, and the carrier density in the corner portion is increased. Becomes lower than the carrier density at the channel surface 65, resulting in a decrease in current value.

In the concave transistor shown in FIG. 22, the sharp corners at both ends of the channel surface 65 are covered with impurity regions without being exposed, so that the carrier density at the corners is increased and the carrier density at the corners is reduced. The resulting decrease in current is suppressed.

The point that the sixth, seventh, and eighth embodiments are superior to the first embodiment is that, in the first embodiment, the source diffusion layer and the drain are formed using the gate electrode 68 formed inside the concave portion 92 as a mask. Ion implantation 9 for forming diffusion layer
In the case where the misalignment between the concave portion 92 and the gate electrode 68 occurs due to the third step, the second source diffusion layer 72a and the second drain diffusion layer 72b are formed asymmetrically, whereas the sixth to eighth embodiments are performed. In the embodiment, the concave portion 161 is formed by etching the impurity region which is formed symmetrically in advance, so that there is no displacement between the gate electrode 68 and the impurity region.
The lower ends of the source and the drain are always formed symmetrically.

The sixth, seventh, and sixth embodiments are different from the fourth embodiment.
The advantage of the eighth embodiment is that the fourth embodiment uses a dummy gate to form the selective epitaxial region 133 and complicates the process, whereas the present embodiment has a small number of process steps, Because it is short, the cost can be reduced.

(Ninth Embodiment) FIGS. 23 to 24 are views for explaining a semiconductor device according to a ninth embodiment of the present invention. This embodiment implements the structure shown in FIGS. 15 to 20 of the sixth embodiment.

The semiconductor device according to the present embodiment is different from the semiconductor device according to the second embodiment in that the semiconductor device according to the second embodiment has a tilt due to an epitaxial layer facet after the formation of the selective epitaxial region 133, the gate insulating film 67 and the gate electrode 68. 1 source diffusion layer 151a and first drain diffusion layer 1
In the present embodiment, the epitaxial regions 281a and 281a and the epitaxial regions 281a and
By forming the impurity region 81b as an impurity region serving as a source and a drain, the source and the drain have an inclination at a boundary surface with the gate insulating film 171 and an inclination at a junction surface with the silicon substrate 61 parallel to the surface of the silicon substrate 61. Is formed. The formation of the source and the drain is performed by the same manufacturing process as in the fourth embodiment.

Hereinafter, the manufacturing process of this embodiment will be described in comparison with the second embodiment. First, as shown in FIG. 23A, selective epitaxial layer impurity regions 281a and 281b are formed on a silicon substrate 61 on which a dummy gate 132 is formed. The region where the selective epitaxial layer impurity regions 281a and 281b are formed is shown in FIG.
This is the same region as the region where the selective epitaxial region 133 is formed in (b).

In the present embodiment, when depositing amorphous silicon on the entire surface, for example, arsine AsH ₃ gas of 20 sccm is supplied in addition to the hydrogen gas and the SiH ₄ gas. The difference between the selective growth epitaxial region 133 and the selective growth epitaxial layer impurity regions 281a and 281b is that the selective growth epitaxial region 133 is formed as a crystalline silicon layer containing no impurities.
Selectively grown epitaxial layer impurity regions 281a and 28
Under the above conditions, 1b is formed to contain high-concentration impurities, that is, for example, about 3 × 10 ²⁰ cm ⁻³ As in the case of an n-type concave MOSFET.

Next, an SiO ₂ film 141 is formed as a protective film on the entire surface of the device (FIG. 23B). In this regard, FIG.
This is the same as (b), but in this embodiment, the ion implantation 14
2. No activation annealing is performed. This is because the impurity region need not be implanted since the selectively grown epitaxial layer impurity region is already formed containing a high concentration of impurity.
Next, a polysilicon film 154 exposing the upper layer of the dummy gate 132 is formed (FIG. 23C). In this regard, FIG.
Same as 1 (b).

The subsequent processes are performed in the same manner as in the second embodiment, and the completed concave transistor is shown in FIGS. FIG. 24A is a top view, and FIGS.
24D is a cross-sectional view of 29A-29A ', 29B-29B', and 29C-29C 'of FIG.

In the present embodiment, compared to the second embodiment, the ion implantation 142 for forming the source and drain impurity regions and the activation annealing step thereof are omitted, and the process is simplified. Further, impurity regions 281a and 281b for forming a source and a drain having an inclination
Is formed on the silicon substrate 61 in advance, the gate insulating film 171 and the gate end portion 172 having the inclination are formed. Therefore, the edge of the gate electrode 68 is set at a position higher than the junction position of the source / drain impurity region having the inclination. The gate electrode 68 can be automatically formed outside the channel and on the side surface of the concave portion including the source and the drain having an inclination, and the gate electrode 68 automatically has a region overlapping the source and the drain with the gate insulating film 171 interposed therebetween. It is formed.

As in the sixth embodiment, the present embodiment has source and drain impurity regions 221a and 221b whose junction surfaces are inclined parallel to the surface of the silicon substrate 61. The present embodiment has an advantage over the sixth embodiment in that a channel is formed by using selective epitaxial growth using a nitride film on a channel portion as a mask instead of RIE to form a concave portion. The substrate surface to be etched is not damaged during etching, and the substrate surface protected by the nitride film can be used for the channel.

Also, impurity regions 281a and 281b having inclination in a self-aligned manner by using selective epitaxial growth.
In the sixth embodiment, the source and the drain are formed.
Compared to performing a lithography process at the time of formation and requiring high-precision alignment, there are fewer factors of structural variation.

Further, in the sixth embodiment, after forming the element isolation insulating film 64 of FIG. 15B, the recess 221 is formed so that the side surface of the element isolation insulating film 64 is exposed as shown in FIG. However, depending on the shape of the side surface of the element isolation insulating film 64, such as the inclination, the side surface is not exposed and the silicon portion remains, which may affect the device characteristics. In the case of this embodiment, no concave portion in the substrate is formed and FIG.
As shown in (c), a source and a drain are formed as projections using an epitaxial layer selectively formed on a substrate. In addition, since the channel portion and the inclined source and drain are formed as a concave portion along with the formation of the concave portion, the side surface of the element isolation insulating film 64 in FIG. The influence of the shape on the element characteristics can be avoided.

(Tenth Embodiment) FIG. 25 shows a first embodiment of the present invention.
FIG. 11 is a cross-sectional view illustrating the overall configuration of the semiconductor device according to the zeroth embodiment. This embodiment shows a case where the method of manufacturing a semiconductor device according to the ninth embodiment is applied to a buried channel type concave transistor. The description of the parts common to the ninth embodiment is omitted, and only the differences from the ninth embodiment will be described below.

In the buried channel type recessed transistor according to this embodiment, a buried channel impurity region 301 is also formed on the surface of the active region. That is, an impurity region 301 having the same polarity as the source and the drain is formed on the bottom surface of the gate electrode 68 and on the surface of the silicon substrate 61 opposite to the gate insulating film 171. This buried channel type concave transistor is particularly effective in a CMOS circuit as in the eighth embodiment.

The present embodiment is manufactured by the same manufacturing method as that of the ninth embodiment. However, before forming the SiO ₂ film 131 of FIG. After forming the buried channel impurity region 301, a process similar to the process described in the ninth embodiment is performed. Thus, the source and drain epitaxial regions 281a and 281b can be connected by the region 301 having the same polarity.

As described above, according to the present embodiment, a structure having both the advantages shown in the eighth and ninth embodiments can be realized.

In the above embodiment, even if one of the source and the drain has the structure shown in the present invention and the other has the conventional structure, the effect of the present invention is not exerted. Of course.

[0199]

As described above, according to the present invention, the gate electrode has a region where the source and the drain face each other. Therefore, since the opposing region operates as the storage layer, the spreading resistance is removed, and the channel and the contact are connected by the current path having a low resistivity and a short length, so that the parasitic resistance can be reduced.

Further, since the region operated as the storage layer is formed at a position shallower than the channel region, there is no need to form the region operated as the storage layer on the same plane as the channel region, and the short channel effect is suppressed. be able to.

Further, since the source and the drain on the side surface of the gate electrode are formed to be inclined with respect to the surface of the semiconductor layer, the distance between the gate electrode and the source and the distance between the gate electrode and the drain are widened, and the parasitic capacitance can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the embodiment;

FIG. 3 is a view showing a manufacturing process of the semiconductor device according to the embodiment;

FIG. 4 is an exemplary sectional view showing a main part of the semiconductor device according to the same embodiment;

FIG. 5 is a diagram showing an overall configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing the overall configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a view showing a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a view showing a manufacturing process of the semiconductor device according to the same embodiment.

FIG. 9 is a view showing a manufacturing process of the semiconductor device according to the same embodiment.

FIG. 10 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 11 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the same embodiment.

FIG. 13 is a view showing a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 14 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 15 is a diagram showing a manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 16 is a view showing a manufacturing step of the semiconductor device according to the same embodiment.

FIG. 17 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 18 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 19 is a view showing the manufacturing process of the semiconductor device according to the same embodiment.

FIG. 20 is a diagram showing an overall configuration of a semiconductor device according to a modification of the embodiment.

FIG. 21 is a diagram showing an overall configuration of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 22 is a diagram showing an overall configuration of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 23 is a view showing an overall configuration of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 24 is a view showing the manufacturing process of the semiconductor device in the embodiment.

FIG. 25 is a diagram showing an overall configuration of a semiconductor device according to a tenth embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the overall configuration of a conventional planar transistor.

FIG. 27 is a diagram showing an electron concentration distribution during operation of a conventional planar transistor.

FIG. 28 is a diagram showing a current density distribution of a conventional planar transistor.

FIG. 29 is a diagram showing an overall configuration of a conventional concave transistor.

FIG. 30 is a cross-sectional view showing the overall configuration of a conventional transistor including a source region and a drain region having an oblique substrate surface.

[Explanation of symbols]

Reference Signs List 61 silicon substrate 62 active region 63 element isolation region 64 element isolation insulating film 65 channel surface 66 substrate surface 67, 105, 171, 263 gate insulating film 68 gate electrode 69 interlayer insulating film 70a to 70c , 110a, 110b, 203a, 20
3b ... wiring 71a, 71b, 106a, 106b, 151a, 15
1b, 261a, 261b... First source and drain diffusion layers 72a, 72b, 108a, 108b, 152a, 15
2b, 262a, 262b ... second source and drain diffusion layers 73 a to 73 c, 210a, 201b ... contact hole 91,103,131,141 ... SiO ₂ film 92,102,104,161,221 ... recess 93,142, 162: ion implantation 101: Si ₃ N ₄ film 107: sidewall nitride film 109, 192: protective nitride film 94a, 94b, 212, 301: impurity region 132: dummy gate 133, 281a, 281b: epitaxial region 134: epitaxial layer surface 171 ... insulating film 172 ... gate end 153 ... CMP 154 ... polysilicon film 163 ... ion implantation layer 191 ... sidewall 111a, 111b, 212a, 212b ... source and drain diffusion layer 271 ... buried channel

Claims (16)

[Claims] A semiconductor layer having at least a concave portion having a side wall that is gentler than a right angle, a gate electrode formed above a bottom surface of the concave portion with a gate insulating film interposed therebetween, and insulating at a side surface of the gate electrode. A source region and a drain region formed in the semiconductor layer with a boundary between the insulating layer and the insulating film inclined with respect to the semiconductor layer surface; and a wiring contact connected to the semiconductor layer surface. An edge of the gate electrode is located inside a concave portion provided in the semiconductor layer, and a region where at least one of the gate electrode and the source region or the gate electrode and the drain region is opposed to each other Wherein at least one of the source region and the drain region in the opposed region operates as a storage layer. MIS-type semiconductor device. 2. An insulating film formed between the source region or the drain region and the gate electrode, a region other than the region where the gate electrode and the source region or the region where the gate electrode and the drain region face each other. 2. The MIS semiconductor device according to claim 1, wherein the MIS semiconductor device is formed to be thicker than the opposed region. 3. A semiconductor layer having at least a concave portion having a side wall that is gentler than a right angle, a gate electrode formed on a bottom surface of the concave portion with a gate insulating film interposed therebetween, and a side surface of the gate electrode, A source region and a drain region formed in the semiconductor layer with the boundary between the insulating film and the insulating film inclined with respect to the surface of the semiconductor layer, and formed below a bottom surface of the concave portion of the semiconductor layer; At a first junction position of the source region and the channel region in the vicinity of the gate insulating film, the source region and the gate electrode have a first opposed region, At a second junction position between the drain region and the channel region near the gate insulating film, the drain region and the gate electrode have a second opposed region; Alternatively, the source region or the drain region of at least one of the second opposed regions operates as a storage layer, and an insulating layer formed between at least one of the source region or the drain region and the gate electrode The MIS semiconductor device, wherein an insulating film in a region other than the first or second opposed region of the film is formed thicker than the first or second opposed region. 4. The device according to claim 3, wherein the height of the gate insulating film has a portion that continuously increases from near the center of the channel region to at least one of the source region and the drain region. MIS type semiconductor device. 5. The semiconductor device according to claim 1, further comprising: a contact formed on the surface of the source region and the drain region so as to be separated from the gate electrode. A current path is formed between the contact and the gate insulating film along a boundary surface with the gate insulating film, and a distance between the contact and the gate electrode is formed to be shorter than 1.5 times a gate width. The MIS type semiconductor device according to claim 3, wherein 6. The semiconductor device according to claim 1, wherein at least one of the surface of the source region and the surface of the drain region in a region closer to the contact than the first and second opposed regions is formed to be inclined with respect to the surface of the semiconductor layer. The MIS type semiconductor device according to claim 5, wherein 7. A height of at least one of lower surfaces of the source region and the drain region in the vicinity of the first or second opposed region is formed higher than a height of the channel region. MI according to claim 3
S-type semiconductor device. 8. The MIS according to claim 3, wherein the source region and the drain region are formed of a material having the same conductivity type as a channel region formed between the source region and the drain region. Type semiconductor device. 9. The gate insulating film between the channel region and the gate electrode is formed linearly, and is formed between both ends of the linear gate insulating film and side walls that are gentler than a right angle. 4. The MIS semiconductor device according to claim 3, wherein each of the MIS type semiconductor devices has a corner portion, and at least one of the first and second joining positions is located between the corner portions. 5. 10. An impurity concentration of the source region or the drain region at one end located below the gate electrode edge of at least one of the first and second opposed regions is 1 × 10 ¹³ cm ⁻² or more. 4. The method according to claim 3, wherein
2. The MIS semiconductor device according to 1. 11. A step of forming, by RIE, a concave portion having a side wall that is gentler than a right angle in a semiconductor layer, and a step of forming a gate insulating film so as to cover the semiconductor layer surface.
Forming a conductive film on the gate insulating film including the concave portion, and forming a gate electrode by patterning the conductive film using a lithography method so that side walls are located on side surfaces of the concave portion; A method for manufacturing a MIS type semiconductor device, comprising: 12. A step of selectively forming a first insulating film and a dummy gate on the first semiconductor layer and selectively solid-phase growing a semiconductor material using the dummy gate as a mask to form a right angle. Second with looser sidewalls
Forming a semiconductor layer with the dummy gate interposed therebetween;
Removing the first insulating film and the dummy gate;
Selectively forming a gate insulating film and a gate electrode sequentially in a region where the first insulating film and the dummy gate have been formed. 13. After the formation of the second semiconductor layer, the second semiconductor layer
Forming a second insulating film so as to cover the semiconductor layer and the surface of the dummy gate; depositing a filler on the second insulating film; planarizing and removing the surface of the filler to remove the dummy gate; And removing the first and second insulating films formed on the side walls of the dummy gate together with the dummy gate, so that the same inclination as the side surface of the second semiconductor layer is formed between the bottom surface and the side wall. Forming a concave portion having a tapered portion, forming a gate insulating film on the bottom surface of the formed concave portion, and filling a conductive material in the concave portion formed with the gate insulating film by using a damascene process. 13. The MI according to claim 12, comprising:
A method for manufacturing an S-type semiconductor device. 14. The method according to claim 12, wherein the solid phase growth is epitaxial growth. 15. A step of forming a source region and a drain region in the semiconductor layer with the gate electrode interposed therebetween, and forming an interlayer insulating film on the semiconductor layer so as to cover the gate electrode, the source region, and the drain region. Forming a contact hole for connecting a wiring to at least one surface of the source region or the drain region by selectively removing the interlayer insulating film using reactive ion etching, 12. The method according to claim 11, wherein the step of forming the contact hole includes forming the contact hole in a self-aligned manner with the gate electrode by using an insulating film for protecting a side wall and a surface of the gate electrode as a mask. MIS described
Of manufacturing a semiconductor device. 16. A step of forming a source region and a drain region on a surface of the second semiconductor layer, and after forming the gate electrode, forming an insulating film on a side wall and a surface of the gate electrode to protect the gate electrode. Forming an interlayer insulating film on the first semiconductor layer so as to cover the insulating film; and selectively removing the interlayer insulating film by reactive ion etching using the insulating film as a mask. 13. The method of manufacturing a MIS type semiconductor device according to claim 12, wherein a contact hole connected to a wiring is formed in at least one surface of the source region or the drain region in a self-aligned manner with the gate electrode. .