JP4774882B2 - Insulated gate field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same, and more particularly to an insulated gate field effect transistor capable of increasing carrier mobility in a channel and a method for manufacturing the same.

  As a method for realizing high-speed operation by reducing the parasitic resistance and parasitic capacitance of the field effect transistor, there is a method of shortening the gate length. However, when the gate length is shortened, a so-called short channel effect occurs in which a current flows between the source and the drain even when the gate is turned off. Therefore, in order to suppress the short channel effect, it is necessary to weaken the electric field strength at the drain end.

  For example, in the MIS type semiconductor device described in Patent Document 1, high-concentration source / drain regions are regrown by epitaxial growth, and these regions are formed at a location higher than the channel. Thus, even when the gate length is shortened, the occurrence of the short channel effect can be suppressed.

  In some cases, an extension portion extending from the high concentration source / drain region to the channel side is provided as in the insulated gate field effect transistor 1 shown in FIG. That is, in the insulated gate field effect transistor 1 shown in FIG. 13, the region of the semiconductor substrate 2 where the channel is formed under the gate insulating film 3 on which the gate electrode G is formed, and the regions are in contact with and separated from each other. The two extension portions 4 (the extension portion on the source electrode S side and the extension portion on the drain electrode D side) formed in this manner are provided. Further, a source region 5 and a drain region 6 are formed on the extension portion 4 so as to be further apart from the opposing ends of the extension portions 4 in a direction away from each other.

  In the insulated gate field effect transistor 1 shown in FIG. 13, the surface of the extension part 4 where the source region 5 and the drain region 6 are not formed and the side surface of the gate insulating film 3 are covered with the insulating film 7 made of SiN. ing. The gate insulating film 3 is composed of two layers, a lower Si oxide film 3a and an upper polycrystalline silicon film 3b, and a part of the Si oxide film 3a runs up to a region covering the extension portion 4. Reference numeral 16 denotes an interlayer film covering the constituent parts of the field effect transistor. In the insulated gate field effect transistor 1 shown in FIG. 13, the presence of the extension portion 4 allows the source region 5 and the drain region 6 to be separated from the channel, thereby suppressing the short channel effect.

JP 2000-82813 A (FIG. 1)

In the field effect transistor shown in Patent Document 1 and FIG. 13, the short channel effect can be suppressed. However, the field effect transistor is further required to operate at a higher speed than the high speed operation obtained by suppressing the short channel effect.
SUMMARY OF THE INVENTION An object of the present invention is to provide an insulated gate field effect transistor capable of higher speed operation and a method for manufacturing the same.

Insulated gate field effect transistor according to the present invention,
The region of the semiconductor substrate in which the channel is formed, the pair of extension portions formed on the semiconductor substrate in contact with the region and spaced apart from each other, and further separated in directions away from the opposing ends of the pair of extension portions The source region and the drain region formed on the extension portion, and the semiconductor substrate on which the channel between the source region and the drain region is formed up to a position corresponding to the end portion of the extension portion. a gate electrode and gate insulating film formed on said gate insulating film, before Symbol gate electrode, said pair of extension portions, formed so as to cover the source region and the drain region, the channel is formed and the stress adjustment layer to apply stress in a region of the semiconductor substrate, the stress adjusting layer Have a, an interlayer film formed on said gate electrode side, at each end of the end portion and the drain region of the source region, the stress adjusting layer are each two in the cross-sectional view in the gate length direction It is formed so as to have an acute angle, and the covering shape of the stress adjusting layer is Z-shaped or Z-mirror character in the cross-sectional view .

A method for manufacturing an insulated gate field effect transistor according to the present invention includes:
Forming a dummy gate layer on a semiconductor substrate at a location where a channel is formed; and a pair of extension portions which are in contact with the semiconductor substrate at a location corresponding to the location where the channel is formed and are separated from each other on the semiconductor substrate A step of forming a sidewall of the silicon oxide film overlying a side wall of the dummy gate layer, and an opposite end of the pair of extension portions. forming by growing a pair of source and drain regions on said extension portion further away in the direction away from each other from the dummy gate layer, the silicon oxide film, said pair of extension portions, the source region and the so as to cover the drain region, the channel Forming a first stress control layer to apply stress in a region of the semiconductor substrate to be made, forming a first interlayer film on the upper layer of the prior SL first stress control layer, the dummy gate layer and the Removing the first stress adjusting layer and the first interlayer film on the upper portion of the silicon oxide film ; removing the dummy gate layer and the silicon oxide film ; and the dummy gate layer and the silicon oxide Forming a gate insulating film on the semiconductor substrate in the cavity formed by removing the film up to a position corresponding to an end of the extension portion; and forming a gate electrode on an upper portion of the gate insulating film When, to form forming a second stress control layer in an upper layer of at least the gate electrode, a second interlayer film on the second stress adjusting layer A step, only contains the respective steps are performed in the order described, the source region, the drain region and the step of forming the first stress adjusting layer of the gate electrode side, an end portion and the said source region At each end of the drain region, the first stress adjustment layer is formed to have two acute angles in a cross-sectional view in the gate length direction, and the covering shape of the first stress adjustment layer is Z-shaped in the cross-sectional view. Or a Z-shaped mirror letter .

Furthermore, a method for manufacturing an insulated gate field effect transistor according to the present invention includes:
After the step of forming the second stress adjustment layer, the method further includes the step of removing the second stress adjustment layer that exists in a region other than the upper portion of the gate electrode.

A method for manufacturing an insulated gate field effect transistor according to the present invention includes:
Forming a dummy gate layer on a semiconductor substrate at a location where a channel is formed; and a pair of extension portions which are in contact with the semiconductor substrate at a location corresponding to the location where the channel is formed and are separated from each other on the semiconductor substrate forming a growth, a top end of said extension portion, and the step of forming the sidewalls of the silicon oxide film so as to cover the side walls of the dummy gate layer, opposite ends of said pair of extension portions forming by growing a pair of source and drain regions on said extension portion further away in the direction away from each other from the dummy gate layer, the silicon oxide film, said pair of extension portions, the source region and the forming a first interlayer film so as to cover the drain region A step that includes the steps of removing the first interlayer film in the upper portion of the dummy gate layer and the silicon oxide film, and removing the dummy gate layer and the silicon oxide film, the dummy gate layer and Forming a gate insulating film on the semiconductor substrate in the cavity formed by removing the silicon oxide film up to a position covering the end of the extension portion; and a gate electrode on the upper portion of the gate insulating film. Forming , removing the first interlayer film left on the pair of extension portions, the source region and the drain region, the gate electrode, the pair of extension portions, the source region, and A semiconductor substrate on which the channel is formed so as to cover the drain region Forming a stress adjusting layer to apply stress to the region, seen including forming a second interlayer film, the said stress adjusting layer, wherein each step is performed in the order described, the source region, the drain The step of forming the region and the stress adjustment layer includes two each of an end portion of the source region and an end portion of the drain region on the gate electrode side, and the stress adjustment layer has two each in a sectional view in the gate length direction. It is formed so as to have an acute angle, and the covering shape of the stress adjusting layer is implemented so as to show a Z shape or a Z mirror character shape in the sectional view .

  In the insulated gate field effect transistor of the present invention, stress is applied to the channel due to the presence of the stress adjusting layer. Therefore, carrier mobility in the channel can be increased and high-speed operation of the transistor can be realized. In addition, since the stress adjusting layer is also formed in the field effect transistor manufactured by the method for manufacturing an insulated gate field effect transistor of the present invention, stress is applied to the channel. Therefore, carrier mobility in the channel can be increased and high-speed operation of the transistor can be realized.

  An embodiment of an insulated gate field effect transistor according to the present invention will be described with reference to FIG. An insulated gate field effect transistor 1 shown in FIG. 1 includes a region of a semiconductor substrate 2 where a channel is formed, and a pair of extension portions 4 (extension portions on the source electrode S side) formed in contact with the region and spaced apart from each other. And an extension portion on the drain electrode D side). The extension part 4 has a source region 5 and a drain region 6 which are further spaced apart from each other in the direction away from each other and formed higher on the extension part 4. A gate insulating film 3 and a gate electrode G are formed on the semiconductor substrate 2 on which a channel between the source region 5 and the drain region 6 is formed.

  Here, in the insulated gate field effect transistor 1 shown in FIG. 1, the surface of the extension part 4 where the source region 5 and the drain region 6 are not formed and the side surface of the gate insulating film 3 are covered with the insulating film 7 made of SiN. It has been broken. The gate insulating film 3 is composed of two layers, a lower Si oxide film 3a and an upper polycrystalline silicon film 3b, and a part of the Si oxide film 3a runs to a position over the end of the extension portion 4. .

  In the insulated gate field effect transistor 1 shown in FIG. 1, the stress adjustment layer 8 is formed so as to cover at least the region from the gate electrode G to the pair of extension portions 4. Due to the presence of the stress adjusting layer 8, a tensile strain or a compressive strain is applied to the region of the semiconductor substrate 2 where the channel is formed, and the stress is applied.

  When tensile strain or compressive strain is applied to the semiconductor substrate 2, the lattice constant of the semiconductor at that portion changes, and the band structure changes. As a result, the mobility of carriers such as electrons and holes in the region of the semiconductor substrate 2 where the channel is formed is increased, and high-speed operation of the transistor can be realized.

A method of manufacturing the insulated gate field effect transistor shown in FIG. 1 will be described with reference to FIGS.
First, the semiconductor substrate 2 made of, for example, Si is placed in a hot water vapor atmosphere, and an oxide film 9 of about 3 nm is formed on the semiconductor substrate. Next, 150 nm thick polycrystalline silicon 10 is deposited on oxide film 9 by LPCVD (Low Pressure Chemical Vapor Deposition). Then, as shown in FIG. 2a), a SiN mask 11 is formed by lithography, and the oxide film 9 and the polycrystalline silicon 10 other than the portion where the SiN mask 11 is formed are removed. Then, the polycrystalline silicon 10 and the oxide film 9 that have not been removed become a dummy gate layer, which is replaced with a gate insulating film to be formed later.

  Then, the SiN film 12 having a thickness of about 4 nm is formed on the side surfaces of the oxide film 9 and the polycrystalline silicon 10 that have not been removed in the above process under the condition of 680 to 760 ° C. by LPCVD. Then, as shown in FIG. 2b), the SiN film 12 is etched back to smooth the surface of the film.

  Thereafter, a natural oxide film (not shown) on the semiconductor substrate 2 on which the dummy gate layer is not formed is removed by DHF (diluted hydrofluoric acid), and as shown in FIG. An Si layer doped with boron (or arsenic) is epitaxially grown on the semiconductor substrate 2 to form an extension portion 4.

After the extension portion 4 is formed, the SiN film 12 is removed by hot phosphoric acid, and a 5 nm SiO ₂ film is formed on the side wall surface of the polycrystalline silicon 10 using TEOS (tetraethyl orthosilicate) as a raw material by LPCVD at 650 ° C. To do. After film formation, etch back was performed. By doing so, the SiO ₂ film 13 is formed on the side surface of the polycrystalline silicon 10 as shown in FIG.

Then, as shown in FIG. 3 b), a side wall made of the SiN film 14 / SiO ₂ deposition layer 15 is formed on the side surface of the polycrystalline silicon film 10. Here, the growth temperature of the SiN film 14 is 680 ° C., and the growth temperature of the SiO ₂ deposition layer 15 using TEOS as a raw material is 650 ° C. Further, the film thickness of the SiN film 14 / SiO ₂ deposition layer 15 is made thin to the extent that the fringe capacitance of the gate is made as small as possible and the short channel effect does not occur. In this example, the thickness of the SiN film 14 / SiO ₂ deposition layer 15 is 20 nm / 50 nm. Note that the side wall formed of the SiN film 14 / SiO ₂ deposition layer 15 becomes a side wall covering the periphery of the side surface of the dummy gate layer, and the lower SiN film 14 becomes the insulating film 7 in FIG.

Further, as described below, a process before forming the source region 5 and the drain region 6 in the extension portion 4 is performed. That is, DHF processing is performed on the exposed surface of the semiconductor substrate 2 to remove a natural oxide film (not shown). At this time, as shown in FIG. 3c), the SiO ₂ deposition layer 15 is etched by DHF to form a dent.

Then, as shown in FIG. 4 a), Si is epitaxially grown on the extension portion 4 where the SiN film 14 / SiO ₂ deposition layer 15 is not formed to form the source region 5 and the drain region 6. Here, the epitaxially grown Si runs on the bottom of the side wall made of the SiN film 14 / SiO ₂ deposition layer 15. Thereafter, in order to make the source region 5 and the drain region 6 conductive, when the field effect transistor to be formed is an n-channel MOS transistor, ion implantation of P at a concentration of 3 × 10 ¹⁵ cm ⁻³ with an acceleration voltage of 10 kV is performed. I do. On the other hand, in the case of a p-channel MOS transistor, B having a concentration of 5 × 10 ¹⁵ cm ⁻³ is performed at an acceleration voltage of 4 kV. Then, annealing is performed at a temperature of 1050 ° C. to activate the implanted ions.

Next, a pretreatment for forming a film of Co silicide or Ni silicide of the material constituting the source electrode S and the drain electrode D formed in the source region 5 and the drain region 6 is performed by DHF. When the DHF process is performed, the SiO ₂ deposition layer 15 is completely removed as shown in FIG.

  After performing the DHF treatment, a film of Co silicide or Ni silicide is formed in the source region 5 and the drain region 6 as shown in FIG. 4C), and the source electrode S and the drain electrode D are formed. When Co silicide is formed, the thickness of Co is set to 8 nm, and TiN having a thickness of 30 nm is deposited thereon to prevent Co oxidation. The deposited TiN is removed after the Co is heat-treated and silicided.

Thereafter, as shown in FIG. 5 a), an extension portion 4, a source region 5, a drain formed by forming a SiN film having a thickness of 20 nm on the semiconductor substrate 2 at a film forming temperature of 420 ° C. as the first stress adjusting layer 8. The region 6, the source electrode S, the drain electrode D, the polycrystalline silicon 10, the SiN mask 11, the SiO ₂ film 13, and the SiN film 14 are formed on the entire exposed portion. After forming the stress adjusting layer 8, as shown in FIG. 5b), the first interlayer film 16 is formed so as to fill the upper portion of the polycrystalline silicon 10 which will later become the gate. As the interlayer film 16, for example, an oxide film formed by HDP (High Density Plasma) can be used.

Then, the polycrystalline silicon 10 is removed, and the original gate insulating film 3 is formed. For this purpose, first, as shown in FIG. 5c), the interlayer film 16 and the mask of SiN 11 are etched so that the upper portion of the polycrystalline silicon 10 is exposed. Then, as shown in FIG. 6a), the polycrystalline silicon 10 is removed by dry etching. Then, the SiO ₂ film 13 formed on the side surface of the polycrystalline silicon 10 and the oxide film 9 formed on the surface of the semiconductor substrate 2 are removed by wet etching. When the polycrystalline silicon 10 and the SiO ₂ film 13 are removed in this way, the SiN film 14 (insulating film 7) is exposed on the side surface of the removed cavity. That is, the cavity becomes a recess of the interlayer film 16 whose inner wall is covered with the insulating film 7.

  Thereafter, the original gate insulating film 3 is formed. That is, as shown in FIG. 6b), first, the positions of the semiconductor substrate 2 exposed on the bottom surface of the cavity surrounded by the insulating film 7 and the end portions of the extension portion 4 are oxidized to form the Si oxide film 3a. Form. Then, a polycrystalline silicon film 3b is formed on the Si oxide film 3a by LPCVD. Thus, the gate insulating film 3 composed of the two layers of the lower Si oxide film 3a and the upper polycrystalline silicon film 3b is formed. Thereafter, CMP (Chemical Mechanical Polishing) is performed for planarization.

  Next, as shown in FIG. 6c), a Co silicide film or a Ni silicide film is formed on the surface of the polycrystalline silicon film 3b, and the gate electrode G is formed. When Co silicide is formed, the thickness of Co is set to 8 nm, and TiN having a thickness of 30 nm is deposited thereon to prevent Co oxidation. The deposited TiN is removed after the Co is heat-treated and silicided.

  After forming the gate electrode G, as shown in FIG. 7a), a SiN film 17 having a thickness of 20 nm is formed on the entire surface of the interlayer film 16 including the surface of the gate electrode G at a film formation temperature of 420 ° C. . Then, in order to leave only the SiN film 17 formed on the upper portion of the gate electrode G, a resist mask 18 is formed at a position corresponding to the upper portion of the gate electrode G.

  After the resist mask 18 is formed, the unnecessary SiN film 17 is removed by dry etching as shown in FIG. 7B). After the SiN film 17 is removed, the resist mask 18 is removed. The SiN film 17 is connected to the first stress adjustment layer 8 formed on the side wall portion of the gate insulating film 3 and the source 5 and drain regions 6 to become a second stress adjustment layer.

Finally, as shown in FIG. 7c), a second interlayer film 16 is further formed so as to cover the SiN film 17 formed on the gate electrode G. As the interlayer film 16, NSG (Non Dope Silicate Glass) can be used. In the figure, the first interlayer film and the second interlayer film are also made of the same material and are integrated with each other, so that the same reference numeral 16 is given.
Thus, the insulated gate field effect transistor shown in FIG. 1 is completed. In FIG. 7c), the first stress adjustment layer and the second stress adjustment layer are made of the same material and are integrated with each other, so that the same reference numeral 8 is given.

  In the insulated gate field effect transistor shown in FIG. 1, the SiN film 17 is formed only on the gate electrode G. However, the SiN film 17 other than the SiN film 17 formed on the gate electrode G may be left as in the insulated gate field effect transistor 1 shown in FIG. The remaining SiN film 17 becomes the second stress adjustment layer. By doing so, the process can be simplified. Note that, among the reference numerals of the insulated gate field effect transistors shown in FIG. 8, all the reference numerals of the insulated gate field effect transistors shown in FIG.

  The process of manufacturing the insulated gate field effect transistor shown in FIG. 8 is common to FIG. 7a) among the above-described manufacturing processes of the insulated gate effect transistor shown in FIG. That is, in FIG. 7 a), after forming the gate electrode G, the SiN film 17 having a thickness of 20 nm is formed on the entire surface of the interlayer film 16 including the surface thereof, and then the SiN film 17 is not etched without being etched. A second interlayer film 16 is formed on the surface. Thus, the insulated gate field effect transistor shown in FIG. 8 is completed. Since the second interlayer film formed here and the first interlayer film already formed are made of the same material, the same reference numeral 16 is given.

  The insulated gate field effect transistor having the same form as the insulated gate field effect transistor 1 shown in FIG. 1 can be manufactured by a manufacturing method different from the manufacturing method described above. Here, the steps of the manufacturing method are common to the steps of the manufacturing method of the insulated gate field effect transistor shown in FIG. 1 described with reference to FIGS. However, after forming a Co silicide or Ni silicide film in the source region 5 and the drain region 6 as shown in FIG. 4c) and forming the source electrode S and the drain electrode D, as shown in FIG. 5a). The difference is that the SiN film as the stress adjusting layer 8 is not formed.

  Instead, as shown in FIG. 9 a), after forming the source electrode S and the drain electrode D, the first portion is buried so that the upper portion of the polycrystalline silicon 10 to be replaced with the gate insulating film 3 later is also filled. The interlayer film 16 is formed. Thereafter, as shown in FIG. 9B), the interlayer film 16 is etched so that the SiN mask 11 formed on the polycrystalline silicon 10 is exposed, and then the SiN mask 11 is removed.

Then, as shown in FIG. 10a), the polycrystalline silicon 10 is removed by dry etching. Then, the SiO ₂ film 13 and the oxide film 9 formed on the side surface of the polycrystalline silicon film 10 are removed by wet etching. When the polycrystalline silicon 10 and the SiO ₂ film 13 are removed in this way, the insulating film 7 is exposed on the side wall surface of the removed cavity.

  Thereafter, the original gate insulating film 3 is formed. That is, as shown in FIG. 10B), first, the positions of the semiconductor substrate 2 exposed at the bottom surface of the cavity surrounded by the insulating film 7 and the end portions of the extension portion 4 are oxidized, and the Si oxide film 3a is formed. Form. Then, a polycrystalline silicon film 3b is formed on the Si oxide film 3a. Thus, the gate insulating film 3 composed of the two layers of the lower Si oxide film 3a and the upper polycrystalline silicon film 3b is formed. Thereafter, CMP (Chemical Mechanical Polishing) is performed for planarization.

  Next, as shown in FIG. 11a), a Co silicide film or a Ni silicide film is formed on the surface of the polycrystalline silicon film 3b to form the gate electrode G. 11B), all of the interlayer film 16 is once removed using DHF, and then a SiN film is formed on the semiconductor substrate 2 as the stress adjusting layer 8 as shown in FIG. 12A). The extension portion 4, the source region 5, the drain region 6, the source electrode S, the gate electrode G, the drain electrode D, the gate insulating film 3, and the insulating film 7 are formed on the entire exposed portion.

  After forming the stress adjusting layer 8, a second interlayer film 16 is formed as shown in FIG. 12b). Thus, the insulated gate field effect transistor shown in FIG. 1 is completed. In the figure, since the first interlayer film and the second interlayer film are also made of the same material, the same reference numeral 16 is given.

  In the insulated gate field effect transistor manufactured by some of the methods for manufacturing an insulated gate effect transistor described above, a stress adjusting layer is formed at least on the side wall portion of the gate insulating film and the source / drain region. Therefore, in such an insulated gate field effect transistor, due to the presence of the stress adjusting layer, a tensile strain or a compressive strain is applied to the region of the semiconductor substrate where the channel is formed, and the stress is applied. Therefore, the mobility of carriers such as electrons and holes in the region of the semiconductor substrate 2 where the channel is formed is increased, and high-speed operation can be realized.

  The insulated gate field effect transistor of the present invention can be applied to an n-channel MOS transistor or a p-channel MOS transistor. The method for manufacturing an insulated gate field effect transistor of the present invention can be applied to the manufacture of an n-channel MOS transistor or a p-channel MOS transistor.

1 is a cross-sectional view of an insulated gate field effect transistor according to the present invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor concerning this invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows the manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is sectional drawing of another insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows another manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows another manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows another manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is a schematic cross section which shows another manufacturing process of the insulated gate field effect transistor which concerns on this invention. It is sectional drawing of the insulated gate field effect transistor which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Insulated gate field effect transistor, 2 ... Semiconductor substrate, 3 ... Gate insulating film, 3a ... Si oxide film, 3b ... Polycrystalline silicon film, 4 ... Extension part, 5 ... Source region, 6 ... Drain region, 7 ... Insulation films, 8 ... stress adjusting layer, 9 ... oxide film, 10 ... polycrystal silicon, 11 ... SiN mask, 12 ... SiN film, 13 ... SiO ₂ film, 14 ... SiN film, 15 ... SiO ₂ deposited layer, 16 ... interlayer Film, 17 ... SiN film, 18 ... resist mask

Claims (4)

A region of the semiconductor substrate where the channel is formed;
A pair of extension portions formed on the semiconductor substrate in contact with the regions and apart from each other;
A source region and a drain region which are formed on the extension part further away from the opposing ends of the pair of extension parts in a direction away from each other;
A gate insulating film formed on the semiconductor substrate in which a channel between the source region and the drain region is formed up to a position corresponding to an end of the extension portion; and a gate electrode formed on the gate insulating film;
Before Symbol gate electrode, said pair of extension portions, the formed so as to cover the source region and the drain region, and the stress adjustment layer to apply stress in a region of the semiconductor substrate on which the channel is formed,
Have a, an interlayer film formed on said stress adjusting layer,
The stress adjusting layer is formed so as to have two acute angles in a cross-sectional view in the gate length direction at each of the end of the source region and the end of the drain region on the gate electrode side, and the stress adjusting layer Is a Z-shaped or Z mirror character in the cross-sectional view,
Insulated gate field effect transistor. Forming a dummy gate layer on a semiconductor substrate at a location where a channel is formed; and a pair of extension portions which are in contact with and separated from the semiconductor substrate at a location corresponding to the location where the channel is formed on the semiconductor substrate. Forming by growth ,
Forming a sidewall of the silicon oxide film on the end portion of the extension portion so as to cover the sidewall of the dummy gate layer;
Forming a pair of source and drain regions by growth on the extension part further away from the opposing ends of the pair of extension parts; and
A first stress adjustment layer that applies stress to a region of the semiconductor substrate on which the channel is formed so as to cover the dummy gate layer , the silicon oxide film, the pair of extension portions, the source region, and the drain region; Forming step;
Forming a first interlayer film on the upper layer of the prior SL first stress control layer,
Removing the first stress adjusting layer and the first interlayer film in the upper part of the dummy gate layer and the silicon oxide film ;
Removing the dummy gate layer and the silicon oxide film ;
Forming a gate insulating film on the semiconductor substrate in the cavity formed by removing the dummy gate layer and the silicon oxide film to a position covering an end of the extension part;
Forming a gate electrode in an upper portion of the gate insulating film;
Forming a second stress adjusting layer on at least the upper layer of the gate electrode;
Forming a second interlayer film on the second stress adjusting layer, only including,
The steps are performed in the order described,
The step of forming the source region, the drain region, and the first stress adjustment layer includes the step of forming the first stress adjustment layer at each of an end portion of the source region and an end portion of the drain region on the gate electrode side. Each of the first stress adjustment layers is formed so as to have two acute angles in a cross-sectional view in the gate length direction, and the first stress adjustment layer is formed so as to show a Z shape or a Z mirror character shape in the cross sectional view.
A method of manufacturing an insulated gate field effect transistor. After the step of forming the second stress adjustment layer, the method further includes the step of removing the second stress adjustment layer existing on the portion other than the upper portion of the gate electrode .
A method for manufacturing an insulated gate field effect transistor according to claim 2 . Forming a dummy gate layer on a semiconductor substrate at a location where a channel is formed; and a pair of extension portions which are in contact with and separated from the semiconductor substrate at a location corresponding to the location where the channel is formed on the semiconductor substrate. Forming by growth ,
Forming a sidewall of the silicon oxide film on the end portion of the extension portion so as to cover the sidewall of the dummy gate layer;
Forming by growing a pair of source and drain regions on said extension portion further away in the direction away from each other from opposite ends of said pair of extension portions,
Forming a first interlayer film so as to cover the dummy gate layer , the silicon oxide film, the pair of extension portions, the source region and the drain region;
And removing said first interlayer film in the upper portion of the dummy gate layer and the silicon oxide film,
Removing the dummy gate layer and the silicon oxide film ;
Forming a gate insulating film on the semiconductor substrate in the cavity formed by removing the dummy gate layer and the silicon oxide film to a position covering an end of the extension part;
Forming a gate electrode in an upper portion of the gate insulating film;
Removing the first interlayer film left on the pair of extension parts, the source region and the drain region;
Forming a stress adjusting layer for applying stress to a region of the semiconductor substrate on which the channel is formed so as to cover the gate electrode, the pair of extension portions, the source region, and the drain region ;
Forming a second interlayer film on the stress adjusting layer, only including,
The steps are performed in the order described,
The step of forming the source region, the drain region, and the stress adjusting layer includes the step of forming the stress adjusting layer in the gate length direction at each of the end of the source region and the end of the drain region on the gate electrode side. Each of the stress adjustment layers is formed so as to have two acute angles in a cross-sectional view, and is implemented so that the covering shape of the stress adjustment layer shows a Z shape or a Z mirror character shape in the cross sectional view.
A method of manufacturing an insulated gate field effect transistor.

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