JP4022395B2 - Semiconductor device, semiconductor wafer, and manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a semiconductor wafer, and in particular, a characteristic monitor unit that measures various characteristic values such as transistor characteristics, logic gate propagation delay time, wiring capacitance and wiring resistance, and grasps distribution and variation in the wafer surface. The present invention relates to a semiconductor device and a semiconductor wafer.
[0002]
[Prior art]
The performance of a semiconductor device such as an integrated circuit (hereinafter referred to as LSI) depends on the quality of physical and electrical characteristics of components such as integrated transistors and wiring. These characteristics are the result of physical and chemical treatments at each step of the manufacturing process, and these treatments cannot be completely uniform across the entire surface of the wafer. The cause is a temperature gradient, a difference in exposure characteristics between the wafer central portion and the peripheral portion, and the like. As a result, the characteristic values of the constituent elements of the LSI have a distribution or variation in the wafer surface. By managing and controlling each process of the normal manufacturing process, such distribution or variation is within the standard range for realizing the target performance of the LSI. However, it cannot be completely avoided that the distribution and variation deviate from the standard range due to various factors. In such a case, it is necessary to specify the process that causes the distribution. The distribution of the characteristic values of the constituent elements within the wafer surface or the variation itself is important information for identifying the cause process.
[0003]
Conventionally, as a technique for analyzing the distribution or variation of such characteristic values in the wafer surface, a technique using Fourier analysis or wavelet analysis such as image processing has been reported. For example, “February 1997, IEE Transactions on Semiconductor Manufacturing, Volume 10, Number 1 (IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL.10, NO.1, FEBRUARY 1997) ”Pages 24 to 40.
[0004]
In such a method, the low frequency component of the spatial frequency is regarded as the tendency of the distribution of characteristic values over the entire wafer surface, while the high frequency component is referred to as a component in which the characteristic values of individual elements vary randomly, signal processing. However, it can be understood as a component corresponding to white noise. From the distribution indicated by the low-frequency component, it is possible to estimate the causal process of the manufacturing process causing it.
[0005]
[Problems to be solved by the invention]
The above method is based on the premise that the elements are uniformly arranged in the wafer surface. This corresponds to the fact that an image in image processing is configured as a two-dimensional array having pixel values sampled at a constant sampling interval as elements. It is necessary that the elements are arranged at equal intervals in at least the horizontal direction and the vertical direction.
[0006]
Such a wafer can be created as a dedicated chip at the time of manufacturing process development and put into the manufacturing process line, but it is difficult to put it in terms of cost and management in mass production. Become. In the above reference, a dedicated chip is created to obtain necessary data.
[0007]
However, the increase in mask manufacturing cost due to the recent process miniaturization and multilayering is remarkable, and such a mask for obtaining wafer in-plane distribution or variation is different from other test element group masks required for process development. Separate creation has become difficult to implement even during manufacturing process development.
[0008]
Mounting a few test transistors, etc. in a chip has been conventionally performed in a product chip, but for a technique applying the image processing described above, the number of data per unit area, that is, the data density Is insufficient in that it is small. As long as it is limited to a certain area in the chip, it is possible to arrange a large number of elements to some extent.
[0009]
The main object of the present invention is to provide a characteristic monitor unit capable of realizing a sufficient number and uniform sampling interval for analyzing the in-wafer distribution or variation of element characteristics due to the manufacturing process even when manufacturing a product chip. A semiconductor device and a semiconductor wafer are provided.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention has a first arrangement in the state of a wafer in which semiconductor chips in which a desired functional circuit is built are arranged in a matrix through a predetermined cutting region. When the direction is the X direction, the second direction orthogonal to the X direction is the Y direction, and the unit pitches of the X-direction and Y-direction arrays of the chips in the wafer state are Lx and Ly, respectively,
The chips are all the same Nx pieces (provided that Nx is arranged on a straight line parallel to the X direction at a predetermined position of the chip at equal intervals px (px and Lx are units of the same length)) Is a positive integer) first characteristic monitor unit, and is arranged on a straight line parallel to the Y direction at a predetermined position of the chip at equal intervals py (where py and Ly are the same length unit) All of the same Ny (where Ny is a positive integer) second characteristic monitor unit,
Further, the above-described chip that satisfies Lx = Nx × px and Ly = Ny × py is included. At this time, the first characteristic monitor unit and the second characteristic monitor unit may have the same configuration.
[0011]
Also, the first and second characteristic monitor sections are all n-channel field effect transistors, p-channel field effect transistors, logic gate propagation delay time measurement circuits, or wiring elements including resistance elements and capacitance elements. Can do.
[0012]
Further, in the semiconductor wafer of the present invention, semiconductor chips in which a desired functional circuit is formed are arranged in a matrix through a predetermined cutting region, and the first direction of the arrangement is an X direction, When the second direction orthogonal to the Y direction is the Y direction, and the unit pitches of the X direction and Y direction arrays of the chips are Lx and Ly, respectively,
A first characteristic monitor unit arranged in a matrix on an X-direction cutting region parallel to the X direction with the arrangement pitches in the X direction and the Y direction being px and Ly, respectively, and the arrangement in the X direction and the Y direction A second characteristic monitor unit having a pitch of Lx and py and arranged in a matrix on a Y direction cutting region parallel to the Y direction,
In addition, the number of the first characteristic monitor units arranged per unit pitch Lx in the X direction is Nx (where Nx is a positive integer), and the number of the second characteristic monitor units arranged per unit pitch Ly in the Y direction. Is Ny (where Ny is a positive integer)
Lx = Nx × px and Ly = Ny × py are satisfied.
[0013]
In another semiconductor wafer of the present invention, semiconductor chips in which a desired functional circuit is formed are arranged in a matrix through a predetermined cutting region, and the first direction of the arrangement is an X direction, When the second direction orthogonal to the direction is the Y direction, and the arrangement pitch of the chip in the X direction and the Y direction is Lx and Ly, respectively,
A first characteristic monitor unit arranged in a matrix on an X-direction cutting region parallel to the X direction with the arrangement pitches in the X direction and the Y direction being px and Ly, respectively, and the Y at a predetermined position on the chip Ny (where Ny is a positive integer) all the same second characteristic monitor units arranged at equal intervals py on a straight line parallel to the direction,
Further, when the number of the first characteristic monitor units arranged per unit pitch Lx in the X direction is Nx (where Nx is a positive integer), Lx = Nx × px and Ly = Ny × py are satisfied. It is characterized by that.
[0014]
Further, according to still another semiconductor wafer of the present invention, semiconductor chips in which a desired functional circuit is formed are arranged in a matrix through a predetermined cutting region, and the first direction of the arrangement is set as an X direction, When the second direction orthogonal to the X direction is the Y direction, and the arrangement pitches of the chip in the X direction and the Y direction are Lx and Ly, respectively,
Nx (where Nx is a positive integer) all the same first characteristic monitor units arranged at equal intervals px on a straight line parallel to the X direction at a predetermined position on the chip, and the X A second characteristic monitor unit arranged in a matrix on a Y-direction cutting region parallel to the Y direction with the arrangement pitch in the direction and the Y direction being Lx and py,
In addition, when the number of the second characteristic monitor units arranged per unit pitch Ly in the Y direction is Ny (where Ny is a positive integer), Lx = Nx × px and Ly = Ny × py are satisfied. It is characterized by that.
[0015]
In each of the semiconductor wafers, the first characteristic monitor unit and the second characteristic monitor unit can have the same configuration.
[0016]
Also, the first and second characteristic monitor sections are all n-channel field effect transistors, p-channel field effect transistors, logic gate propagation delay time measurement circuits, or wiring elements including resistance elements and capacitance elements. Can do.
[0017]
Further, the first characteristic monitor unit and the second characteristic monitor unit may all be arranged at a position excluding an intersection of the X direction cut region and the Y direction cut region.
[0018]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which semiconductor chips having desired functional circuits are arranged in a matrix through predetermined cutting regions and have a first and second characteristic monitor unit. Comprising the steps of:
When the first direction of the array is the X direction, the second direction orthogonal to the X direction is the Y direction, and the unit pitch of the array of the chips in the X direction and the Y direction is Lx and Ly, respectively ,
The first characteristic monitor unit is arranged in a matrix on a straight line parallel to the X direction when the arrangement pitch in the X direction and the Y direction is px and Ly, respectively.
The second characteristic monitor unit is arranged in a matrix on a straight line parallel to the Y direction with the arrangement pitches in the X direction and the Y direction being Lx and py, respectively.
In addition, the number of the first characteristic monitor units arranged per unit pitch Lx in the X direction is Nx (where Nx is a positive integer), and the number of the second characteristic monitor units arranged per unit pitch Ly in the Y direction. Is Ny (where Ny is a positive integer)
Lx = Nx × px and Ly = Ny × py are satisfied.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
In order to clarify the above objects, features, and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the units such as pitch, interval, distance, width, and length are all common (here, μm unit).
[0020]
FIG. 1 is a diagram for explaining the semiconductor device according to the first embodiment of the present invention, and is a schematic plan view of a chip showing an example of an arrangement of a characteristic monitor unit. FIG. 2 is a plan view schematically showing a state in which the chips are arranged in a matrix on the semiconductor wafer before being individually separated, and FIG. 1 is an enlarged view of a portion A in FIG. . Hereinafter, a description will be given with reference to FIGS.
[0021]
The chip 10 included in the semiconductor device of the present embodiment includes Nx first characteristic monitor units arranged at a constant interval px on a straight line parallel to X-direction sides (hereinafter simply referred to as X sides) 7a and 7b. 12 and Ny second characteristic monitor units 14 arranged at a constant interval py on a straight line parallel to Y-direction sides (hereinafter simply referred to as Y sides) 6a and 6b. (However, Nx and Ny are both integers of 1 or more, and at least one is preferably 2 or more. In the example of FIG. 1, Nx = 5 and Ny = 4). Assuming that the arrangement pitches of the upper chip 10 in the X direction and the Y direction are Lx and Ly, respectively, Nx × px = Lx and Ny × py = Ly. Therefore, the first characteristic monitor unit 12 is arranged over the entire surface of the wafer 1 with the arrangement pitches in the X direction and Y direction being px and Ly, respectively. Similarly, the second characteristic monitor unit 14 is arranged over the entire surface of the wafer 1 with the arrangement pitches in the X and Y directions being Lx and py, respectively.
[0022]
Here, a condition in which Nx first characteristic monitoring units 12 and Ny second characteristic monitoring units 14 are all arranged in the effective area of the chip 10 will be described.
[0023]
First, the first characteristic monitor unit 12 is formed in rectangular regions with lengths in the X direction and Y direction of dx1 and dy1, respectively, and the second characteristic monitor unit 14 has lengths in the X direction and Y direction of dx2 respectively. , Dy2 is formed in the rectangular area. In addition, the effective lengths of the X side and the Y side that determine the effective area that is surely left after the chips 10 are individually separated are Lxe and Lye, respectively, and the widths of the X-direction cutting area 5x and the Y-direction cutting area 5y are set as the widths. If both are Ws, then Lx = Lxe + Ws and Ly = Lye + Ws. Further, the distance between the X side 7a and the Y side 6b adjacent to the center of the first characteristic monitor unit 12y disposed in the effective area of the chip 10 and closest to the Y side 6b, for example, is Y1 and X1, respectively. When the distance between the center of the second characteristic monitor unit 12x closest to the X side 7b and the adjacent X side 7b and Y side 6a is Y2 and X2, respectively.
(Nx−1) × px + dx1 ≦ Lxe = Lx−Ws (1)
dx1 ≦ 2 × X1 (2)
dy1 ≦ 2 × Y1 (3)
(Ny-1) × py + dy2 ≦ Lye = Ly−Ws
dx2 ≦ 2 × X2
dy2 ≦ 2 × Y2
If all of the above are satisfied, all of the Nx first characteristic monitor units 12 and the Ny second characteristic monitor units 14 can be formed in the effective area of the chip 10.
[0024]
FIG. 3 is a plan view schematically showing the arrangement of the first and second characteristic monitor units 12 and 14 on the wafer 1 in which the chips 10 are arranged in a matrix. As can be seen from FIG. 3, the area occupied by the first and second characteristic monitor units 12 and 14 is very small even when viewed in the chip 10 or the entire surface of the wafer 1. In the case of a dedicated chip created for conventional test measurement, this is a major difference from the fact that the characteristic monitor unit can be arranged so as to be two-dimensionally filled in the wafer surface. When such a dedicated chip is used, when analyzing the characteristic value of the element, the distribution in the wafer surface and the like can be acquired by applying a two-dimensional Fourier transform, wavelet transform or the like.
[0025]
On the other hand, in the wafer 1 on which the chips 10 of this embodiment are arranged, the characteristic value group acquired from the first characteristic monitor unit 12 in the first characteristic monitor unit arrangement region 210 in FIG. 3 and the second characteristic monitor unit arrangement region 220. A one-dimensional Fourier transform or wavelet transform is applied to the characteristic value group acquired from the second characteristic monitor unit 14.
[0026]
In either case of one dimension or two dimensions, a low frequency component, that is, a component that changes relatively slowly over the entire surface of the wafer is regarded as a distribution in the wafer surface, and a high frequency equivalent to white noise in terms of signal processing. The component is regarded as a component in which the characteristic value of the element varies randomly.
[0027]
In the case of data acquisition by the chip 10 of the present embodiment, the region where the distribution of the element characteristic values in the wafer plane cannot be analyzed is larger than that in the case of the dedicated chip, but the distribution in the wafer plane is a low frequency component. Therefore, a non-analyzable area of about chip size existing between each of the first characteristic monitor unit arrangement region 210 and the second characteristic monitor unit arrangement region 220 as shown in FIG. It will not be a major obstacle.
[0028]
Further, since the random variation component does not depend on the position in the wafer surface, statistical properties such as standard deviation are obtained from the characteristic value group acquired from the first characteristic monitor unit arrangement region 210 and the second characteristic monitor unit arrangement region 220. Can be grasped.
[0029]
Furthermore, it is considered that the wafer in-plane distribution includes some periodicity with the exposure unit size at the time of exposure as the basic period, but the periodicity should also have horizontal and vertical components, From the respective characteristic value groups acquired from the first and second characteristic monitor units 12 and 14 in the first characteristic monitor unit arrangement area 210 and the second characteristic monitor unit arrangement area 220, the horizontal periodicity and the vertical direction respectively. Can be confirmed.
[0030]
From the above, by arranging the first and second characteristic monitor units 12 and 14 as in the chip 10 of this embodiment, it is necessary to grasp the in-wafer distribution or random variation even in the case of a product chip. It becomes possible to acquire a characteristic value group of a simple element.
[0031]
If the first characteristic monitor unit 12 and the second characteristic monitor unit 14 are arranged so as not to overlap each other as in the example of FIG. 1, the first and second characteristic monitor units 12 and 14 may have the same configuration. There is no problem with different configurations. In addition, if the first and second characteristic monitor units 12 and 14 have the same configuration, one characteristic monitor unit arrangement region can be shared. FIG. 4 is an example of a schematic plan view when one characteristic monitor unit arrangement region is shared by the first and second characteristic monitor units. Referring to FIG. 4, the chip 20 includes a common characteristic monitor unit 25, a first characteristic monitor unit 26, and a second characteristic monitor unit 27, all of which are characteristic monitor units having the same configuration. The common characteristic monitor unit 25 is located at the intersection of a virtual X direction straight line in which the first characteristic monitor unit 26 is arranged and a virtual Y direction straight line in which the second characteristic monitor unit 27 is arranged, and The center-to-center distances between the adjacent first characteristic monitor unit 26 and second characteristic monitor unit 27 are px and py, respectively. By arranging in this way, the arrangement area of the characteristic monitor unit can be saved.
[0032]
Next, a specific example of the first embodiment will be described below. FIG. 5 is a diagram for explaining this specific example. As an example, an n-channel field effect transistor (hereinafter referred to as NMOS) is used as the first characteristic monitor unit 12, and a main part related to the description of the horizontal arrangement. It is a top view which shows typically. FIG. 6 is a diagram schematically showing the details of the NMOS electrode assignment. In FIG. 6, a wiring connecting the gate electrode 250 and the gate electrode pad 254, a wiring connecting the source region 251 and the source electrode pad 255, a wiring connecting the drain region 252 and the drain electrode pad 256, and an NMOS are formed. Illustration of the well and the wiring connecting the well and the well electrode pad 253 is omitted.
[0033]
The arrangement pitch Lx of the chips 10 in the X direction is 10000 μm, the widths dx1 and dy1 of the first characteristic monitor unit 12 are 125 μm and 100 μm, respectively, the arrangement interval px of the first characteristic monitor unit 12 is 250 μm, and X1 and Y1 are 75 μm and 60 μm, respectively. The width Ws of the cutting region is assumed to be 100 μm. Therefore, Nx = Lx / px = 10000/250 = 40. Moreover, all the expressions (1) to (3) are also satisfied. In addition, the first characteristic monitor unit 12 of this example is disposed on the side edge region between the external connection electrode 8 and the X-direction cutting region 5x in contact with the chip 10 on the chip 10. If Nx is relatively small, px can be widened accordingly. In this case, different types of characteristic monitor units can be arranged between the first characteristic monitor units 12.
[0034]
Next, a semiconductor wafer according to a second embodiment of the present invention will be described. FIG. 7 is a schematic plan view of the semiconductor wafer of the present embodiment, and FIG. 8 is a schematic plan view in which a portion B in FIG. 5 is enlarged. In the first embodiment, the first characteristic monitor unit and the second characteristic monitor unit are all disposed in the effective area that remains reliably after the chips 10 are individually separated. In the present embodiment, on the contrary, The one characteristic monitor unit and the second characteristic monitor unit are all arranged in the cutting region.
[0035]
7 and 8, in the semiconductor wafer 3 of the present embodiment, the chip 30 on which various elements and wirings for realizing a desired function are formed is interposed via the X-direction cutting region 5x and the Y-direction cutting region 5y. The arrangement in a matrix is the same as that of the semiconductor wafer 1 of the first embodiment. However, the first characteristic monitor unit 32 is arranged in the X direction cutting region 5x with the X direction pitch px and the Y direction pitch Ly. Further, the second characteristic monitor unit 34 is different from the semiconductor wafer 1 in that the Y-direction cutting region 5y is arranged in a matrix over the entire surface of the semiconductor wafer 3 with the X-direction pitch Lx and the Y-direction pitch py. . Also in this embodiment, the arrangement pitches of the chips 30 in the X direction and the Y direction are Lx and Ly, respectively, and the Nx first characteristic monitor unit arrangement regions 213 and the Ny second characteristic monitor unit arrangement regions 223 are arranged. As described above, assuming that the number of the first characteristic monitor unit 32 per Lx is Nx and the number of the second characteristic monitor unit 34 per Ly is Ny, Nx × px = Lx and Ny × py = Ly. .
[0036]
Further, the first characteristic monitor unit 32 and the second characteristic monitor unit 34 of the present embodiment are also long in the X direction and the Y direction, similarly to the first characteristic monitor unit 12 and the second characteristic monitor unit 14 of the first embodiment. Are respectively formed in rectangular regions of dx1 and dy1, and lengths of Xx and Y directions are respectively in rectangular regions of dx2 and dy2, and the widths of the X-direction cutting region 5x and the Y-direction cutting region 5y are respectively formed. When both are Ws, dy1 <Ws and dx2 <Ws are satisfied, and (px−dx1) ≧ Ws or (py−dy2) ≧ Ws is satisfied. The first characteristic monitor unit 32 and the second characteristic monitor unit 34 can be arranged so that they do not overlap even at the intersection of the X direction cut region 5x and the Y direction cut region 5y. In addition, since monitor patterns for other purposes are often arranged at the intersections between the X-direction cut area 5x and the Y-direction cut area 5y, both the first characteristic monitor section 32 and the second characteristic monitor section 34 In order to avoid the intersection, it is only necessary to satisfy (px−dx1) ≧ Ws and (py−dy2) ≧ Ws.
[0037]
Also in the present embodiment, when the first characteristic monitor unit 32 and the second characteristic monitor unit 34 have the same configuration, a common characteristic monitor unit is arranged at the intersection of the X-direction cut region 5x and the Y-direction cut region 5y. As in the case of the first embodiment, the distance between the centers of the adjacent first characteristic monitor unit 32 and the second characteristic monitor unit 34 may be set to px and py, respectively. Detailed illustration and description are omitted. Further, in this case, there is a restriction that it is necessary to satisfy all of dx1 <Ws, dy1 <Ws, dx2 <Ws, and dy2 <Ws.
[0038]
Also in the semiconductor wafer 3 of the present embodiment, as in the case of the wafer 1 in which the chips 10 of the first embodiment are arranged, the characteristic value group acquired from the first characteristic monitor unit 32 in the X-direction cutting region 5x, and Y By applying a one-dimensional Fourier transform or wavelet transform to the characteristic value group acquired from the second characteristic monitor unit 34 in the direction cut region 5y, the distribution in the wafer plane can be analyzed. Also in this embodiment, even if the region where the distribution of element characteristic values in the wafer plane cannot be analyzed is larger than that in the case of the dedicated chip, the distribution in the wafer plane is a low-frequency component, so the analysis is about the chip size. As in the case of the first embodiment, the impossible area does not become a major obstacle in grasping the distribution in the wafer surface.
[0039]
As described above, the semiconductor wafer 3 according to the present embodiment completes the wafer processing by arranging the first and second characteristic monitor units 32 and 34 in the X direction cutting region and the Y direction cutting region at a predetermined pitch, respectively. Later, by measuring and obtaining desired characteristics of the first and second characteristic monitor units, the distribution within the wafer surface or the surface of the product chip can be obtained without providing a characteristic monitor unit that is not directly related to the realization of the product function. It becomes possible to acquire a characteristic value group of elements necessary for grasping random variations.
[0040]
Needless to say, the present invention is not limited to the description of the above embodiment, and can be changed within the scope of the gist thereof. For example, the first embodiment and the second embodiment are combined, the first characteristic monitor unit is arranged in the effective area of the chip, and the second characteristic monitor unit is arranged in the Y-direction cut area, or vice versa. Even if the first characteristic monitor unit is arranged in the X-direction cutting region and the second characteristic monitor unit is arranged in the effective region of the chip, the distribution of the element characteristic values in the wafer plane is similar to the case of the above embodiment. It is clear that it can be grasped.
[0041]
The first characteristic monitor unit and the second characteristic monitor unit are not limited to the NMOS of the above specific example, but a p-channel field effect transistor, a logic gate propagation delay time measurement circuit, or a wiring element including a resistance element and a capacitance element. It is also possible to include a combination of these.
[0042]
【The invention's effect】
As described above, according to the semiconductor chip and the semiconductor wafer of the present invention, without producing a monitor-dedicated chip during the manufacturing process of the product chip, the distribution or variation of the characteristic values of the elements in the wafer surface can be achieved. Data sets of characteristic values that can be easily analyzed by signal processing techniques such as Fourier analysis and wavelet analysis can be acquired, so that fluctuations in the manufacturing process can be monitored to stabilize the product yield. The effect that can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a semiconductor device according to a first embodiment of the present invention, and is a schematic plan view of a chip showing an example of an arrangement of a characteristic monitor unit.
FIG. 2 is a plan view schematically showing a state in which the chips of FIG. 1 are arranged in a matrix on a semiconductor wafer before being individually separated;
FIG. 3 is a plan view schematically showing a state of arrangement of first and second characteristic monitor units in a wafer in which chips of the first embodiment are arranged in a matrix.
FIG. 4 is an example of a schematic plan view when one characteristic monitor unit arrangement region is shared by the first and second characteristic monitor units.
FIG. 5 is a diagram for explaining a specific example of the first embodiment. FIG. 5 is a plan view schematically showing a main part related to the description of the arrangement in the horizontal direction, using NMOS as an example of the first characteristic monitor unit. is there.
6 is a diagram schematically showing the details of the electrode assignment of the NMOS of FIG. 5. FIG.
FIG. 7 is a schematic plan view of a semiconductor wafer according to a second embodiment of the present invention.
FIG. 8 is a schematic plan view enlarging a part B of FIG. 5;
[Explanation of symbols]
1,3 Wafer 5x, 5y Cutting area
6a, 6b Y side
7a, 7b X side 8 External connection electrodes 10, 20, 30 Chips 12, 12_1a, 12_a, 12_a1, 12y, 26, 32 First characteristic monitor unit 14, 14_a, 14_a1, 14x, 27, 34 Second characteristic monitor unit 25 Common characteristic monitor unit 213 Nx first characteristic monitor unit arrangement region 223 Ny second characteristic monitor unit arrangement region 250 Gate electrode 251 Source region 252 Drain region 253 Well electrode pad 254 Gate electrode pad 255 Source electrode pad 256 Drain electrode pad

Claims (16)

A first direction of the arrangement when the semiconductor chips in which a desired functional circuit is built is arranged in a matrix through a predetermined cutting region is defined as an X direction, and a second direction orthogonal to the X direction. Is the Y direction, and when the unit pitches of the X-direction and Y-direction arrays of the chips in the wafer state are Lx and Ly, respectively, the chip is parallel to the X direction at a predetermined position of the chip. All the same Nx (where Nx is a positive integer) first characteristic monitor units arranged at equal intervals px (where px and Lx are the same length unit) on a straight line, All the same Ny pieces (where Ny is a positive integer) arranged at equal intervals py (where py and Ly are units of the same length) on a straight line parallel to the Y direction at a predetermined position of the chip a second characteristic monitor unit, further, at least one of Nx and Ny is 2 or more integer A is a semiconductor device which comprises the tip which satisfies Lx = Nx × px, Ly = Ny × py, a. The semiconductor device according to claim 1, wherein the first characteristic monitor unit and the second characteristic monitor unit have the same configuration. The semiconductor device according to claim 1, wherein each of the first and second characteristic monitor units is an n-channel field effect transistor. The semiconductor device according to claim 1, wherein each of the first and second characteristic monitor units is a p-channel field effect transistor. The semiconductor device according to claim 1, wherein each of the first and second characteristic monitoring units is a logic gate propagation delay time measuring circuit. The semiconductor device according to claim 1, wherein each of the first and second characteristic monitor units is a wiring element. A semiconductor wafer in which a semiconductor chip in which a desired functional circuit is built is arranged in a matrix through a predetermined cutting region, and a first direction of the arrangement is defined as an X direction, and a first orthogonal to the X direction. 2 is the Y direction, and the unit pitches of the chips in the X direction and the Y direction are Lx and Ly, respectively, the arrangement pitches in the X direction and the Y direction are px (where px and Lx is a unit of the same length), and the first characteristic monitor unit arranged in a matrix on the X direction cutting region parallel to the X direction at Ly, and the arrangement pitches in the X direction and the Y direction are respectively Lx, py (where py and Ly are units of the same length) and a second characteristic monitor unit arranged in a matrix on a Y-direction cutting region parallel to the Y direction, and 1 unit monitor in the X direction of the characteristic monitor The number of arrangement per Lx is Nx (where Nx is a positive integer), and the number of arrangement per unit pitch Ly in the Y direction of the second characteristic monitor unit is Ny (where Ny is a positive integer). A semiconductor wafer characterized in that at least one of Nx and Ny is an integer of 2 or more and satisfies Lx = Nx × px and Ly = Ny × py. A semiconductor wafer in which a semiconductor chip in which a desired functional circuit is built is arranged in a matrix through a predetermined cutting region, and a first direction of the arrangement is defined as an X direction, and a first orthogonal to the X direction. 2 is the Y direction, and the arrangement pitch of the chip in the X direction and the Y direction is Lx and Ly, respectively, the arrangement pitches in the X direction and the Y direction are px (where px and Lx are A first characteristic monitor unit arranged in a matrix on an X-direction cutting region parallel to the X direction at Ly, and a straight line parallel to the Y direction at a predetermined position on the chip Ny (where Ny is a positive integer) all the same second characteristic monitor units arranged at equal intervals py (where py and Ly are units of the same length), The unit pitch in the X direction of the first characteristic monitor unit When the number of arrangements per Lx is Nx (where Nx is a positive integer), at least one of Nx and Ny is an integer of 2 or more, and Lx = Nx × px, Ly = Ny × py, A semiconductor wafer characterized by satisfaction. A semiconductor wafer in which a semiconductor chip in which a desired functional circuit is built is arranged in a matrix through a predetermined cutting region, and a first direction of the arrangement is defined as an X direction, and a first orthogonal to the X direction. 2 is the Y direction, and the arrangement pitches of the chip in the X direction and the Y direction are Lx and Ly, respectively, on a straight line parallel to the X direction at a predetermined position px ( However, Nx (where Nx is a positive integer) all the same first characteristic monitor units arranged in the same length unit) and the X direction and the Y direction The second characteristic monitor unit is arranged in a matrix on the Y-direction cutting region parallel to the Y direction with the arrangement pitches of Lx and py (where py and Ly are units of the same length), The unit pitch in the Y direction of the second characteristic monitor unit When the number of arrangements per Ly is Ny (where Ny is a positive integer), at least one of Nx and Ny is an integer of 2 or more, and Lx = Nx × px, Ly = Ny × py, A semiconductor wafer characterized by satisfaction. The semiconductor wafer according to claim 7, wherein the first characteristic monitor unit and the second characteristic monitor unit have the same configuration. 10. The semiconductor wafer according to claim 7, wherein each of the first and second characteristic monitor units is an n-channel field effect transistor. 10. The semiconductor wafer according to claim 7, wherein each of the first and second characteristic monitor units is a p-channel field effect transistor. The semiconductor wafer according to claim 7, wherein each of the first and second characteristic monitor units is a logic gate propagation delay time measurement circuit. The semiconductor wafer according to claim 7, wherein each of the first and second characteristic monitor units is a wiring element. 15. The semiconductor according to claim 7, wherein the first characteristic monitor unit and the second characteristic monitor unit are all disposed at a position excluding an intersection of the X direction cut region and the Y direction cut region. Wafer. A step of forming a semiconductor wafer having a first characteristic monitor unit and a second characteristic monitor unit, wherein the semiconductor chips in which a desired functional circuit is formed are arranged in a matrix through a predetermined cutting region, When the first direction of the chip is the X direction, the second direction orthogonal to the X direction is the Y direction, and the unit pitch of the arrangement of the chip in the X direction and the Y direction is Lx and Ly, respectively, In the first characteristic monitor unit, the arrangement pitch in the X direction and the Y direction is px (where px and Lx are units of the same length), and Ly is in a matrix on a straight line parallel to the X direction. The second characteristic monitor unit is arranged on a straight line parallel to the Y direction when the arrangement pitches in the X direction and the Y direction are Lx and py (where py and Ly are units of the same length), respectively. Arranged in a matrix In addition, the number of the first characteristic monitor units arranged per unit pitch Lx in the X direction is Nx (where Nx is a positive integer), and the number of the second characteristic monitor units arranged per unit pitch Ly in the Y direction. the Ny-number (where, Ny is a positive integer) when the, at least one of Nx and Ny is a integer of 2 or more, characterized by satisfying Lx = Nx × px, Ly = Ny × py, the A method for manufacturing a semiconductor device.

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