JP4015411B2 - 演算装置及びその演算装置を用いた情報処理装置 - Google Patents
演算装置及びその演算装置を用いた情報処理装置 Download PDFInfo
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- JP4015411B2 JP4015411B2 JP2001379549A JP2001379549A JP4015411B2 JP 4015411 B2 JP4015411 B2 JP 4015411B2 JP 2001379549 A JP2001379549 A JP 2001379549A JP 2001379549 A JP2001379549 A JP 2001379549A JP 4015411 B2 JP4015411 B2 JP 4015411B2
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- 230000010365 information processing Effects 0.000 title claims description 4
- 238000004364 calculation method Methods 0.000 claims description 36
- 230000001629 suppression Effects 0.000 claims description 13
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- 238000000034 method Methods 0.000 description 31
- 238000010586 diagram Methods 0.000 description 21
- 238000001514 detection method Methods 0.000 description 12
- 230000008901 benefit Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
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- 230000005764 inhibitory process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001379549A JP4015411B2 (ja) | 2001-12-13 | 2001-12-13 | 演算装置及びその演算装置を用いた情報処理装置 |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001379549A JP4015411B2 (ja) | 2001-12-13 | 2001-12-13 | 演算装置及びその演算装置を用いた情報処理装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003177911A JP2003177911A (ja) | 2003-06-27 |
| JP2003177911A5 JP2003177911A5 (enExample) | 2005-07-28 |
| JP4015411B2 true JP4015411B2 (ja) | 2007-11-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2001379549A Expired - Fee Related JP4015411B2 (ja) | 2001-12-13 | 2001-12-13 | 演算装置及びその演算装置を用いた情報処理装置 |
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| JP (1) | JP4015411B2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2005327979A1 (en) | 2004-06-18 | 2006-08-31 | The Trustees Of The University Of Pennsylvania | Optical circuits and circuit elements and methods of forming same |
| JP2009187075A (ja) * | 2008-02-04 | 2009-08-20 | Japan Radio Co Ltd | デジタル回路 |
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| JP2003177911A (ja) | 2003-06-27 |
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