JP4014449B2 - Circuit equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention has a built-in bridge circuit.Circuit equipmentIt is about.
[0002]
[Prior art]
  2. Description of the Related Art Conventionally, a circuit device set in an electronic device is used in a mobile phone, a portable computer, and the like. For example, a semiconductor device as an example of a circuit device will be described. As a general semiconductor device, there is a package type semiconductor device sealed by a conventional transfer mold. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.
[0003]
  In the package type semiconductor device 61, the semiconductor chip 62 is covered with a resin layer 63, and external connection lead terminals 64 are led out from the resin layer 63. However, in the package type semiconductor device 61, the lead terminal 64 protrudes from the resin layer 63.
[0004]
  Referring to FIG. 11, an H bridge circuit is an example of a circuit composed of package type semiconductor device 61 and the like. This H-bridge circuit is also used as a circuit that converts an analog signal from a digital signal and drives a speaker to generate sound, and is required to be small and thin. A configuration of an H bridge circuit having four transistors will be described with reference to FIG.
[0005]
  In this H bridge, four transistors TR1, TR2, TR3, and TR4 are connected in a bridge shape, and outputs are taken out from the connection point between TR1 and TR3 and the connection point between TR2 and TR4. A load is provided between the outputs. Further, power is supplied from the connection point between TR1 and TR2, and GND is provided at the connection point between TR3 and TR4.
[0006]
  An operation example of the H bridge circuit configured as described above will be described. Pulse signals are applied to the gate electrodes G1, G2, G3 and G4 of TR1, TR2, TR3 and TR4. Since the pulse signals applied to G1 and G4 are synchronized, TR1 and TR4 perform an ON-OFF operation at the same timing. Further, since the pulse signals applied to G2 and G3 are synchronized, TR2 and TR3 perform an ON-OFF operation at the same timing. Furthermore, the timing when TR1 and TR4 are turned on is different from the timing when TR2 and TR3 are turned on. When TR1 and TR4 are in the ON state, the current supplied from Vdd flows in the order of Vdd → TR1 → load → TR4 → GND. When TR2 and TR3 are in the ON state, the current supplied from Vdd flows in the order of Vdd → TR2 → load → TR3 → GND.
[0007]
  Various loads can be adopted as the above-described load. For example, a low-pass filter composed of a coil and a capacitor can be adopted as this load. In this case, a carrier signal obtained by PWM modulating the audio signal is added to G1 to G4. Then, the amplified audio signal is output to the speaker by removing the carrier signal with the low-pass filter connected to the load.
[0008]
  With reference to FIG. 12, the case where a bridge circuit is comprised by the package type semiconductor device 61 is demonstrated. The configuration of the H-bridge circuit has been realized by mounting a package type semiconductor device 61 in which semiconductor chips are individually molded on a printed circuit board PS. This figure is a perspective view of the package type semiconductor device 61 described above. The semiconductor chip 62 is on the island of the lead 61A with the drain electrode on the bottom surface.
The gate electrode and the source electrode were connected to the lead 64B or 64C through the fine metal wire 65. Further, the package type semiconductor device 61 is mounted on the mounting substrate PS through the leads 64A to 64C. Therefore, the semiconductor chip 62 is electrically and thermally coupled to the mounting substrate PS via the fine metal wires 65 and the leads 64.
[0009]
[Problems to be solved by the invention]
  However, the semiconductor device as described above has the following problems.
[0010]
  First, as shown in FIG. 10, the semiconductor elements TR1 to TR4 constituting the bridge circuit are individually supplied as package products, and are fixed to the substrate via leads led out from the package. Further, since the semiconductor elements TR1 to TR4 constituting the bridge circuit perform switching at a high frequency, a large amount of heat is generated. The heat generated from the semiconductor elements TR1 to TR4 is mainly discharged to the outside through the leads, but there is a problem that heat dissipation by the leads is not sufficient.
[0011]
  Secondly, the semiconductor elements TR1 to TR4 and the conductive path on the mounting substrate are electrically connected via the fine metal wires and the leads, and the distance between the elements is long. For this reason, there has been a problem that a lot of secondary noise is generated due to the high-frequency current flowing in the parasitic inductance due to the conductive path.
[0012]
  The present invention has been made in view of such problems, and a main object of the present invention is to provide a hybrid integrated circuit device in which the heat radiation effect of the semiconductor elements constituting the bridge circuit is improved.
[0013]
[Means for Solving the Problems]
  The present invention provides four transistorsWithIn a circuit device having a built-in H-bridge circuit that extracts an output between connection points of the transistor, the conductive pattern electrically connected to the transistor, and the conductive pattern and the lower surface of the conductive pattern are exposed. An insulating resin that covers the transistor, and the conductive pattern is provided between the first conductive pattern having the first main electrode of the transistor fixed to the upper surface and the first conductive pattern. A second conductive pattern connected to the second main electrode or the control electrode of the transistor, and each of the four transistors is disposed at four corners of the circuit device having a square shape in plan view, The output of the H-bridge circuit is extracted from the first conductive pattern in a region below the transistor.
[0014]
[0015]
[0016]
[0017]
[0018]
[0019]
[0020]
DETAILED DESCRIPTION OF THE INVENTION
  (Example:Configuration of hybrid integrated circuit device 10)
  With reference to FIG. 1, the configuration of the hybrid integrated circuit device 10 of the present invention will be described. FIG. 1A is a plan view of the hybrid integrated circuit device 10, and FIG. 1B is a cross-sectional view of the hybrid integrated circuit device 10.
[0021]
  Referring to FIGS. 1A and 1B, hybrid integrated circuit device 10 has the following configuration. That is, in the hybrid integrated circuit device having a built-in bridge circuit in which four MOS transistors TR1, TR2, TR3 and TR4 are connected in an H bridge shape and an output is taken out between the connection points of each set of MOS transistors. An insulating resin 17 that covers and integrally supports the first conductive patterns 11, 12, 13, and 14 for fixing the MOS transistors and the MOS transistors, and a first exposed from the back surface of the insulating resin 17. The hybrid integrated circuit device 10 includes first external electrodes 21, 22, 23, and 24 provided on the conductive patterns 11, 12, 13, and 14. The connection points J1 and J2 are directly taken out from the first external electrodes 21, 22, 23 and 24. Each of these components will be described below.
[0022]
  The first conductive patterns 11, 12, 13 and 14 are made of metal such as copper foil, and are embedded in the insulating resin 17 with the back surface exposed. Four first conductive patterns 11, 12, 13, and 14 are arranged at the four corners of the hybrid integrated circuit device 10, and the two sides have an outer shape. MOS transistors TR1 to TR4 are mounted on the first conductive patterns 11, 12, 13 and 14, respectively. First conductive pattern
The shapes of the turns 11, 12, 13, and 14 can be changed depending on the circuit configured therein. For example, as shown in the plan view, the first conductive pattern can be locally extended in the lateral direction in order to secure a region to be a bonding pad of the fine metal wire 16. That is, the shapes of the first conductive patterns 11, 12, 13, and 14 may not be the same. Here, the first conductive pattern 11 and the other first conductive pattern 12 are continuous and electrically coupled. However, when the first conductive pattern 11 and another first conductive pattern 12 are electrically connected on the substrate side on which the hybrid integrated circuit device 10 is mounted, the first inside the hybrid integrated circuit device 10 is the first. The conductive patterns can be electrically separated from each other. Here, first external electrodes 21, 22, 23 and 24 made of a brazing material such as solder indicated by hatching are formed on the back surfaces of the first conductive patterns 11, 12, 13 and 14.
[0023]
  Similar to the first conductive pattern described above, the second conductive pattern 15 is made of a metal such as copper, and is buried in the insulating resin 17 with the back surface exposed. The second conductive pattern 15 is provided between the first conductive patterns 11, 12, 13 and 14. The second conductive pattern 15 is electrically connected to the gate electrodes or source electrodes of the MOS transistors TR1 to TR4 mounted on the first conductive pattern via the fine metal wires 16. Specifically, five second conductive patterns 15 are provided in the hybrid integrated circuit device 10. The four second conductive patterns 15 are electrically connected to the gate electrodes of the MOS transistors TR1 to TR4 through the thin metal wires 16. The remaining one second conductive pattern 15 is connected to the source electrodes of the MOS transistors TR3 and TR4 via the metal thin wire 16, and is a conductive pattern that works as a ground potential. Here, on the back surface of the second conductive pattern 15, a second external electrode 25 made of a brazing material such as solder indicated by hatching with hatching is formed.
[0024]
  MOS transistors TR1, TR2, TR3 and TR4 are arranged one by one at the four corners. Here, the individual MOS transistors TR1, TR2, TR3 and TR4 are mounted on the first conductive patterns 11, 12, 13 and 14 with the drain electrode as the bottom surface. The gate electrodes of the MOS transistors TR1, TR2, TR3, and TR4 are connected to the second conductive pattern via the metal thin wire 16.
Connected to turn 15. The source electrode of the MOS transistor TR1 is connected to the first conductive pattern 13 on which the MOS transistor TR3 is mounted via the fine metal wire 16. The source electrode of the MOS transistor TR2 is connected to the first conductive pattern 14 on which the MOS transistor TR4 is mounted via the fine metal wire 16. Furthermore, MOS transistors TR3 and TR
Both source electrodes 4 are connected to a second conductive pattern 15 provided between both MOS transistors via a fine metal wire 16. The MOS transistor is mounted via a brazing material such as solder or Ag paste.
[0025]
  In the above description, the MOS transistors TR <b> 1 to TR <b> 4 are employed as elements that are built in the hybrid integrated circuit device 10 and constitute a bridge circuit. However, it is also possible to use bipolar transistors as an alternative to MOS transistors.
[0026]
  The insulating resin 17 exposes the back surfaces of the first and second conductive patterns and seals the whole. Here, the MOS transistor, the fine metal wire 16 and the conductive pattern are sealed. As a material for the insulating resin 17, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be used.
[0027]
  The first external electrodes 21 to 24 are provided on the back surfaces of the first conductive patterns 11 to 14 with a brazing material such as solder. Specifically, the first external electrodes 21 to 24 are provided so as to be positioned below the MOS transistors TR1 to TR4 mounted on the first conductive pattern. The planar size of the first external electrodes 21 to 24 is the planar size of the MOS transistors TR1 to TR4 located above each of the first external electrodes 21 to 24.
It is formed larger than. Therefore, it can be said that the MOS transistors TR1 to TR4 are arranged so as to overlap the first external electrodes 21 to 24. Further, the shape of the first external electrodes 21 to 24 is a square shape similar to the shape of the MOS transistor, and each is formed in the same size. The first external electrodes 23 and 24 serve as connection points that are electrically connected to a load (not shown) provided outside the hybrid integrated circuit device 10. Furthermore, the first external electrodes 21 and 22 are electrically connected to a power source. Details of the bridge circuit built in the hybrid integrated circuit device 10 will be described later with reference to FIG.
[0028]
  The second external electrode 25 is provided on the back surface of the second conductive pattern 15 with a brazing material such as solder. As described above, since the second conductive pattern 15 is electrically connected to the gate electrodes or source electrodes of the MOS transistors TR1 to TR4, the second external electrode 25 is the gate electrode or source of the MOS transistors TR1 to TR4. It is electrically connected to the electrode. In FIG. 1A, the second external electrode 25 connected to the gate electrodes of the MOS transistors TR1 to TR4 has a circular shape in plan view, and the size thereof is smaller than that of the first external electrode. Is formed. This is because the pulse wave applied to the gate electrode of the MOS transistor flows through these second external electrodes 25, and therefore, the value of the current flowing therethrough is small compared to the first external electrodes 21-24. . Note that, on the back surface of the hybrid integrated circuit device 10, a portion where the first or second external electrode is not provided may be covered with a solder resist.
[0029]
  With reference to FIG. 1B, a cross section of the hybrid integrated circuit device 10 mounted on the mounting substrate 30 will be described. In the figure, hatched arrows indicate paths of heat generated from the MOS transistors.
[0030]
  The hybrid integrated circuit device 10 having the above-described configuration and incorporating the H bridge circuit is mounted on the conductive path of the mounting substrate 30 by a reflow process. In the drawing, first external electrodes 23 and 24 are fixed to a first conductive path 31 formed on the mounting substrate 30. The first conductive path 31 formed on the mounting substrate 30 is connected to a load that is an output destination of the H bridge circuit. Therefore, it can be said that the connection point of the H-bridge circuit built in the hybrid integrated circuit device 10 is directly taken out from the first external electrodes 23 and 24.
[0031]
  MOS transistors TR3 and TR4 are fixed with the drain electrode as the bottom surface. Therefore, heat generated by the MOS transistors TR3 and TR4 switching at high speed is transmitted in the direction of the arrow shown in FIG. Specifically, the light is transmitted to the first conductive paths 30 and 31 via the first conductive patterns 13 and 14 and the first external electrodes 23 and 24, and is emitted to the outside. The same applies to the MOS transistors TR1 and TR2.
[0032]
  Further, the MOS transistors TR1 to TR4 are arranged at the four corners, and all of them are mounted with the first conductive patterns 11 to 14 with the drain electrode as the bottom surface, so that the heat radiation from the MOS transistors TR1 to TR4 is good. To be dissipated. Therefore, the heat dissipation balance is very good and local temperature rise can be suppressed.
[0033]
  Furthermore, the first conductive patterns 11 to 14 on which the MOS transistors TR1 to TR4 are mounted occupy most of the hybrid integrated circuit device 10 in plan view. Heat dissipation of the MOS transistors TR1 to TR4 is performed via the first conductive patterns 11 to 14. Therefore, by forming the first conductive patterns 11 to 14 large in this way, a heat dissipation path generated from the MOS transistors TR1 to TR4 can be secured, so that the heat dissipation effect can be improved.
[0034]
  With reference to FIG. 2, the H bridge circuit configured in the hybrid integrated circuit device 10 will be described.
[0035]
  In this H-bridge circuit, four MOS transistors TR1, TR2, TR3, and TR4 are connected in a bridge shape, and outputs are taken out from a connection point between TR1 and TR3 and a connection point between TR2 and TR4. A load is provided between the outputs. Further, power is supplied from the connection point between TR1 and TR2, and GND is provided at the connection point between TR3 and TR4.
[0036]
  In the present invention, the output is taken out from the first external electrodes 23 and 23 provided on the back surfaces of the first conductive patterns 13 and 14 on which the MOS transistors TR3 and TR4 are mounted, and connected to the load. Power is supplied from the first external electrodes 21 and 22 provided on the back surfaces of the first conductive patterns 11 and 12 on which the MOS transistors TR1 and TR2 are mounted.
[0037]
  An operation example of the H bridge circuit configured as described above will be described. Pulse signals are applied to the gate electrodes G1, G2, G3 and G4 of TR1, TR2, TR3 and TR4. Since the pulse signals applied to G1 and G4 are synchronized, TR1 and TR4 perform an ON-OFF operation at the same timing. Further, since the pulse signals applied to G2 and G3 are synchronized, TR2 and TR3 perform an ON-OFF operation at the same timing. Furthermore, the timing when TR1 and TR4 are turned on is different from the timing when TR2 and TR3 are turned on.
[0038]
  When TR1 and TR4 are in the ON state, the current supplied from Vdd flows in the order of Vdd → TR1 → first external electrode 23 → load → first external electrode 24 → TR4 → GND. When TR2 and TR3 are in the ON state, the current supplied from Vdd flows in the order of Vdd → TR2 → first external electrode 24 → load → first external electrode 23 → TR3 → GND.
[0039]
  Various loads can be adopted as the above-described load. For example, a low-pass filter 35 composed of a coil and a capacitor can be adopted as this load. In this case, a carrier signal obtained by PWM modulating the audio signal is added to G1 to G4. Then, the amplified audio signal is output to the speaker 36 by removing the carrier signal with the low-pass filter connected to the load.
It is. It is also possible to employ a motor or the like as a load connected to the output of the H bridge.
[0040]
  With reference to FIG. 3, another embodiment of the hybrid integrated circuit device 10 will be described. 3A is a plan view of another hybrid integrated circuit device 10, and FIG. 3B is a cross-sectional view taken along the arrow in FIG. 1A.
[0041]
  As described above, in the hybrid integrated circuit device 10 shown in FIG. 1, the four MOS transistors TR1 to TR4 are arranged at the four corners. On the other hand, in the hybrid integrated circuit device 10 shown in FIG. 3, three MOS transistors TR1, TR2, and TR4 are arranged at the corner, and one MOS transistor TR2 is arranged near the center. Accordingly, the shapes of the first and first conductive patterns are also different from those of the hybrid integrated circuit device 10 shown in FIG. Specifically, the first conductive pattern 11 on which the MOS transistor TR1 is mounted also extends near the center. The MOS transistor TR2 is mounted on the first conductive pattern 11 extending to the central portion. Therefore, the MOS transistors TR1 and TR2 are mounted on the same conductive pattern 11 and are electrically connected. Yes.
[0042]
  However, the H bridge circuit configured in the hybrid integrated circuit device 10 is the same as that shown in FIG. The same applies to each component constituting the hybrid integrated circuit device 10.
[0043]
  Referring to FIG. 3A, the output of the built-in H bridge circuit is taken out from first external electrodes 13 and 14. The power is supplied from the electrode provided on the back surface of the first conductive pattern 11 on which the MOS transistors TR1 and TR2 are mounted. Therefore, the output from the H bridge circuit is taken out via the first conductive patterns 13 and 14 on which the MOS transistors are mounted.
This is performed directly from the partial electrodes 23 and 24. Therefore, it is possible to minimize the distance from the load that is the output destination of the H-bridge circuit. Furthermore, the heat dissipation effect of the MOS transistors TR1 to TR4 is also improved.
[0044]
  In the above description, the H bridge circuit is configured in the hybrid integrated circuit device 10. However, a half bridge circuit may be configured in the hybrid integrated circuit device 10 instead of the H bridge circuit. In this case, two MOS transistors are built in the hybrid integrated circuit device 10. Further, the conductive pattern is also changed so that a half bridge circuit is formed inside. Specifically, a half-bridge circuit can be configured with the left half or the right half of FIG.
[0045]
  Even when the half-bridge circuit is configured, the bridge circuit is taken out from the external electrode formed on the back surface of the conductive pattern on which the MOS transistor is mounted. Therefore, even when the half-bridge circuit is built in the hybrid integrated circuit device 10, it has the same characteristics and effects as when the H-bridge circuit is built.
[0046]
  A feature of the present invention is that a connection point between an H-bridge circuit configured inside the hybrid integrated circuit device 10 and a load provided outside is directly taken out from the first external electrodes 23 and 24. . Specifically, referring to FIG. 1, MOS transistors TR3 and TR4 are fixed to first conductive patterns 13 and 14 with their drain electrodes facing downward. The first conductive patterns 13 and 14 are fixed to the first conductive paths 30 and 31 on the mounting substrate 30 via the first external electrodes 23 and 24.
[0047]
  Therefore, the drain electrodes of the MOS transistors TR3 and TR4 are thermally transferred to the first conductive path 31 on the mounting substrate via the first conductive patterns 13 and 14 and the first external electrodes 23 and 24. Electrically connected. Therefore, the MOS transistors TR3 and TR4 are thermally and electrically connected to the first conductive path 31 on the mounting substrate at the shortest distance. Therefore, MOS transistors TR3 and TR4
The heat dissipation effect can be improved. Furthermore, since the distance from the load such as a low-pass filter can be shortened, it is possible to suppress the occurrence of secondary noise.
[0048]
  In the present embodiment, the case where a bridge circuit including four semiconductor elements is configured inside the hybrid integrated circuit device 10 has been described. However, the circuit built in the hybrid integrated circuit device 10 is not limited to the bridge circuit. . For example, it is possible to incorporate four semiconductor elements constituting a DC / DC converter in the hybrid integrated circuit device 10. Specifically, a booster circuit is configured in the hybrid integrated circuit device 10.
It is possible to incorporate two semiconductor elements that constitute the step-down circuit. A semiconductor element constituting a DC / DC converter has a relatively large current flowing therethrough, and generates a large amount of heat in order to perform switching at a higher speed. Therefore, by adopting the configuration of the hybrid integrated circuit device 10 as described above, the heat generated from the semiconductor elements constituting the DC / DC converter can be efficiently discharged to the outside.
[0049]
(Reference example: Method of manufacturing hybrid integrated circuit device 10)
  Below, as a reference example,A method for manufacturing the hybrid integrated circuit device 10 will be described. BookReference exampleNow, a method for manufacturing the hybrid integrated circuit device 10 shown in FIG. 1 will be described. However, the manufacturing method is the same for the hybrid integrated circuit device 10 and the hybrid integrated circuit device incorporating the half-bridge circuit as shown in FIG. .
[0050]
  The hybrid integrated circuit device 10 is manufactured by the following process. That is, a step of preparing the conductive foil 40, a step of forming a separation groove 41 shallower than the thickness of the conductive foil 40 in the conductive foil 40 to form the conductive pattern 51, and each circuit device portion 45 of the desired conductive pattern 51. The step of fixing the MOS transistor to the substrate, the step of wire bonding between the MOS transistor and the desired conductive pattern 51, and the MOS transistor of each circuit device unit 45 are collectively covered so that the isolation groove 41 is filled. It is composed of a step of common molding with the insulating resin 17, a step of removing the back surface of the conductive foil 40 until the insulating resin 17 is exposed, and a step of dicing the insulating resin 17 to separate the circuit device portion. ing. Below, each process of this invention is demonstrated with reference to FIGS.
[0051]
  In the first step of the present invention, as shown in FIGS. 4 to 6, a conductive foil 40 is prepared, and a separation groove 41 shallower than the conductive foil 40 is formed in the conductive foil 40 by etching to form a conductive pattern 51. It is to form.
[0052]
  In this step, first, a sheet-like conductive foil 40 is prepared as shown in FIG. The conductive foil 40 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy such as Ni is employed.
[0053]
  The thickness of the conductive foil is preferably about 10 μm to 300 μm in consideration of later etching, but it is basically good if it is 300 μm or more or 10 μm or less. As will be described later, it is only necessary that the separation groove 41 shallower than the thickness of the conductive foil 40 can be formed.
[0054]
  In addition, the sheet-like conductive foil 40 is prepared by being wound into a roll with a predetermined width, for example, 45 mm, and this may be conveyed to each step described later, or a strip-shaped cut into a predetermined size. The conductive foil 40 may be prepared and conveyed to each process described later.
[0055]
  Specifically, as shown in FIG. 4B, 4 to 5 blocks 42 in which a large number of circuit device portions 45 are formed are arranged on the strip-shaped conductive foil 40 so as to be spaced apart. A slit 43 is provided between each block 42 to absorb the stress of the conductive foil 40 generated by the heat treatment in the molding process or the like. Also, index holes 44 are provided at regular intervals at the upper and lower peripheral ends of the conductive foil 40, and are used for positioning in each step. Subsequently, a conductive pattern is formed.
[0056]
  First, as shown in FIG. 5, a photoresist (etching resistant mask) PR is formed on the conductive foil 60, and the photoresist PR is patterned so that the conductive foil 40 excluding the region to be the conductive pattern 51 is exposed. Then, as shown in FIG. 6A, the conductive foil 40 is selectively etched.
[0057]
  A specific conductive pattern 51 is shown in FIG. This figure corresponds to an enlarged view of one of the blocks 42 shown in FIG. One hatched portion is one circuit device unit 45, and in one block 42, a large number of circuit device units 45 are arranged in a matrix of 2 rows and 2 columns, and the same conductive pattern is provided for each circuit device unit 45. 51 is provided. A frame-like pattern 46 is provided around each block, and a small amount
An alignment mark 47 for dicing is provided inside and separated from the inner side. The frame-shaped pattern 46 is used for fitting with a mold, and has a function of reinforcing the insulating resin 17 after the back surface etching of the conductive foil 40.
[0058]
  In the second step of the present invention, as shown in FIG. 7, the MOS transistors TR1 to TR4 are fixed to each circuit device portion 45 of the desired conductive pattern 51, the electrodes of the MOS transistors TR1 to TR4, the desired conductive pattern 51, and the like. Is to wire bond.
[0059]
  Here, a MOS transistor is employed as the transistor, but a bipolar transistor can be employed. Bare chip MOS transistor chips TR1 to TR4 are die-bonded to the first conductive patterns 11 to 14, respectively.
[0060]
  Thereafter, the base electrodes and the gate electrodes of the MOS transistors TR1 to TR4 of each circuit device are collectively bonded by ball bonding by thermocompression bonding and wedge bonding by ultrasonic waves. Specifically, the gate electrode and the base electrode of each MOS transistor are connected to the second conductive pattern 15 through a fine metal wire.
[0061]
  In the third step of the present invention, as shown in FIG. 8, the MOS transistors TR1 to TR4 of each circuit device section 45 are collectively covered, and are molded with the insulating resin 17 so as to fill the isolation grooves 41. There is.
[0062]
  In this step, as shown in FIG. 8A, the insulating resin 17 completely covers the MOS transistors TR1 to TR4A and the plurality of conductive patterns, and the isolation groove 41 is filled with the insulating resin 17, and the isolation groove 41 to fit firmly. The conductive pattern 51 is supported by the insulating resin 17.
[0063]
  Further, this step can be realized by transfer molding, injection molding, or potting. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.
[0064]
  Further, when performing transfer molding or injection molding in this step, each block 42 stores the circuit device portion 63 in one common mold as shown in FIG. 8B, and one insulating property is provided for each block. The resin 17 is molded in common. For this reason, the amount of resin can be greatly reduced as compared with a method in which each circuit device unit is individually molded, such as a conventional transfer mold.
[0065]
  The feature of this step is that the conductive foil 40 that becomes the conductive pattern 51 becomes a support substrate until the insulating resin 17 is coated. Conventionally, the conductive pattern is formed by using a support substrate that is not originally required, but in the present invention, the conductive foil 40 serving as the support substrate is a material necessary as an electrode material. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.
[0066]
  Further, since the separation groove 41 is formed shallower than the thickness of the conductive foil, the conductive foil 40 is not individually separated as the conductive pattern 51. Therefore, the sheet-like conductive foil 40 can be handled as a unit, and when the insulating resin 17 is molded, it has a feature that the work of transporting to the mold and mounting to the mold becomes very easy.
[0067]
  The fourth step of the present invention is to remove the back surface of the conductive foil 40 until the insulating resin is exposed.
[0068]
  In this step, the back surface of the conductive foil 40 is chemically and / or physically removed and separated as the conductive pattern 51. This step is performed by polishing, grinding, etching, laser metal evaporation, or the like.
[0069]
  In the experiment, the conductive foil 40 is wet-etched on the entire surface to expose the insulating resin 17 from the separation groove 41. This exposed surface is indicated by a dotted line in FIG. As a result, the conductive pattern 51 is separated.
[0070]
  As a result, the back surface of the conductive pattern 51 is exposed to the insulating resin 17. That is, the surface of the insulating resin 17 filled in the separation groove 41 and the surface of the conductive pattern 51 are substantially matched.
[0071]
  Furthermore, the back surface treatment of the conductive pattern 51 is performed to obtain, for example, the final structure shown in FIG. That is, a conductive material such as solder is deposited on the exposed conductive pattern 51 as necessary to complete the circuit device.
[0072]
  The fifth step of the present invention is to separate the insulating resin 17 by dicing for each circuit device section 45 as shown in FIG.
[0073]
  In this step, the block 42 is vacuum-adsorbed on the mounting table of the dicing apparatus, and the insulating resin 17 in the separation groove 41 is diced along a dicing line (one-dot chain line) between the circuit device portions 45 with a dicing blade 49, Separate into individual hybrid integrated circuit devices.
[0074]
  In this step, the dicing blade 49 may be cut at a cutting depth that substantially cuts the insulating resin 17, and after taking out the block 42 from the dicing apparatus, a chocolate break may be caused by a roller. At the time of dicing, the alignment mark 47 of each block provided in the first step described above is recognized in advance and dicing is performed based on this. As is well known, dicing dicing all dicing lines in the vertical direction
Then, the mounting table is rotated 90 degrees and dicing is performed according to the horizontal dicing line 70.
[0075]
【The invention's effect】
  In the present invention, the following effects can be obtained.
[0076]
  First, in the present invention, in a hybrid integrated circuit device with a built-in H-bridge circuit, an output is directly extracted from a first external electrode provided on the back surface of the first conductive pattern on which the MOS transistor is mounted. ing. Therefore, compared with the conventional method of mounting a circuit device via leads, the distance between the semiconductor elements can be shortened, and the distance between the conductive path on the mounting substrate and the semiconductor element can be shortened. this thing
Since the distance from the load such as the low-pass filter that is the output destination of the H bridge circuit built in the hybrid integrated circuit device can be shortened, the occurrence of secondary noise can be suppressed.
[0077]
  Furthermore, since the MOS transistor is thermally coupled to the conductive path on the mounting substrate via the first conductive pattern and the first external electrode, the heat generated from the MOS transistor is favorably transferred to the conductive path. It is transmitted and released to the outside.
[0078]
  Second, the four first conductive patterns for mounting the MOS transistors TR1 to TR4 are arranged at the four corners of the hybrid integrated circuit device. Therefore, the conductive path of the mounting substrate connected to the first conductive step through the external electrode can be formed large. Thus, the heat released from the MOS transistor can be released to the outside through the conduction.
[0079]
  Third, the four first external electrodes formed on the back surface of the first conductive pattern on which the MOS transistor is mounted are larger than the MOS transistor and formed in the same shape. Accordingly, the strength of fixing the hybrid integrated circuit device to the mounting substrate can be improved, and thus the external electrodes can be prevented from being damaged under the usage conditions.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view illustrating a hybrid integrated circuit device of the present invention.
FIG. 2 is a circuit diagram illustrating an H-bridge circuit built in the hybrid integrated circuit device of the present invention.
3A and 3B are a plan view and a cross-sectional view illustrating a hybrid integrated circuit device of the present invention.
4A and 4B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a hybrid integrated circuit device of the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a hybrid integrated circuit device of the present invention.
6A and 6B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a hybrid integrated circuit device of the present invention.
7A and 7B are a plan view and a cross-sectional view illustrating a method for manufacturing a hybrid integrated circuit device of the present invention.
8A and 8B are a cross-sectional view and a plan view illustrating a method for manufacturing a hybrid integrated circuit device of the present invention.
FIG. 9 is a plan view illustrating the method for manufacturing the hybrid integrated circuit device of the present invention.
FIG. 10 is a cross-sectional view illustrating a conventional circuit device.
FIG. 11 is a circuit diagram illustrating a conventional circuit device.
FIG. 12 is a perspective view illustrating a conventional circuit device.

Claims (5)

In a circuit device including four transistors and incorporating an H-bridge circuit that extracts an output between connection points of the transistors,
A conductive pattern electrically connected to the transistor, and an insulating resin that covers the conductive pattern and the transistor in a state where a lower surface of the conductive pattern is exposed;
The conductive pattern is provided between a first conductive pattern in which a first main electrode of the transistor is fixed on an upper surface and the first conductive pattern, and a second main electrode or a control electrode of the transistor. A second conductive pattern connected,
Each of the four transistors is arranged at four corners of the circuit device having a square shape in plan view,
A circuit device, wherein the output of the H-bridge circuit is extracted from the first conductive pattern in a region below the transistor.   2. The circuit device according to claim 1, wherein the transistor is either a MOS transistor or a bipolar transistor.   2. The circuit device according to claim 1, wherein an external electrode is provided on a lower surface of the first conductive pattern in a region where the transistor is fixed.   2. The circuit device according to claim 1, wherein the size of the external electrode is larger than that of the transistor. External electrodes are provided on the lower surface of the conductive pattern,
The external electrode connected to the first main electrode or the second main electrode of the transistor is formed in a square shape, and the external electrode connected to the control electrode of the transistor is formed in a circular shape. The circuit device according to claim 1.

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