JP4006180B2 - マルチスレッド式プロセッサでスレッド切替えイベントを選択するための方法および装置 - Google Patents

マルチスレッド式プロセッサでスレッド切替えイベントを選択するための方法および装置 Download PDF

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Publication number
JP4006180B2
JP4006180B2 JP2000517334A JP2000517334A JP4006180B2 JP 4006180 B2 JP4006180 B2 JP 4006180B2 JP 2000517334 A JP2000517334 A JP 2000517334A JP 2000517334 A JP2000517334 A JP 2000517334A JP 4006180 B2 JP4006180 B2 JP 4006180B2
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thread
cache
processor
switch
instruction
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JP2001521215A (ja
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ボルケンハーゲン、ジョン、マイケル
アイケマイヤー、リチャード、ジェームズ
フリン、ウィリアム、トーマス
レヴィンステイン、シェルダン、ベマード
ウォットレング、アンドリュー、ヘンリー
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
JP2000517334A 1997-10-23 1998-10-14 マルチスレッド式プロセッサでスレッド切替えイベントを選択するための方法および装置 Expired - Fee Related JP4006180B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/958,716 1997-10-23
US08/958,716 US6697935B1 (en) 1997-10-23 1997-10-23 Method and apparatus for selecting thread switch events in a multithreaded processor
PCT/US1998/021716 WO1999021081A1 (en) 1997-10-23 1998-10-14 Method and apparatus for selecting thread switch events in a multithreaded processor

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JP2001521215A JP2001521215A (ja) 2001-11-06
JP4006180B2 true JP4006180B2 (ja) 2007-11-14

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JP2000517334A Expired - Fee Related JP4006180B2 (ja) 1997-10-23 1998-10-14 マルチスレッド式プロセッサでスレッド切替えイベントを選択するための方法および装置

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US (1) US6697935B1 (hu)
EP (1) EP1029269B1 (hu)
JP (1) JP4006180B2 (hu)
KR (1) KR100403658B1 (hu)
CN (1) CN1112636C (hu)
CA (1) CA2299348C (hu)
HU (1) HUP0100013A3 (hu)
IL (1) IL134823A (hu)
PL (1) PL193285B1 (hu)
TW (1) TW409227B (hu)
WO (1) WO1999021081A1 (hu)

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