JP3991286B2 - I / O circuit - Google Patents

Description

[0001]
【table of contents】
The present invention will be described in the following order.
Prior art (FIGS. 5 and 6)
Means for Solving the Problems to be Solved by the Invention Embodiment of the Invention (FIGS. 1 to 4)
Effect of the Invention
BACKGROUND OF THE INVENTION
The present invention relates to an input / output circuit, and is suitably applied to, for example, an input / output circuit for inputting / outputting data to / from a memory cell.
[0003]
[Prior art]
Conventionally, in a storage circuit such as a DRAM (dynamic random access memory), for example, data input via a predetermined signal line is amplified by a write amplifier (write amplification circuit) and written to a memory cell, and at the time of reading In FIG. 1, data read from the memory cell is amplified by a read amplifier (read amplifier circuit) and then output to a predetermined signal line through an output buffer.
[0004]
That is, in FIG. 5, reference numeral 1 denotes a memory circuit as a whole, and address data D _A input via the address buffer 2 is a row in which the memory decoder 6 designates the memory area of the memory cell 6 by row number and column number in the address decoder 3. The address is divided into an address and a column address, and is input to the memory cell 6 via the X address input circuit 4 and the Y address input circuit 5.
[0005]
The write data D _IN inputted to the write amplifier 9 via an input buffer 8 is amplified based on the timing of the write enable signal WTE1 and column signal CL1 is output from the control circuit 12 via the sense amplifier 11 memory Data is written in the area designated by the address data of the cell 6.
[0006]
On the other hand, when data is read from the memory cell 6, the data specified by the address data is input to the read amplifier 13 via the sense amplifier 11, and the read enable signal output from the control circuit 12 here. RAE1 and amplified based on the timing of the column signal CL1, via the output buffer 14 as the read data D _OUT to a predetermined signal line.
[0007]
Here, FIG. 6 shows a circuit configuration of a write amplifier 9 and the read amplifier 13 of the memory circuit 1, the NAND circuit of the logic circuit 9A write data D _IN write amplifier 9 input through the input buffer NAND1 and NAND3 Input to one input terminal of each. Also the logical circuit 9A after inverted by the NOT circuit INV1 write data D _IN, and inputs it to the NAND circuit NAND2 and a respective one of the input terminals of NAND4.
[0008]
The output of the NAND circuit NAND1 is input to the gate of a field-effect transistor (hereinafter referred to as an H-active transistor) TRH1 that has an active operation (ON operation) with a gate input having a logic “H (high)” level. The The output of the NAND circuit NAND2 is inverted via the NOT circuit INV2 and then input to the gate of the H active transistor TRH2. The output of the NAND circuit NAND3 is inverted via the NOT circuit INV3 and then input to the gate of the H active transistor TRH3. The output of the NAND circuit NAND4 is input to the gate of the H active transistor TRH4.
[0009]
Signal of the write data bus BAS _W1 outputted from the slave connexion the logical circuit 9A, the write data D one signal line L1 and the other signal, respectively the signal level on line L2 is "H" in response to the _IN level or "L The signal is inverted to level.
[0010]
Also to the write data bus BAS _W1 is connected to Purichiyaji circuit 9B, by the write data D _IN of the writing Purichiyaji signal PRW is in other than the writing is summer and logic "L" level, Purichiyaji signal this writing Three L-active transistors TRL1, TRL2, and TRL3 that input PRW to the gate are activated to hold the write data bus BAS _W1 at the power supply voltage. Incidentally, the L-active transistor is a field effect transistor that performs an active operation (ON operation) when the signal level input to the gate is a logic “L” level.
[0011]
When slave connexion write data D _IN is inputted, keeping the write data bus BAS _W1 by raising the write Purichiyaji signal PRW logical "H" level to the floating state, the write enable signal WTE1 in this state logic by raising the "H" level, negative the write enable signal WTE1 is inputted to the other input terminal aND circuit NAND1, NAND2, NAND3 and NAND4 takes in write data D _iN, respectively, to the write data D _iN In response, signals inverted to the logic “H” level or logic “L” level are output to the signal lines L1 and L2 of the write data bus BAS _W1 .
[0012]
By the write data D _IN, which is output to the data bus BAS _W1 for writing the H Akuteibu transistor TRH5 and TRH6 is Yotsute Akuteibu operation to the write enable signal WTE1, H Akuteibu type provided in an output stage for the sense amplifier It is output to transistors TRH8 and TRH9. By this time the H Akuteibu transistor TRH8 and TRH9 is operating Yotsute Akuteibu the column signal CL1, the write data D _IN is written into the memory cell 6 via the subsequent sense amplifier.
[0013]
On the other hand, in the read amplifier 13, the precharge circuit 13B is connected to the read data bus BAS _R1 , and the read precharge signal PRR is at the logic “L” level except when reading data from the memory cell. Thus, the three L-active transistors TRL5, TRL6, and TRL7 that input the read precharge signal PRR to the gate are activated to hold the read data bus BAS _R1 at the power supply voltage.
[0014]
If the slave connexion memory cell 6 reads the data had it occurred specified in the address data D _A, keeping the read data bus BAS _R1 in floating state by raising the read Purichiyaji signal PRR logical "H" level, In this state, the column signal CL1 is raised to the logic “H” level and the read enable signal RAE1 is raised to the logic “H” level, whereby the read data of the memory cell 6 is taken into the read data bus BAS _R1 .
[0015]
The read data bus BAS _R1 is connected to an amplifier circuit 13A having a current mirror configuration including four H-active transistors TRH13, TRH14, TRH15, and TRH16 and an H-active transistor TRH17 that constitutes a current source. A differential operation is performed when RAE1 rises to a logic "H" level.
[0016]
Accordingly, the difference between the read data taken in the two signal lines L3 and L4 constituting the read data bus BAS _R1 is amplified by the amplifier circuit 13A, and the negative data INV5 connected to the one signal line L3 is passed through the negative circuit INV5. Then, the data is output as the read data D _OUT via the subsequent output buffer 14 (FIG. 5). Incidentally, the L active type transistor TRL8 provided in the output line is configured to keep the output line at the power supply voltage when the read enable signal RAE1 is at the logic “L” level, except when the read data is output from the memory cell 6. The output line is held at the power supply voltage.
[0017]
[Problems to be solved by the invention]
By the way, in the memory circuit 1 having such a configuration, there is a problem that the circuit scale is increased as a whole by configuring an amplifier circuit in each of the write amplifier 9 and the read amplifier 13 provided as the input / output circuit of the memory cell. In particular, when the memory circuit 1 is multi-bit, it is necessary to provide a plurality of write amplifiers 9 and read amplifiers 13 described above with reference to FIG. 6 according to the multi-bit, and it is inevitable that the circuit area increases. There was.
[0018]
The present invention has been made in view of the above points, and intends to propose an input / output circuit that can further reduce the circuit area.
[0019]
[Means for Solving the Problems]
In order to solve such a problem, the present invention is an input / output circuit that inputs data from the outside to a predetermined circuit and outputs data from the predetermined circuit to the outside. Differential amplifier circuit for amplifying the data output from the predetermined circuit to the first and second signal lines constituting the data bus for inputting the data of the data and outputting the data from the predetermined circuit to the outside In the differential amplifier circuit , a common connection point of the pair of transistors of opposite conductivity type with respect to the pair of transistors for supplying power supply voltage is the same conductivity type as the pair of transistors of opposite conductivity type. A data bus driving transistor is connected.
In addition, a charging transistor having a reverse conductivity type is connected to the common connection point with respect to the transistor forming the current source of the differential amplifier circuit.
Further, a driving unit that drives one of the driving transistors is provided in accordance with a first control signal input from the outside.
A second control signal which is input in common to the gate of the transistor of the transistor and the charge forming the current source of the differential amplifier circuit, when the first control signal and rises state, the data from the external When only a second control signal is input to a predetermined circuit and is in a rising state , data from the predetermined circuit is output to the outside.
[0020]
In this way, in the present invention, the data bus consisting of a pair of signal lines is used for inputting data to a predetermined circuit and for outputting data from the predetermined circuit, so that an output connected to the data bus is used. The amplifier circuit is also used for input. Accordingly, the data bus and the amplifier circuit are shared, so that the number of circuit elements can be reduced and the circuit area is reduced.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0022]
In FIG. 1, in which parts corresponding to those in FIG. 5 are assigned the same reference numerals, 20 denotes a memory circuit as a whole, and address data D _A input via the address buffer 2 is stored in the memory cell 6 in the address decoder 3. The region is divided into a row address and a column address that are designated by a row number and a column number, and is input to the memory cell 6 via the X address input circuit 4 and the Y address input circuit 5.
[0023]
The write data D _IN obtained from the outside via the input buffer 8 is input to the read / write amplifier 21 is provided as input-output circuit for a memory cell 6, the output from the control circuit 12 in the read / write amplifier 21 The signal is amplified based on the timing of the write enable signal WTE2, the read enable signal RAE2 and the column signal CL2, and is written to the area designated by the address data of the memory cell 6 via the sense amplifier 11.
[0024]
On the other hand, when data is read from the memory cell 6, the data in the memory cell 6 designated by the address data is output to the read / write amplifier 21 via the sense amplifier 11, and here the control circuit 12 amplified based on the timing of the read enable signal RAE2 and column signal CL2 output from, via the output buffer 14 as the read data D _OUT.
[0025]
Here, FIG. 2 shows a circuit configuration of the read / write amplifier 21 of the memory circuit 20, the write data D _IN obtained through the input buffer 8, one input terminal of the NAND circuit NAND21 of the data input control unit 21C , And after being inverted through the NOT circuit INV22, the signal is input to one input terminal of the NAND circuit NAND22. The NAND circuits NAND21 and NAND22 each receive a write enable signal WTE2 at the other input terminal.
[0026]
The output of the NAND circuit NAND21 is inverted via the NOT circuit INV24 and then input to the gate of the H active transistor TRH26 provided for driving the data bus. The output of the NAND circuit NAND22 is inverted via the NOT circuit INV23 and then input to the gate of the H active transistor TRH27 provided for driving the data bus.
[0027]
Accordance connexion write the data D _IN is introduced to the write enable signal by the rise of WTE2 connexion NAND circuit NAND21 and NAND 22, the output is H Akuteibu transistor mutually inverted from each NAND circuit NAND21 and NAND 22 TRH26 and TRH27 Input to the gate.
[0028]
As a result, only the H active type transistor TRH26 or TRH27 whose gate input becomes the logic "H" level is activated. For example, when only the H-active transistor TRH27 is activated when the gate input of the H-active transistor TRH27 becomes the logic "H" level and the gate input of the H-active transistor TRH26 becomes the logic "L" level, the read / write data bus BAS. The signal level of one of the two signal lines L21 and L22 constituting the _RW falls to the logic “L” level.
[0029]
A latch amplifier circuit 21B is connected to the read / write data bus BAS _RW . In the latch amplifier circuit 21B, the signal line L22 of the read / write data bus BAS _RW is connected to the gate of the L active transistor TRL25, and the signal line L21 is connected to the gate of the L active transistor TRL24. Therefore, for example, when the signal level of the signal line L22 falls to the logic “L” level, the other signal line L21 is held at the power supply voltage by the active operation of the L-active transistor THL25.
[0030]
The H active transistors TRH23 and TRH24 constituting the differential amplifier circuit of the latch amplifier circuit 21B have their gates connected to the signal lines L21 and L22 of the read / write data bus BAS _RW , respectively, and the current source of the differential amplifier circuit is The read enable signal RAE2 is input to the gate of the H active transistor TRH25 that forms the structure. Therefore, when the read enable signal RAE2 rises to the logic “H” level, the H active transistor TRH25 operates as a current source, thereby amplifying the signal level difference between the signal lines L21 and L22 by the differential amplifier circuit. It is made like that.
[0031]
Here, the voltage at the common connection point (node a) of the pair of H active transistors TRH23 and TRH24 constituting the differential amplifier circuit is a read enable signal input to the gate of the L active transistor THL26 constituting the charge circuit. When the RAE2 is at the logic “L” level, the L active transistor TRL26 is held at the power supply voltage by the active operation. Accordingly, when the read enable signal RAE2 is at the logic "L" level, the L active transistor TRL26 is activated and the H active transistor TRH25 is turned off, thereby preventing the differential amplifier circuit from malfunctioning. When the read enable signal RAE2 becomes a logic “H” level, the differential amplifier circuit operates.
[0032]
Thus latch amplifier circuit 21B, for example read enable signal RAE2 signal line L22 is in the state where the O connexion logic "L" level and the I connexion signal line L21 side to the input is held at the power supply voltage of the write data D _IN is logic " When the signal rises from the “L” level to the logic “H” level, the signal level difference between the signal lines L21 and L22 can be amplified.
[0033]
Also the read / write data bus BAS _RW is connected to Purichiyaji circuit 21A, it Purichiyaji signal PR is summer and logic "L" level except during reading writing and when reading data D _OUT of the write data D _IN by, is adapted to hold the Purichiyaji signal PR 3 one L Akuteibu transistor input to the gate of TRL21, TRL22 and TRL23 is to Akuteibu operating read / write data bus BAS _RW to the supply voltage.
[0034]
As shown in accordance connexion Figure 3, when the write data D _IN is input, read by raising the logic "H" level at time t11 the Purichiyaji signal PR (Fig. 3 (E)) / write data bus BAS _RW In this state, the column signal CL2 (FIG. 3A) input to the gates of the H active transistors TRH21 and TRH22 provided in the output stage for the sense amplifier is logically “H” at time t12. By rising to the level, the two H-active transistors TRH21 and TRH22 are activated, whereby the data in the memory cell 6 (FIG. 1) flows into the read / write data bus BAS _RW (FIG. 3B).
[0035]
The write enable signal WTE2 at time t13 At this time (FIG. 3 (D)) by raising a logic "H" level, the read / write data bus BAS respective write data D _IN in the signal lines L21 and L22 of the _RW Accordingly, signals whose signal levels are inverted are taken in (FIG. 3B), and read / write data is further raised by raising the read enable signal RAE2 (FIG. 3C) to a logic “H” level at time t14. the write data D _iN incorporated into bus BAS _RW is by connexion amplified latch amplifier circuit 21B, a memory cell 6 (FIG. 1) is output to the side.
[0036]
On the other hand, when the data stored in the memory cell 6 is read from the address specified by the address data D _A , first, as shown in FIG. 4, the precharge signal PR (FIG. 4E) is first applied at the time t21. After holding the read / write data bus BAS _RW in the floating state by raising it to the logic “H” level, the column signal CL2 (FIG. 4A) is raised to the logic “H” level at time t22. As a result, the designated read data D _OUT in the memory cell is taken into the read / write data bus BAS _RW (FIG. 4B).
[0037]
Further, when read enable signal RAE2 (FIG. 4C) rises to logic “H” level at time t23, read data D _OUT taken into read / write data bus BAS _RW is amplified by latch amplifier circuit 21B. (FIG. 4B) and output to the output buffer 14 (FIG. 1) via the negative circuit INV21. By the way, keeping the write enable signal WTE2 when the memory cell 6 reads out the read data D _OUT is a (FIG. 4 (D)) in a state that remains lowered to logic "L" level, H Akuteibu transistor TRH26 and The TRH 27 is held in the off state.
[0038]
In the above construction, when writing write data D _IN in the memory cell 6, somewhat amplify by connexion write data D _IN read / write data bus BAS _RW connected to the H Akuteibu transistor TRH26 and TRH27 to be Akuteibu operation This is taken into the read / write data bus BAS _RW .
The write data D _IN taken into read / write data bus BAS _RW is further amplified Te latch amplifier circuit 21B Niyotsu and written in the memory cell 6.
[0039]
On the other hand, when reading data from the memory cell 6, the H-active transistors TRH26 and TRH27 that are activated during the write operation are kept in the OFF state by holding the write enable signal WTE2 at the logic “L” level. To do. Therefore, in this state, the read / write data bus BAS _RW is in a state of taking in only the read data D _OUT from the memory cell 6, and after the read data D _OUT is amplified by the latch amplifying circuit 21B, this is read out. Output.
[0040]
In this way, by using the read / write data bus BAS _RW composed of the pair of signal lines L21 and L22 for both reading and writing, the latch amplifier circuit 21B provided in the reading / writing data bus BAS _RW can be used for reading and By combining it for writing, and switching this depending on the operating state of the H active transistors TRH26 and TRH27, the number of circuit elements and data buses constituting the amplifier circuit are reduced as a whole compared to the conventional case, Accordingly, the circuit area can be reduced.
[0041]
Thus, according to the above configuration, the memory circuit 20 that operates in the same manner as the conventional memory circuit 1 can be realized with a smaller circuit area. Therefore, even when a plurality of read / write amplifiers 21 are provided for the purpose of increasing the number of bits, for example, the circuit area can be further reduced.
[0042]
Incidentally, by providing the read / write amplifier 21 which is used for both reading and writing, the circuit area can be reduced to about 2/3 in the cell as compared with the case where it is provided separately as in the prior art. As a result, the circuit area of the entire memory circuit can be reduced by about 12.5 [%].
[0043]
In the above-described embodiment, the case where the present invention is applied to the data input / output circuit for the memory cell 6 has been described. However, the present invention is not limited to this, and the circuit provided in the input / output stage of other various circuits is described. The present invention can be widely applied.
[0044]
【The invention's effect】
As described above, according to the present invention, the data bus driving transistor connected to the data bus composed of a pair of signal lines is turned on at the time of data writing to take in the write data, and at the time of data reading, the transistor is turned on. When the data bus is used for data reading after being turned off, the data bus and the read amplifier circuit connected to the data bus can also be used for writing, and the number of circuit elements can be reduced.
Thus, an input / output circuit with a further reduced circuit area can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a memory circuit using an input / output circuit according to the present invention.
FIG. 2 is a connection diagram showing an embodiment in which an input / output circuit according to the present invention is applied to a read / write amplifier.
FIG. 3 is a signal waveform diagram showing an operation of a circuit at the time of data writing.
FIG. 4 is a signal waveform diagram showing an operation of a circuit at the time of data reading.
FIG. 5 is a block diagram showing a conventional memory circuit.
FIG. 6 is a connection diagram showing a circuit configuration of a conventional read amplifier and write amplifier.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,20 ... Memory circuit, 6 ... Memory cell, 8 ... Input buffer, 12 ... Control circuit, 14 ... Output buffer, 21 ... Read / write amplifier, 21B ... Latch amplifier circuit, 21C ... Data input control unit, TRH26, TRH27... Data bus driving transistor, BAS _RW ... Read / write data bus.

Claims (1)

In an input / output circuit that inputs data from the outside to a predetermined circuit and outputs data from the predetermined circuit to the outside,
A data bus for inputting data from the outside to the predetermined circuit and outputting data from the predetermined circuit to the outside;
A differential amplifier circuit that is connected to the first and second signal lines constituting the data bus and amplifies data output from the predetermined circuit;
Among the differential amplifier circuits , a pair of transistors for supplying a power supply voltage is connected to a common connection point of a pair of transistors of opposite conductivity type, and a transistor constituting a current source of the differential amplifier circuit A transistor for charging which is of a reverse conductivity type;
A driving transistor for the data bus connected to the first and second signal lines and having the same conductivity type as the pair of transistors connected to the common connection point;
A drive unit for driving one of the drive transistors in response to a first control signal input from the outside,
A second control signal which is input in common to the gate of the transistor of the transistor and the charge forming the current source of the differential amplifier circuit, when the first control signal and rises state, the external The input / output circuit is characterized in that data from the predetermined circuit is output to the outside when only the second control signal is in a rising state .

Images