JP3970643B2 - Ion implantation method - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an ion implantation method for forming a semiconductor element.
[0002]
[Prior art]
In a conventional ion implantation method for forming an impurity diffusion region such as a source / drain, there is a clamp for fixing the wafer to the frame of the ion implantation apparatus at the periphery of the semiconductor wafer. For this reason, when a resist is coated as a mask for ion implantation, rinsing (resist removal) of the peripheral portion of the wafer is generally performed so that the resist does not remain. If the wafer peripheral portion is not rinsed, the resist is peeled off at the clamp portion and foreign matter is generated. Therefore, the wafer peripheral portion must be rinsed.
[0003]
[Problems to be solved by the invention]
In ion implantation, a high concentration of impurities may be implanted. For this reason, high-concentration impurities are implanted into the rinse portion around the wafer. There is a risk that this impurity may be diffused to the outside in a process such as a later heat treatment and the characteristics may be changed by entering an element on the wafer. This problem is great in that the uniformity of the elements within the wafer surface is ensured.
[0004]
[Means for Solving the Problems]
According to the present invention, a hard mask for preventing ion implantation is provided in the edge rinse region at the periphery of the wafer, and the ion implantation is performed.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described with reference to FIG. 1 of HYPERLINK “JavaScript: void (0)”. The wafer 103 is fixed to a wafer holder (not shown) of the ion implantation apparatus using a clamp. The clamp fixes the wafer 103 at a part of the outermost peripheral portion of the wafer 103. A registry area (an area where no resist mask is formed) is formed wider than an area where the outer periphery of the wafer 103 is clamped. A hard mask is provided between the clamped wafer 103 and the ion source 101 for implanting ions as impurities. The hard mask 102 has a shape that covers the entire registry area. Ions emitted from the ion source 101 are implanted into the wafer 103, but if the hard mask 102 is used, ions are not implanted into the periphery of the wafer. The width of the hard mask is made to correspond to the rinse width of the peripheral portion of the wafer so that the same width can be covered.
[0006]
Further, by providing a hard mask wider than the rinse width, it becomes possible to prevent contamination of impurities more reliably. In this case, it is desirable to estimate the alignment accuracy between the wafer and the hard mask and determine how much overlap should be taken into consideration.
[0007]
【The invention's effect】
By using a hard mask, impurities can be prevented from being mixed into the peripheral portion of the wafer, the influence on the elements in the wafer can be suppressed, and highly accurate semiconductor mass production can be achieved.
[0008]
For example, in the case of a source / drain implanter, an impurity of about 5E15 cm ⁻² is usually ion-implanted. Since all of this is dosed to the periphery of the wafer, the impurity concentration at that location is very high. When a heat treatment for diffusion is performed, impurities are diffused outward, which may adversely affect elements in the wafer, such as a poly resistor and a transistor. By using the apparatus of the present invention, it is possible to prevent abnormality due to impurities around the wafer.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an ion method according to the present invention.
[Explanation of symbols]
101 Ion source 102 Hard mask 103 Wafer

Claims (1)

Ion implantation characterized by providing a hard mask having a width that can cover the same width as the edge rinse region in order to prevent impurities from being implanted into the edge rinse region at the periphery of the wafer. Method.

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