JP2003272550A - Ion implantation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that in a conventional ion implantation device, high-concentration impurities may be implanted in a rinse part in the peripheral part of a wafer, the impurities diffuse to the outside in a process of a heat treatment or the like and intrude into an element on the wafer, and hence the characteristic thereof can be changed. <P>SOLUTION: According to this application, the purpose can be accomplished by the ion implantation device characterized by having a hard mask for preventing ion implantation into an edge rinse region in the peripheral part of the wafer. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation method for forming a semiconductor device. 2. Description of the Related Art In a conventional ion implantation method for forming an impurity diffusion region such as a source / drain, a clamp for fixing a wafer to a base of an ion implantation apparatus is provided around a semiconductor wafer. . For this reason, when coating a resist as a mask for ion implantation, it is common to rinse (remove the resist) the periphery of the wafer so that the resist does not remain. If this wafer rinsing is not performed, the resist is peeled off at the clamped portion, and foreign matter is generated. Therefore, rinsing around the wafer must be performed. [0003] In ion implantation, high-concentration impurities may be implanted in some cases. For this reason,
High-concentration impurities are implanted into the rinsing portion around the wafer. There is a danger that these impurities will diffuse out in a later process such as heat treatment and will change the characteristics by entering the elements on the wafer. This problem is significant in that the uniformity of the elements within the wafer surface is ensured. According to the present invention, there is provided a hard mask for preventing ion implantation in an edge rinse region at a peripheral portion of a wafer. [0007] The present invention will be described with reference to FIG. The wafer 103 is fixed to a wafer holder (not shown) of the ion implantation apparatus using a clamp. The clamp is provided at a part of the outermost periphery of the wafer 103.
Is fixed. In addition, a resistance area (an area where a resist mask is not formed) is formed wider than an area related to the clamp on the outer peripheral portion of the wafer 103. A hard mask is provided between the clamped wafer 103 and an ion source 101 for implanting ions as impurities. The hard mask 102 has a shape that covers the entire resistance area. The ions emitted from the ion source 101 are implanted into the wafer 103, but if the hard mask 102 is used, the ions are not implanted into the periphery of the wafer. The width of the hard mask is made to correspond to the rinsing width of the peripheral portion of the wafer so that the same width can be covered. Further, by providing a hard mask wider than the rinse width, it is possible to more reliably prevent impurities from being mixed. In this case, it is desirable to estimate the alignment accuracy between the wafer and the hard mask, and to determine the degree of overlap in consideration of the accuracy. By using a hard mask, it is possible to prevent impurities from being mixed into the peripheral portion of the wafer, to suppress the influence on elements in the wafer, and to achieve high-precision mass production of semiconductors. . For example, in a source / drain implant, an impurity of about 5E15 cm ⁻² is usually ion-implanted.
Since all of this is dosed to the periphery of the wafer, the impurity concentration at that location is very high. When heat treatment for diffusion is performed, impurities diffuse outward, which may adversely affect elements in the wafer, for example, a polyresistor and a transistor. By using the apparatus of the present invention, abnormalities due to impurities around the wafer can be prevented.

[Brief description of the drawings] FIG. 1 is a schematic view showing an ion method according to the present invention. [Explanation of symbols] 101 ion source 102 Hard Mask 103 wafer

Claims (1)

Claims: 1. An ion implantation method, comprising: providing a hard mask for preventing ion implantation into an edge rinse region in a peripheral portion of a wafer;