JP3949682B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a TFT (thin film transistor) provided over an insulating substrate such as glass and a method for manufacturing the semiconductor device.

  Known semiconductor devices having TFTs on an insulating substrate such as glass include active liquid crystal display devices and image sensors that use these TFTs to drive pixels.

  A thin film silicon semiconductor is generally used for TFTs used in these devices. Thin film silicon semiconductors are roughly classified into two types: those made of amorphous silicon semiconductor (a-Si) and those made of crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a vapor phase method, and are highly mass-productive. However, physical properties such as conductivity have crystallinity. Since it is inferior to a silicon semiconductor, the establishment of a method for manufacturing a TFT made of a crystalline silicon semiconductor has been strongly demanded in order to obtain higher speed characteristics in the future. Note that the silicon semiconductor having crystallinity includes non-single crystal silicon such as polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, and semi-amorphous silicon having an intermediate state between crystalline and amorphous. Semiconductors are known. Hereinafter, these non-single-crystal silicon semiconductors having crystallinity are referred to as crystalline silicon.

As a method of obtaining a thin film silicon semiconductor having these crystallinity,
(1) A film having crystallinity is directly formed at the time of film formation.
(2) An amorphous semiconductor film is formed and given crystallinity by the energy of laser light.
(3) An amorphous semiconductor film is formed and crystallized by applying heat energy.
Is known. However, the method (1) is technically difficult to uniformly form a film having good semiconductor properties over the entire surface of the substrate, and the film forming temperature is as high as 600 ° C. There was also a problem of cost that a glass substrate could not be used. In the method (2), the excimer laser, which is currently most commonly used, has a problem that the throughput is low because the irradiation area of the laser beam is small. The laser is not stable enough to treat the material uniformly, and there is a strong sense of the next generation technology. The method (3) has an advantage that it can cope with a large area as compared with the methods (1) and (2), but it is also necessary to set the heating temperature to a high temperature of 600 ° C. or more, which is an inexpensive glass. Considering the use of a substrate, it is necessary to further lower the heating temperature. In particular, in the case of the current liquid crystal display device, the screen has been enlarged, and therefore it is necessary to use a large glass substrate as well. When such a large glass substrate is used, shrinkage and distortion in the heating process that is indispensable for semiconductor fabrication reduce the accuracy of mask alignment and the like, which is a serious problem. In particular, in the case of 7059 glass that is most commonly used at present, the strain point is 593 ° C., and the conventional heat crystallization method causes large deformation. In addition to the temperature problem, in the current process, the heating time required for crystallization is several tens of hours or more, and it is necessary to further shorten the time.

  The present invention provides means for solving the above problems. More specifically, in a method for producing a thin film made of a crystalline silicon semiconductor using a method of crystallizing a thin film made of amorphous silicon by heating, the temperature required for crystallization is lowered and the time is shortened. The purpose is to provide a process that balances the two. Of course, the silicon semiconductor having crystallinity produced using the process provided by the present invention has physical properties equivalent to or better than those produced by the prior art, and can be used for the active layer region of the TFT. It goes without saying that there are.

BACKGROUND OF THE INVENTION
The inventors have conducted the following experiment on the method of forming an amorphous silicon semiconductor film by the CVD method or the sputtering method and crystallizing the film by heating, as described in the section of the prior art. And discussed.

  First, as an experimental fact, when an amorphous silicon film is formed on a glass substrate and the mechanism for crystallizing this film by heating is investigated, crystal growth starts from the interface between the glass substrate and amorphous silicon, Above the film thickness, it was recognized that the film progressed in a columnar shape perpendicular to the substrate surface.

  In the above phenomenon, there is a crystal nucleus (a seed that becomes the basis of crystal growth) at the interface between the glass substrate and the amorphous silicon film, and the crystal grows from the nucleus. It is considered to be caused by Such crystal nuclei include impurity metal elements that are present in minute amounts on the substrate surface and crystal components on the glass surface (as called crystallized glass, the crystal component of silicon oxide exists on the glass substrate surface) Is considered).

  Therefore, we thought that it would be possible to lower the crystallization temperature by more aggressively introducing crystal nuclei, and in order to confirm the effect, a small amount of other metal was deposited on the substrate and non-coated on it. An experiment was conducted in which a thin film made of crystalline silicon was formed and then heated for crystallization. As a result, when several metals were formed on the substrate, a decrease in the crystallization temperature was confirmed, and it was predicted that crystal growth occurred using foreign substances as crystal nuclei. Therefore, the mechanism of the impurity metals that could be reduced in temperature was investigated in more detail.

  Crystallization can be considered in two stages: initial nucleation and crystal growth from the nuclei. Here, the initial nucleation rate is observed by measuring the time until fine crystals are generated at a constant temperature at a constant temperature. In some cases, the effect of introducing crystal nuclei on lowering the crystallization temperature was confirmed. Moreover, unexpectedly, when the growth of crystal grains after nucleation was examined by changing the heating time, a certain kind of metal was deposited, and then the amorphous silicon thin film deposited thereon was formed. In crystallization, it was observed that the rate of crystal growth after nucleation increased dramatically. This mechanism will be described in detail later.

  In any case, due to the above two effects, when a thin film made of amorphous silicon is formed on a small amount of a certain kind of metal, and then heated and crystallized, it has not been considered in the past. It has been found that sufficient crystallinity can be obtained in about 4 hours at a temperature of 580 ° C. or lower. Examples of impurity metals having such effects include indium, tin, antimony, germanium, thallium, lead, bismuth, and zinc. These are metal materials whose group or period is close to that of silicon and easily form a compound with silicon. In addition, since they have a material with a relatively low melting point, they are hereinafter referred to as “low melting point metal” in the present specification. In addition, lanthanoids are examples of materials that have the effect of lowering the temperature as a result of experiments with other elements. These are used as hydrogen storage alloys and have a common point that they have a high reaction to hydrogen. Therefore, these are referred to as “catalytic metals” in the present specification. Further, according to the knowledge of the present inventors, any material having the above physical properties among the elements of Groups 3, 4, and 5 can be used as the catalyst metal in principle. That is, the Group 3 elements B, Al, Ga, In, Tl, Sc, Y, and the lanthanoid are Group 4 elements C, Ge, Sn, Pb, Ti, Zr, and Hf are the 5 elements. N, P, As, Sb, Bi, V, Nb, and Ta can be used. However, it is preferable to use indium (In), tin (Sn), antimony (Sb), germanium (Ge), thallium (Tl), lead (Pb), bismuth (Bi), or zinc (Zn). It is useful for obtaining a remarkable effect. Zinc is a group 2 element, but can be used as the low melting point metal because of its low melting point.

  As an example of the effect of typical tin as a low melting point metal material, plasma CVD is performed on a substrate (Corning 7059) on which no treatment is performed, that is, a thin film of tin is not formed. When the thin film made of amorphous silicon formed by the method is crystallized by heating in a nitrogen atmosphere, if the heating temperature is 600 ° C., a heating time of 10 hours or more is required. In the case of using a thin film made of amorphous silicon on a substrate on which a small amount of tin thin film was formed, a similar crystallization state could be obtained by heating for about 1 hour. The determination of crystallization at this time utilized a Raman spectrum. From this alone, it can be seen that the effect of tin is very large.

  As can be seen from the above description, when a thin film of amorphous silicon is formed after forming a thin film of low melting point metal or catalytic metal, the time required for lowering the crystallization temperature and for crystallization is reduced. Shortening is possible. Therefore, a more detailed description will be added on the assumption that this process is used for manufacturing TFTs. As will be described in detail later, the low melting point metal thin film has the same effect when it is formed not only on the substrate but also on the amorphous silicon, and it is the same in the ion implantation. In the specification, these series of treatments will be referred to as “low melting point metal trace addition” and “catalyst metal trace addition”. Further, a method of adding at the time of forming an amorphous silicon thin film may be used.

  First, a method for adding a low melting point metal will be described. The addition of a small amount of low melting point metal can be achieved by forming a small amount of low melting point metal thin film on the substrate and then forming amorphous silicon. The method of forming a low-melting-point metal thin film has the effect of lowering the temperature as in both cases, and it has been found that the film-forming method can be either a sputtering method or a vapor deposition method, and the film-forming method is not limited. However, when a small amount of a low melting point metal thin film is formed on the substrate, a silicon oxide thin film is formed on the substrate rather than directly on the 7059 glass substrate, The effect is more remarkable when a small amount of a low melting point metal thin film is formed thereon. As a possible reason for this, it is important for the low temperature crystallization that silicon and a low melting point metal are in direct contact, and in the case of 7059 glass, components other than silicon can contact or react with each other. It is mentioned that it may inhibit. Also, the same addition method can be used for the catalyst metal.

As a method of adding a small amount, in addition to forming a thin film in contact with or under amorphous silicon, almost the same effect was confirmed even when adding by ion implantation. As the amount of the low melting point metal, for example, for tin, it has been confirmed that the temperature is lowered by addition of an amount of 1 × 10 ¹⁵ atoms / cm ³ or more, but in the addition amount of 1 × 10 ²¹ atoms / cm ³ or more, , since the shape of the peak of the Raman spectrum is clearly different from the ones of elemental silicon, the actually usable is in the range of ^{1 × 10 15 atoms / cm 3} ~5 × 10 19 atoms / cm 3 I think that the. Further, considering that the semiconductor is used for the active layer of the TFT, it is necessary to suppress this amount to 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁹ atoms / cm ³ .

  Subsequently, the crystallization mechanism presumed when a small amount of low melting point metal is added will be described first.

  As described above, when the low-temperature crystallization catalyst metal is not added, nuclei are randomly generated from crystal nuclei such as the substrate interface, and crystal growth from the nuclei is also random, depending on the production method (110). Alternatively, it has been reported that a relatively oriented crystal is obtained at (111), and of course, almost uniform crystal growth is observed over the entire thin film.

  First, in order to confirm this mechanism, analysis by DSC (differential scanning calorimeter) was performed. The amorphous silicon thin film formed on the substrate by plasma CVD was filled in the sample container while attached to the substrate, and the temperature was raised at a constant rate. Then, a clear exothermic peak was observed around 700 ° C., and crystallization was observed. This temperature naturally shifts when the rate of temperature increase is changed, but crystallization started from 700.9 ° C., for example, when performed at a rate of 10 ° C./min. Next, three types of temperature rising rates were measured and the activation energy for crystal growth after initial nucleation was determined from them by the Ozawa method. As a result, a value of about 3.04 eV was obtained. In addition, when the reaction rate equation was obtained by fitting with the theoretical curve, it was found that it was best explained by disordered nucleation and its growth model, and nuclei were randomly generated from crystal nuclei such as the substrate interface. The validity of the model of crystal growth from the nucleus was confirmed.

  The same measurement as described above was performed on a sample added with a low melting point metal, here a sample added with a small amount of tin as an example. Then, when the temperature is raised at a rate of 10 ° C./min, crystallization starts from 625.5 ° C., and the activation energy of crystal growth obtained from these series of measurements is about 2.3 eV, It became numerically clear that crystal growth was easy.

Here, the lowering of the crystallization start temperature can be considered relatively easily as a foreign matter effect as described above, but what is the cause of the decrease in activation energy for crystal growth? The inventors consider the following reasons as this reason.
The rate-limiting process in the crystallization of amorphous silicon is generally said to be self-diffusion of silicon atoms. If that is the case, a higher diffusion rate can be achieved. However, in the case of crystallization from amorphous silicon, unlike the precipitation of crystals from an aqueous solution or the like, it should be considered as crystallization from a highly viscous concentrated solution. The difference is very small and atoms cannot move easily. In order to give mobility to atoms in such an environment, the following three methods can be considered.
1. By changing the viscosity of the amorphous film, an environment in which silicon atoms can move more easily is created.
2. A large amount of defects or vacancies are introduced to create an environment in which silicon atoms can move easily.
3. Coulomb force or the like is applied to change the driving force for crystallization.
These three are not independent of each other, and it is considered that there are some which satisfy two or three of them at the same time depending on the material to be added.
Here, most of the low melting point metal materials added this time are as described in 1. above. Is considered to be satisfied. In addition, with respect to the Group 3 and 5 materials, it is expected that positive or negative vacancies will be formed in order to satisfy the principle of electrical neutrality, and that it is expected to satisfy 2. Similarly, in Groups 3 and 5, when the Fermi level is shifted by the generation of levels due to them, and the shift amount is different between the amorphous part and the crystalline part (generally, in the amorphous part It is considered that the driving force due to the difference in the shift amount is generated and the crystallization temperature can be lowered. As a result of supporting this mechanism, it is mentioned that it is difficult to lower the temperature when the groups 3 and 5 are added simultaneously.
Next, the crystallization mechanism when a catalyst metal is added will be described.
Also in this case, the activation energy of crystal growth by DSC was measured, and as a result, it was found to be about 2.1 eV, and it was found that crystallization was also promoted. The following mechanism is considered as the reason.
As described above, these “catalytic metals” are very reactive with hydrogen. Therefore, it is expected to bond preferentially with hydrogen bonded to silicon, and as a result, a large amount of dangling bonds are generated. This large amount of dangling bonds is the same as in 2. of the above-described method for imparting mobility to atoms. It is considered that Also, due to the difference in electronegativity between silicon and lanthanoids, vacancies may be generated to satisfy the principle of electrical neutrality. Otherwise, dangling bonds are electrically charged strongly. It is necessary to be. In that case, the above-mentioned 3. Therefore, it is expected that a driving force accompanying the movement of the Fermi level may be generated.

Next, the crystal form of the crystalline silicon film obtained by adding a small amount of the low melting point metal or catalytic metal will be described. Since both showed almost the same crystal form, it seems that both of these results are due to the ease of movement of silicon atoms.
The added metal (both the low melting point metal and the catalyst metal) diffuses in a considerably wide area below the crystallization temperature. This has been confirmed by SIMS (secondary ion mass spectrometry). As a result, the crystallization temperature is lowered in these diffusion regions. And it became clear that a crystal form differs in this direct addition area | region and its diffusion area | region. That is, it was confirmed that the directly added region grew in the vertical direction to the substrate, while the peripheral diffusion region grew in the horizontal direction on the substrate. It is speculated that these are all due to the difference in initial nucleation of crystals. That is, in the directly added portion, these foreign substances become crystal nuclei and crystal growth occurs from there to the columnar shape, whereas in the peripheral diffusion region, the crystal nuclei are directly added portions grown in the above-described vertical direction. This is because it is construed that the growth is inevitably happening laterally in order to start growing from there. Hereinafter, in this specification, the lateral crystal growth region extending from the direct addition region of the low-temperature crystallization catalyst metal to the periphery will be referred to as a “lateral growth” region.

Next, the electrical characteristics of the portion added with a small amount and the laterally grown portion in the vicinity thereof when using the above metal, for example, indium which is a low melting point metal will be described. The electrical characteristics of the portion with a small amount of addition are the same values as those of the film with no conductivity added, that is, the value obtained by crystallization at about 600 ° C. for several tens of hours, and activated due to the temperature dependence of the conductivity. As a result of obtaining the energy, when the addition amount of tin is set to about 10 ¹⁷ atoms / cm ³ to 10 ¹⁸ atoms / cm ³ as described above, the behavior seems to be caused by the level of indium (In). Was not observed. That is, from this experimental fact, it is considered that the above-mentioned concentration can be used as an active layer of a TFT.

  On the other hand, the laterally grown portion has a conductivity that is higher by one digit or more than the directly added portion, and has a considerably high value as a silicon semiconductor having crystallinity. This is thought to be due to the fact that the path direction of the current coincides with the lateral growth direction of the crystal, so that there are few or almost no grain boundaries existing while electrons pass between the electrodes. Consistent with the results. That is, since the movement of the carrier is along the grain boundary of the crystal grown in the shape of a needle or a column, it can be considered that the carrier is easily moved. Further, the concentration of In in the laterally grown region was about an order of magnitude lower than that in the region where In was directly added. This is useful for using a crystalline silicon film without being affected by In.

  Finally, a method applied to the TFT will be described based on the various characteristics described above. Here, as an application field of the TFT, an active matrix liquid crystal display device using the TFT for driving the pixel is assumed.

  As described above, in the recent large-screen active matrix liquid crystal display devices, it is important to suppress the shrinkage of the glass substrate. However, by using the catalytic metal trace addition process for low-temperature crystallization according to the present invention, This is particularly preferable because crystallization can be performed at a temperature sufficiently lower than the strain point. According to the present invention, a portion where amorphous silicon has been used conventionally is added to a silicon having crystallinity by adding a small amount of a low melting point metal or a catalytic metal and crystallizing at about 500 to 550 ° C. for about 4 hours. It can be easily replaced. Of course, it is necessary to change the design rules and the like accordingly, but it is considered that the apparatus and the process can be sufficiently handled by conventional ones, and the merit is great.

  In addition, if the present invention is used, the TFT used for the pixel and the TFT for forming the driver of the peripheral circuit can be separately formed using crystal forms corresponding to the characteristics, and the active liquid crystal display device There are many merits especially in application to. A TFT used for a pixel does not require much mobility, and a smaller off-current has a greater merit than that. Therefore, when using the present invention, a small amount of a low melting point metal or a catalytic metal is added to a region to be a TFT used for a pixel to grow a crystal in the vertical direction, and as a result, many grain boundaries are formed in the channel direction. Thus, the off-state current can be reduced. On the other hand, the TFT that forms the driver of the peripheral circuit needs very high mobility when considering application to a workstation in the future. Therefore, when applying the present invention, a small amount of a low melting point metal or a catalytic metal is added in the vicinity of the TFT forming the driver of the peripheral circuit, and a crystal is grown in one direction therefrom, and the crystal growth direction is adjusted to the channel. By aligning with the current path direction, a TFT having very high mobility can be manufactured. FIG. 4 shows an example in which the Ni concentration after crystallization was examined by SIMS in an example in which a crystalline silicon film was obtained using Ni as the catalyst metal. Referring to FIG. 4, it can be seen that the Ni concentration in the crystal growth portion (Lateral growth) in the direction parallel to the substrate is lower than the Ni concentration in the Ni-added region (Plasma treated). Further, a-Si is data of an amorphous silicon film to which no Ni is added, and is interpreted as a background value. In the case of the present invention as well, it is considered that data having basically the same tendency as the data of FIG. 4 can be obtained. From this, it is useful to use the region where the crystal is grown in the direction parallel to the substrate. Conceivable.

  When a silicon film is crystallized using a Group 3 element, the Group 3 element remains in the film after crystallization, so that a crystalline silicon film having a P-type conductivity is obtained. Can do. Similarly, when crystallization is performed using a Group 5 element, a crystalline silicon film having an N-type conductivity can be obtained. The conductivity of these crystalline silicon films having one conductivity type can be controlled by the amount of Group 3 or Group 5 element introduced during crystallization. Further, an impurity imparting one conductivity type may be added to control the conductivity type and conductivity.

Further, for example, in the case where In, which is a group 3 element, is selectively introduced into a region of 100, and then an amorphous silicon film 104 is formed and further crystallized by heating at 550 ° C. for 4 hours, Crystal growth is performed in a direction parallel to the substrate as indicated by an arrow 105 from the region. At this time, since In diffuses with crystal growth, In exists in the region where crystallization has been performed. Since the concentration is about 2 × 10 ¹⁷ to 2 × 10 ¹⁹ cm ⁻³ , the region crystallizes and becomes P-type. Further, by selecting a diffused position according to the amount of In introduced or crystallization, a P ⁺ region or a P ⁻ region can be obtained. By forming a TFT using this region, it is possible to obtain a TFT having a channel formation region of P ⁺ type or P ⁻ type. Similarly, when Sb which is a Group 5 element is used instead of In described above, a TFT having a channel formation region of N ⁺ type or N ⁻ type can be obtained. Thus, the conductivity type of the channel forming region P ^- type or N ^- to the type are useful can control the V _th of the TFT.

In the present invention, a small amount of the aforementioned low-melting point metal or catalytic metal, which is a trace element for crystallization, is added, and then one-dimensional crystal growth is performed in a direction parallel to the substrate. An electronic device is configured using a region where crystal growth has been performed. In particular, when an insulated gate field effect transistor is formed using a thin-film silicon semiconductor having crystallinity in this region, the direction in which carriers move and the crystal growth direction of the silicon film are roughly aligned in the channel formation region. A TFT having high mobility can be obtained. It is also useful to integrate and form diodes and transistors using a crystalline silicon film that has grown in a direction parallel to the substrate. Furthermore, capacitors, resistors, and the like can be integrated on the same substrate. Moreover, these have another feature that they can be configured using an inexpensive glass substrate.

[Action]
In a semiconductor device using a thin film silicon semiconductor, the movement of carriers is aligned with the grain boundary by roughly aligning the crystal growth direction of the crystalline silicon film grown in needles or columns in the plane direction of the film with the movement direction of carriers. The direction can be along, and the carrier can be moved with high mobility.

  When a non-single crystal silicon semiconductor film having crystallinity that is provided on a substrate and grown in a direction parallel to the substrate surface is used for a TFT, the crystal growth is performed in the direction of the flow of carriers moving in the TFT. By combining with the above direction, the carrier can move along (in parallel) the crystal grain boundary of the crystal grown in a needle shape or column shape, and a TFT having high mobility can be obtained. . Furthermore, since these TFTs can be formed at a low temperature of 600 ° C. or less, an inexpensive glass substrate can be used as the substrate.

In addition, TFTs having the required mobility can be selectively made. In particular,
1. Using a crystalline silicon film grown in a direction parallel to the substrate, a TFT is manufactured so that carriers move in a direction along the crystal grain boundary.
2. Using a crystalline silicon film crystal-grown in a direction parallel to the substrate, a TFT is manufactured so that carriers move across the crystal grain boundary.
3. A TFT is formed in a region where the crystal has grown in a direction perpendicular to the substrate.
4). By partially introducing an element for crystallization, a crystalline silicon film is selectively formed, and by using the crystalline silicon film, a specific portion of the TFT is made a high mobility TFT.
In particular, since the crystalline silicon film in a region away from the region where the element for crystallization is introduced has a one-dimensional orientation, a TFT having a high mobility is utilized using this region. Can be obtained.

In the following examples, an example in which a silicon film is crystallized by adding a small amount of Group 3 element In, Group 5 element Sb, and Group 4 element Sn will be described. Even when using Group 3 or Group 5, or Group 4 elements, or Zn, the same as in the following examples. At this time, the addition amount of these trace elements may be such that the concentration in the silicon film after crystallization is 2 × 10 ¹⁷ to 2 × 10 ¹⁹ cm ⁻³ .

  In this embodiment, a circuit in which a P-channel TFT (PTFT) using a crystalline silicon film and an N-channel TFT (NTFT) are combined on a glass substrate in a complementary manner is formed. The configuration of this embodiment can be used for pixel electrode switching elements, peripheral driver circuits, image sensors, and other integrated circuits in active liquid crystal display devices.

  FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, a silicon oxide base film 102 having a thickness of 2000 mm is formed on a substrate (Corning 7059) 101 by sputtering. Next, a mask 103 formed of a metal mask or a silicon oxide film is provided. The mask 103 exposes the base film 102 in a slit shape in a region indicated by 100. That is, when the state of FIG. 1A is viewed from above, the base film 102 is exposed in a slit shape, and the other portions are masked.

  After the mask 103 is provided, an In thin film having a thickness of 5 to 200 mm, for example, 20 mm, is selectively formed on 100 regions by vapor deposition. Actually, it is difficult to form an In film with a uniform thickness of 20 mm, and it is also difficult to measure the exact thickness. It can be estimated. This step is for introducing a small amount of In, which is a Group 3 element, and crystallizing an amorphous silicon film to be formed later from the region where In is introduced.

  Next, an intrinsic (I-type) amorphous silicon film 104 having a thickness of 500 to 1500 mm, for example, 1000 mm is formed by plasma CVD. Then, this is crystallized by annealing for 4 hours at 550 ° C. or in an inert atmosphere (atmospheric pressure) at 550 ° C. in a hydrogen reducing atmosphere (preferably the partial pressure of hydrogen is 0.1 to 1 atm). . At this time, the crystallization of the crystalline silicon film 104 occurs in the direction perpendicular to the substrate 101 in the region 100 where the In thin film is selectively formed. In regions other than the region 100, crystal growth is performed from the region 100 in the lateral direction (direction parallel to the substrate) as indicated by an arrow 105. For example, when In is introduced into the region indicated by 100 in FIG. 2, crystal growth is performed one-dimensionally as indicated by an arrow 105. The crystal growth is performed in a needle shape or a column shape.

  In order to promote this crystallization and to obtain a denser crystalline silicon film, annealing by lamp heating is performed after the above heat annealing. This annealing is performed using 1.2 μm infrared light. Also, the annealing time is within 5 minutes. Infrared light is efficiently absorbed by silicon, and a great effect can be obtained in improving the film quality of silicon. On the other hand, since it is difficult to be absorbed by the glass substrate, it is possible to obtain the significance that energy is selectively given to silicon and the glass substrate is not heated so much. As light used for annealing by this lamp heating, tungsten halogen lamp light (wavelength: 0.5 μm to 3.5 μm) or the like can be used. A dense crystalline silicon film can be obtained by annealing by this lamp heating. It is also possible to perform annealing using laser light instead of the lamp heating. This annealing by lamp heating has the effect of improving the crystallinity, in particular, greatly reducing defects in the film.

As a result of the above step, the crystalline silicon film 104 can be obtained by crystallizing the amorphous silicon film. Thereafter, element isolation is performed to determine the active layer region in which the source / drain region and the channel formation region of the TFT are formed. In this example, since crystal growth in a direction parallel to the substrate was observed over about 40 μm or more, the length of each active layer (length in the source / drain direction) was set to 40 μm. In this case, the distance between the center of the channel and the position where In is introduced is about 20 μm. By setting this distance, the concentration of In in the active layer (especially the channel formation region) can be selected. it can.

  Next, a silicon oxide film 106 having a thickness of 1000 mm is formed as a gate insulating film by a sputtering method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 350 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example 0.1 or less. To do.

  After this step, the previous annealing by lamp heating is performed again. This is to improve the interface characteristics between the gate insulating film 106 made of a silicon oxide film and the crystalline silicon film 104. Of course, the crystallinity of the crystalline silicon film 104 is further improved by this lamp heating annealing. As is well known, the interface characteristics between the gate insulating film of the insulated gate field effect transistor and the channel formation region (in FIG. 1, 112 and 115 are the crystalline silicon film portions that become the channel formation region) are improved. Specifically, it is important to reduce defects and levels in the region as much as possible. Therefore, annealing by lamp heating performed after the formation of the gate insulating film 106 can obtain a great effect. Further, annealing by laser beam irradiation may be performed instead of lamp heating.

Next, aluminum (containing 0.1 to 2% silicon) having a thickness of 6000 to 8000 mm, for example, 6000 mm is formed by sputtering. Then, patterning is performed to form gate electrodes 107 and 109. Further, the surface of the aluminum electrode is anodized to form oxide layers 108 and 110 on the surface. This anodization was performed in an ethylene glycol solution containing 1 to 5% tartaric acid. The thickness of the obtained oxide layers 108 and 110 was 2000 mm. Note that the oxides 108 and 110 have a thickness for forming an offset gate region in a subsequent ion doping step, and therefore the length of the offset gate region can be determined in the anodic oxidation step. Of course, this gate electrode may have a structure having silicon as a main component, further having a silicide of silicon and metal, one having a metal as a main component, and a stack of silicon and metal.

Next, an impurity imparting one conductivity type is added to the active layer region (which constitutes a source / drain and a channel) by ion doping (ion implantation). In this doping step, impurities (phosphorus and boron) are implanted using the gate electrode 107 and its surrounding oxide layer 108 and the gate electrode 109 and its surrounding oxide layer 110 as masks. As the doping gas, phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used. In the former case, the acceleration voltage is set to 60 to 90 kV, for example, 80 kV, and in the latter case, 40 to 80 kV, for example, 65 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus is 2 × 10 ¹⁵ cm ⁻² and boron is 5 × 10 ¹⁵ . In doping, each region is selectively doped by covering one region with a photoresist. As a result, the N-type impurity region 11
4 and 116, and P-type impurity regions 111 and 113 are formed, and a P-channel TFT (PTFT) region and an N-channel TFT (NTFT) region can be formed.

Thereafter, annealing is performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but other lasers may be used. The laser light is irradiated under an energy density of 200 to 400 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots are irradiated at one place. It is useful to heat the substrate to about 200 to 450 ° C. during the laser light irradiation. In the laser annealing process, since the region which is crystallized before In is diffused by irradiation of the laser beam, recrystallization proceeds easily, impurity imparting P-type doped impurities The regions 111 and 113 and the impurity regions 114 and 116 doped with an impurity imparting N can be easily activated.

  Further, as the annealing method for the source / drain regions, the annealing method by lamp heating described above is also effective. This lamp heating (for example, using 1.2 μm of infrared light) selectively heats silicon as described above, and thus is useful for processes such as this example in which it is desired to avoid heating the glass substrate as much as possible. .

  Subsequently, a silicon oxide film 118 having a thickness of 6000 mm is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the silicon oxide film 118, and a TFT electrode / wiring is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum. 117, 120, and 119 are formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete a semiconductor circuit in which TFTs are configured in a complementary manner. (Figure 1 (D))

  The circuit shown above has a CMOS structure in which PTFT and NTFT are provided in a complementary manner. However, in the above process, two TFTs are formed at the same time, and two independent TFTs are manufactured simultaneously by cutting at the center. Is also possible.

  FIG. 2 shows an outline of FIG. 1D viewed from above. The reference numerals in FIG. 2 correspond to the reference numerals in FIG. As shown in FIG. 2, the direction of crystallization, that is, the direction of crystal growth is the direction indicated by the arrow 105. This direction is a rough direction of the source / drain region (a line direction connecting the source region and the drain region). In this configuration, carriers grow between the source / drain in a needle shape or a column shape during the operation of the TFT. Move along the crystal. That is, the carrier moves substantially along the grain boundary of the needle-like or columnar crystal. Therefore, the resistance received when the carrier moves can be reduced, and a TFT having high mobility can be obtained.

  In this embodiment, as a method for introducing In, a thin film is selectively formed on the base film 102 under the amorphous silicon film 104 (it is difficult to observe as a film because it is extremely thin). Although the method of crystal growth from a part is adopted, a method of selectively forming an In thin film after forming the amorphous silicon film 104 may be used. That is, crystal growth may be performed from the upper surface of the amorphous silicon film or from the lower surface. As a method for introducing In, a method of adding a small amount of In at the time of plasma treatment, In ion implantation, or formation of a silicon film to be crystallized may be used.

  This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. In the following, one pixel will be described, but many other (generally several hundred thousand) pixels are formed with the same structure. Needless to say, the P-channel type may be used instead of the N-channel type. Further, it can be used not only in the pixel portion of the liquid crystal display device but also in the peripheral circuit portion. It can also be used for image sensors and other integrated circuits. That is, as long as it is used with a thin film transistor, its application is not particularly limited.

In this embodiment, the characteristics of the N-channel TFT formed are controlled by using In as a trace element for crystallization and making the crystallized silicon film P ⁻ type. . Here, if Sb is used instead of In, the channel formation region can be made N ⁻ type. The conductivity can be determined by the amount of these trace elements introduced, the distance from the introduced position, and the crystallization conditions (the degree of diffusion varies).

  An outline of the manufacturing process of this example is shown in FIG. In this example, a glass substrate (thickness 1.1 mm, 300 × 400 mm) was used as the substrate 201. First, a base film 203 (silicon oxide) is formed to a thickness of 2000 mm by a sputtering method. Thereafter, in order to selectively introduce In, a mask 203 is formed using a metal mask, a silicon oxide film, a photoresist, or the like. Then, an In thin film is formed by vapor deposition. This In film is formed to a thickness of 5 to 200 mm, for example, 20 mm. In this manner, the trace element In for selectively crystallizing the silicon film into the region 204 is introduced.

  Thereafter, an amorphous silicon film 205 is formed to a thickness of 1000 mm by LPCVD or plasma CVD, dehydrogenated at 400 ° C. for 1 hour, and then crystallized by heat annealing. This annealing step is performed at 550 ° C. for 4 hours in a hydrogen reducing atmosphere (preferably, the hydrogen partial pressure is 0.1 to 1 atm). Further, this heat annealing step may be performed in an inert atmosphere such as nitrogen.

  In this annealing step, since an In film is formed in a partial region (region 204) under the amorphous silicon film 205, crystallization occurs from this portion. During this crystallization, as shown by an arrow in FIG. 3B, silicon crystal growth proceeds in a direction perpendicular to the substrate 201 in the portion 204 where the In thin film is formed. Similarly, as indicated by an arrow, in a region where the In thin film is not formed (region other than the region 205), crystal growth is performed in a direction parallel to the substrate. That is, lateral growth is performed. Thereafter, annealing is performed by lamp heating similar to that in the first embodiment to improve the crystallinity (densification) of the silicon film.

  Thus, the semiconductor film 205 made of crystalline silicon can be obtained. Next, the semiconductor film 205 is patterned to form island-shaped semiconductor regions (TFT active layers). At this time, the concentration of In in the channel formation region 209 can be determined by setting a distance between a portion where the channel formation region 209 is formed and 204 into which In is introduced. That is, if the distance is increased, the In concentration in the channel formation region 209 can be decreased, and if the distance is decreased, the In concentration in the channel formation region can be increased. Of course, in this case, it must be a region where the silicon film 205 is crystallized.

  Further, a gate insulating film (thickness 700 to 1200 mm, typically 1000 mm) 206 of silicon oxide is formed by plasma CVD in an oxygen atmosphere using tetraethoxysilane (TEOS) as a raw material. The substrate temperature is set to 400 ° C. or lower, preferably 200 to 350 ° C., in order to prevent the glass from shrinking or warping. Thereafter, lamp heating by infrared light irradiation is performed for 1 to 5 minutes in the same manner as in Example 1 to improve the interface characteristics between the semiconductor film 205 and the gate insulating film 206.

Next, a gate electrode 207 is formed by forming a known silicon-based film by a CVD method and performing patterning. Thereafter, phosphorus is doped as an N-type impurity by ion implantation, and a source region 208, a channel formation region 209, and a drain region 210 are formed in a self-aligned manner. Then, irradiation with KrF laser light improves the crystallinity of the silicon film whose crystallinity has deteriorated due to ion implantation. At this time, the energy density of the laser beam is set to 250 to 300 mJ / cm ² . By this laser irradiation, the sheet resistance of the source / drain of this TFT becomes 300 to 800 Ω / cm ² . This step can also be performed by infrared lamp heating instead of using laser light.

  Thereafter, an interlayer insulator 211 is formed with silicon oxide, and further, the pixel electrode 212 is formed with ITO. Then, a contact hole is formed, and electrodes 213 and 214 are formed of a chromium / aluminum multilayer film in the source / drain region of the TFT, and one of the electrodes 213 is also connected to the ITO 212. Finally, annealing is performed in hydrogen at 200 to 300 ° C. for 2 hours to complete the hydrogenation of silicon. In this way, the TFT is completed. This process is simultaneously performed in many other pixel regions.

  In the TFT manufactured in this embodiment, a crystalline silicon film grown in the carrier flow direction is used as an active layer constituting a source region, a channel formation region, and a drain region. Since the carriers do not cross, that is, the carriers move along the crystal grain boundaries of the needle-like or columnar crystals, a TFT having high carrier mobility can be obtained.

  This embodiment is an example in which the source / drain is provided in the direction perpendicular to the crystal growth direction in the TFT shown in the second embodiment. That is, in this example, the carrier moves in a direction perpendicular to the crystal growth direction, and the carrier moves so as to cross the crystal grain boundary of the needle-like or columnar crystal. With such a configuration, the resistance between the source / drain can be increased. This is because the carriers must move so as to cross the crystal grain boundaries of the crystals that have grown into needles or columns. In order to realize the configuration of this embodiment, it is only necessary to set the direction in which the TFT is provided in the configuration shown in Embodiment 2.

  In this embodiment, in the structure shown in Embodiment 2, the direction in which the TFT is provided (defined here by a line connecting the source / drain regions. That is, the direction of the TFT is determined by the direction in which carriers flow) is crystalline. The gist is to select the TFT characteristics by setting the crystal growth direction with respect to the substrate surface of the silicon film at an arbitrary angle.

  As described above, when carriers are moved in the crystal growth direction, the carriers move along the crystal grain boundaries, so that the mobility can be improved. On the other hand, when carriers are moved in a direction perpendicular to the crystal growth direction, the carriers must cross a large number of grain boundaries, so that the carrier mobility decreases.

  Therefore, by selecting between these two states, that is, by setting the angle between the crystal growth direction and the carrier movement direction in the range of 0 to 90 °, the carrier mobility can be controlled. . From another viewpoint, the resistance between the source / drain regions can be controlled by setting the angle between the crystal growth direction and the carrier moving direction. Of course, this configuration can also be used for the configuration shown in the first embodiment. In this case, the slit-like In trace addition region 100 shown in FIG. 2 rotates in the range of 0 to 90 °, and the angle between the crystal growth direction indicated by the arrow 105 and the line connecting the source / drain regions is 0 to 90. It will be selected in the range. When this angle is close to 0 °, the mobility can be increased and the electrical resistance between the source / drain can be reduced. When this angle is close to 90 °, the mobility is small and the resistance between the source and drain, that is, the resistance of the channel formation region can be large.

  This example is an example in which, in the manufacturing process of Example 2 shown in FIG. 3, an In thin film is formed on the entire surface of the base film 202, whereby crystal growth is performed in the direction perpendicular to the substrate on the entire surface of the silicon film. In manufacturing the TFT, an In thin film is formed on the entire surface of the base film 202 without providing the mask 203, and thereafter, an amorphous silicon film 205 is formed as described in Example 2, followed by a crystallization step. A TFT is produced.

The schematic cross section of the TFT of this embodiment is not different from that shown in FIG. 3D, but in the active layer in which the source / drain regions 208 and 210 and the channel formation region 209 are formed, needle-like or The growth direction of the columnar crystals is perpendicular to the substrate 201. For this reason, the carriers moving between the source region (208 or 210) and the drain region (210 or 208) move across the crystal grain boundary of the needle-like or columnar crystal. Therefore, the TFT has a slightly high resistance between the source and the drain. Such a TFT has a mobility of 100 cm ² / Vs or less, but has a small off-state current, so that it is an optimal format for a pixel TFT of a liquid crystal display device intended to hold charges.

  However, the TFT as in this embodiment has a problem in yield and reliability because it is difficult to control the concentration of In in the active layer. This problem can be improved by using a method (for example, ion implantation method) that can control the amount of In introduced.

  In this embodiment, crystallization is further promoted by implantation of silicon ions in addition to elements of Group 3 or Group 5 which are trace elements for crystallization of a silicon film by heating. A manufacturing process of this embodiment will be described with reference to FIGS. Unless otherwise specified, the manufacturing conditions and film thickness in each manufacturing process are the same as those described in Example 1.

First, a base film (silicon oxide film) is formed on the glass substrate 101, and further a mask 103 is formed, and selectively formed as a thin film of In, which is a catalytic element for crystallization, as a thin film. Next, the mask 103 is removed, and a non-single crystal silicon film, here an amorphous silicon film 104, is formed by plasma CVD. Next, silicon which is a group 4 element is implanted into the entire surface by ion implantation. At this time, the projected range is set on the substrate side in the vicinity of the interface between the silicon film 104 and the base film 102. The acceleration voltage for ion implantation is 60 kV, and the dose is 2 × 10 ¹⁵ cm ⁻² . As a result, the amorphization is thoroughly performed mainly in the vicinity of the interface between the substrate (including the base film) and the amorphous silicon film 104, and the existence of crystallization nuclei can be eliminated as much as possible.

The reason why Si ions are used here is that Si ions are electrically neutral impurities with respect to silicon. The dose may be 5 × 10 ^{14 to} 5 × 10 ¹⁶ ions cm ⁻² .

  Thereafter, the amorphous silicon film 104 is crystallized by heating at 550 ° C. for 4 hours. At this time, crystal growth occurs in the direction parallel to the substrate as indicated by the arrow 105 from the region 100. This crystal growth is performed in a needle shape or a column shape. During the crystal growth, the crystal component that becomes the nucleus of crystal growth centering on the interface between the substrate and the amorphous silicon film (the crystal component exists as a matter of degree even if it is an amorphous silicon film). Therefore, the crystal growth performed in the direction parallel to the substrate from the region 100 is not hindered by the crystal growth generated from the interface between the silicon film 104 and the base film 102, and thus the orientation is not affected. It is possible to perform crystal growth with good properties, that is, with a uniform crystal growth direction.

  Thereafter, as described in the first embodiment, PTFT and NTFT are formed to complete a complementary TFT circuit. When a TFT is formed in a crystalline silicon film having good orientation as in this embodiment so that the crystal growth direction and the carrier movement direction are substantially aligned, the carrier moves along the crystal grain boundary. Therefore, it is possible to adopt a configuration that is hardly affected by the grain boundary during the movement. That is, high speed operation can be obtained.

  In this example, the crystallinity was further improved, and a TFT with high mobility was obtained in the crystal growth in the direction parallel to the substrate from the introduction region of the group 3 element In. It is considered that the crystal growth in the direction parallel to the substrate was preferentially performed because the crystal component that promotes the crystal growth in the vertical direction to the substrate that hinders the growth was thoroughly removed in advance. In particular, it is considered effective to thoroughly amorphize the vicinity of the interface between the silicon film and the substrate where crystal nuclei exist when the crystal is grown in a columnar shape in a direction perpendicular to the substrate.

  In this example, in an active liquid crystal display device, a peripheral driver circuit is crystallized by adding a small amount of a Group 3 or Group 5 element, and the TFT is shown in the manufacturing process in Example 1 or Example 2. This is an example in which the TFT provided in the portion is constituted by a TFT using known amorphous silicon (amorphous silicon).

As is well known, in an active type liquid crystal display device, a TFT in a peripheral driver circuit portion has a high mobility (100 cm ² / Vs or more) and a TFT capable of flowing a large amount of on-current is required. The TFT provided in the portion is required to have a relatively small mobility (about 10 cm ² / Vs) in order to avoid a malfunction caused by a small off-state current and light irradiation in order to retain charges.

This requirement is satisfied to some extent by forming the peripheral circuit portion with the TFT described in the first and second embodiments and forming the pixel portion with a TFT (a-Si TFT) using a known amorphous silicon film. Is done. However, a TFT using an amorphous silicon film has a mobility of 1 cm ² / Vs or less, so that a problem remains in that respect.

This embodiment is a further development of the embodiment 7. The TFT in the peripheral circuit portion is composed of the TFT having a high mobility of 100 cm ² / Vs or more shown in the embodiment 1 or 2, and the pixel. This is an example in which the TFT of the portion is constituted by the TFT shown in the fifth embodiment.

  In the TFT shown in Example 5, crystal growth is performed in a direction perpendicular to the substrate so that the crystal grain boundaries are perpendicular to the carrier flow so that the carriers cross many crystal grain boundaries. This is a TFT configured as follows. In such a TFT, since the carrier movement is hindered by the crystal grain boundary, the mobility is lowered. However, since the off-state current becomes small, the charge retention rate can be increased, which is suitable as a pixel TFT.

  In this embodiment, if the mobility of the TFT in the peripheral circuit portion is further increased, neutral element ion implantation as shown in Embodiment 7 may be used in the region.

  This example is an example in which Sn, which is a group 4 element, is used as the trace element for promoting crystallization in Example 1 or Example 2. In addition to Sn, C, Ge, and Pb can be used. In this embodiment, Sn is introduced as a thin film by vapor deposition as in the first and second embodiments. However, Sn ions may be implanted into the amorphous silicon film and Sn may be introduced directly into the silicon film. Good.

The manufacturing process of an Example is shown. The outline | summary of an Example is shown. The manufacturing process of an Example is shown. The metal element concentration in the crystalline silicon film is shown.

Explanation of symbols

101 glass substrate 102 base film (silicon oxide film)
103 Mask 104 Silicon film 105 Direction of crystallization 106 Gate insulating film 107 Gate electrode 108 Anodized layer 109 Gate electrode 110 Anodized layer 111 Source / drain region 112 Channel formation region 113 Drain / source region 114 Source / drain region 115 Channel formation Region 116 Drain / source region 117 Electrode 118 Interlayer insulator 120 Electrode 119 Electrode 201 Glass substrate 202 Base film (silicon oxide film)
203 Mask 204 In Small Addition Region 205 Silicon Film 206 Gate Insulating Film 207 Gate Electrode 208 Source / Drain Region 209 Channel Formation Region 210 Drain / Source Region 211 Interlayer Insulator 213 Electrode 214 Electrode 212 ITO (Pixel Electrode)

Claims (3)

A method for manufacturing a semiconductor device having complementary N-channel TFTs and P-channel TFTs using one active layer made of a crystalline silicon film,
Forming an amorphous silicon film on the substrate;
Introducing an element into a part of the amorphous silicon film;
Crystallizing the amorphous silicon film by heating, forming the crystalline silicon film,
Patterning the crystalline silicon film to form the active layer;
Forming a gate insulating film on the active layer;
Forming gate electrodes of the N-channel TFT and the P-channel TFT on the active layer via the gate insulating film;
Forming a first photoresist covering the N-channel TFT;
By selectively doping boron into the active layer using the gate electrode of the P-channel TFT and the first photoresist as a mask, a P-type impurity region is formed in the active layer,
Forming a second photoresist covering the P-channel TFT;
By selectively doping phosphorus into the active layer using the gate electrode of the N-channel TFT and the second photoresist as a mask, an N-type impurity region is formed in the active layer,
One of the P-type impurity regions and one of the N-type impurity regions are in contact with each other in which the element is introduced ,
The elements are B, Al, Ga, In, Tl, Sc, Y, lanthanoid, C, Ge, Sn, Pb, Ti, Zr, Hf, N, P, As, Sb, Bi, V, Nb, Ta, Or a method for manufacturing a semiconductor device, wherein the semiconductor device is Zn . A method for manufacturing a semiconductor device having complementary N-channel TFTs and P-channel TFTs using one active layer made of a crystalline silicon film,
Forming an amorphous silicon film on the substrate;
Introducing an element into a part of the amorphous silicon film;
Crystallizing the amorphous silicon film by heating, forming the crystalline silicon film,
Patterning the crystalline silicon film to form the active layer;
Forming a gate insulating film on the active layer;
Forming gate electrodes of the N-channel TFT and the P-channel TFT on the active layer via the gate insulating film;
Forming a first photoresist covering the N-channel TFT;
By selectively doping boron into the active layer using the gate electrode of the P-channel TFT and the first photoresist as a mask, a P-type impurity region is formed in the active layer,
Forming a second photoresist covering the P-channel TFT;
By selectively doping phosphorus into the active layer using the gate electrode of the N-channel TFT and the second photoresist as a mask, an N-type impurity region is formed in the active layer,
Forming an interlayer insulating film on the N-channel TFT and the P-channel TFT;
The interlayer insulating film to form a contact hole, an electrode or a wiring forming a plurality of connecting with the N-type non-pure product region and the P-type non-pure product area,
Wherein one of one said P-type impurity region of the N-type impurity region is in contact with the portion of the element is introduced,
In the contact portion, one of the electrodes or wiring contacts both the one of the N-type impurity regions and the one of the P-type impurity regions ,
The elements are B, Al, Ga, In, Tl, Sc, Y, lanthanoid, C, Ge, Sn, Pb, Ti, Zr, Hf, N, P, As, Sb, Bi, V, Nb, Ta, Or a method for manufacturing a semiconductor device, wherein the semiconductor device is Zn . According to claim 1 or claim 2, wherein one is in contact portions of said one said P-type impurity region of the N-type impurity region, said than the active layer other than the area where contact with the concentration of the element A method for manufacturing a semiconductor device, which is expensive.

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