JP3375692B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a TFT (thin film transistor) provided on an insulating substrate such as glass and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a semiconductor device having TFTs on an insulating substrate such as glass, active type liquid crystal display devices and image sensors using these TFTs for driving pixels are known.

Thin film silicon semiconductors are generally used for TFTs used in these devices. The thin-film silicon semiconductor is roughly classified into two, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are the most commonly used because they have a low manufacturing temperature, can be relatively easily manufactured by the vapor phase method, and have high mass productivity. Since it is inferior to the silicon semiconductors it has,
In order to obtain higher speed characteristics in the future, establishment of a method for manufacturing a TFT made of a crystalline silicon semiconductor has been strongly demanded. As the crystalline silicon semiconductor, non-single crystalline silicon such as polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, and semi-amorphous silicon having an intermediate state between crystalline and amorphous. Semiconductors are known. Hereinafter, the non-single crystal silicon semiconductor having crystallinity will be referred to as crystalline silicon.

As a method for obtaining these thin film silicon semiconductors having crystallinity, (1) a film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed and crystallized by the energy of laser light. (3) An amorphous semiconductor film is formed in advance and heat energy is applied so that the film has crystallinity. The method is said to be known. However, in the method (1), it is technically difficult to uniformly form a film having good semiconductor physical properties over the entire surface of the substrate, and since the film forming temperature is as high as 600 ° C. or more, it is inexpensive. There was also a cost problem that the glass substrate could not be used. Also, (2)
In the case of the most commonly used excimer laser, the method of (1) has a problem that throughput is low because the irradiation area of the laser beam is small, and the entire surface of a large area substrate is uniformly processed. The laser is not stable enough, and there is a strong sense that it is a next-generation technology. (3)
The method (1) has an advantage of being able to handle a large area as compared with the methods (1) and (2), but it is still necessary to set the heating temperature to a high temperature of 600 ° C. or higher, and an inexpensive glass substrate is used. Considering this, it is necessary to further lower the heating temperature. In particular, in the case of current liquid crystal display devices, the screen size is increasing, and therefore it is necessary to use a large glass substrate as well. When such a large glass substrate is used, shrinkage or distortion in the heating step, which is indispensable for semiconductor fabrication, lowers the accuracy of mask alignment and the like, which is a serious problem. Particularly, in the case of 7059 glass which is most commonly used at present, the strain point is 593 ° C., and the conventional heat crystallization method causes a large deformation. In addition to the problem of temperature, in the present process, the heating time required for crystallization reaches several tens of hours or more, so it is necessary to further shorten the heating time.

[0005]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, in a method of manufacturing a thin film of a crystalline silicon semiconductor using a method of crystallizing a thin film of amorphous silicon by heating, the temperature required for crystallization is lowered and the time is shortened. Its purpose is to provide a process that achieves both. Of course, the crystalline silicon semiconductor manufactured by using the process provided by the present invention has physical properties equal to or higher than those manufactured by the conventional technique and can be used for the active layer region of the TFT. It goes without saying that there is.

BACKGROUND OF THE INVENTION The inventors of the present invention form an amorphous silicon semiconductor film by the CVD method or the sputtering method, and crystallize the film by heating, as described in the section of the conventional technique. Regarding the method, the following experiments and consideration were performed.

First, as an experimental fact, when an amorphous silicon film is formed on a glass substrate and the mechanism of crystallizing this film by heating is examined, crystal growth starts from the interface between the glass substrate and amorphous silicon. It was confirmed that the crystals grow relatively randomly in the film thickness direction.

The above phenomenon is considered to be one of the reasons that the critical nuclei are small in the heterogeneous nucleation at the interface, but more directly, at the interface between the glass substrate and the amorphous silicon film, It is considered that there is a crystal nucleus (a seed that is a basis for crystal growth) that is a basis for crystal growth, and it is considered that the crystal grows from the nucleus. Such crystal nuclei are considered to be impurity metal elements present in a trace amount on the substrate surface, crystal components on the glass surface, or fine irregularities on the surface.

Therefore, it is thought that the crystallization temperature can be lowered by more positively introducing the crystal nuclei, and in order to confirm the effect, a small amount of another metal is formed on the substrate, An experiment was conducted to form a thin film of amorphous silicon on the top and then perform heat crystallization. As a result, a decrease in crystallization temperature was confirmed when several metals were formed on the substrate, and it was expected that crystal growth with foreign particles as crystal nuclei occurred. Therefore, the mechanism of a plurality of impurity metals that could be lowered in temperature was investigated in more detail.

Crystallization can be considered by dividing it into two stages: initial nucleation and crystal growth from the nuclei. Here, the initial nucleation rate is observed by measuring the time until a point-like fine crystal is generated at a constant temperature, and this time is any value in the thin film on which the impurity metal is formed. The case was shortened, and the effect of introducing crystal nuclei on lowering the crystallization temperature was confirmed. And, unexpectedly, the growth of crystal grains after nucleation was examined by changing the heating time, and it was found that after depositing a certain metal, the amorphous silicon thin film deposited on it was deposited. In crystallization, it was observed that the rate of crystal growth after nucleation increased dramatically. This mechanism will be described in detail later.

In any case, due to the above two effects, it has not been possible in the past to form a small amount of a certain kind of metal on a thin film of amorphous silicon and then heat crystallization. It has been found that sufficient crystallinity can be obtained at a temperature of 580 ° C. or lower in about 4 to 8 hours. Examples of the impurity metals having such effects to some extent include indium, thallium, antimony, bismuth,
Tin and lead can be mentioned, but lead was the most effective material in our experiments. Therefore, the description will be limited to the case where lead is added below.

First, to give an example of how much lead has the effect of low temperature crystallization, no treatment is performed.
That is, when a thin film made of amorphous silicon formed by the plasma CVD method is crystallized by heating in a nitrogen atmosphere on a substrate on which a thin film of lead is not formed (Corning 7059), the heating temperature is When the temperature is 600 ° C,
Although a heating time of 10 hours or more was required, when a thin film made of amorphous silicon on a substrate on which a thin film of lead was formed was used, the same crystallization was achieved by heating for about 1 hour. I was able to get the status. In addition, Raman spectroscopy spectrum was utilized for the judgment of crystallization at this time. From this alone, it can be seen that the effect of lead is very large.

[0013]

[Means for Solving the Problems] As can be seen from the above description,
If a thin film of amorphous silicon is formed after a thin film of lead is formed, the crystallization temperature can be lowered and the time required for crystallization can be shortened. Therefore, on the premise that this process is used for manufacturing a TFT, a more detailed description will be added.

First, a method of adding lead will be described. A small amount of lead is added by forming a small amount of a lead metal thin film on a substrate and then forming amorphous silicon, or by directly introducing lead into the amorphous silicon thin film by ion implantation, or Low-temperature crystallization was achieved by any one of the methods in which amorphous silicon was formed into a film and a small amount of lead thin film was formed thereon by sputtering. However, in the case of a method in which amorphous silicon is first formed and then a small amount of lead thin film is formed thereon by vapor deposition, low temperature crystallization cannot be achieved unless a considerably large amount of lead is added. This is because it is largely related to the crystal growth mechanism, and in order to explain it, the crystal growth theory of amorphous silicon and the factors that change when lead is added will be described below.

As described above, in the case of pure amorphous silicon to which a metal such as lead is not added, nuclei are randomly generated from crystal nuclei at the substrate interface or the like, and crystal growth from the nuclei is also random. , (110) or (11) depending on the manufacturing method.
It has been reported in 1) that relatively oriented crystals are obtained, and of course almost uniform crystal growth is observed over the entire thin film.

First, in order to confirm this mechanism, analysis by DSC (differential scanning calorimeter) was performed. An amorphous silicon thin film formed on a substrate by plasma CVD was filled in a sample container with the substrate attached and the temperature was raised at a constant rate. Then,
A clear exothermic peak was observed at around 700 ° C., and crystallization was observed. This temperature naturally shifts when the temperature rising rate is changed, but when it was carried out at a rate of 10 ° C./min, for example, crystallization started from 700.9 ° C. Next, three types of temperature rising rates were measured, and the activation energy of crystal growth after initial nucleation was determined from them by the Ozawa method. Then, a value of about 3.04 eV was obtained. In addition, when the reaction rate equation was obtained by fitting with a theoretical curve, it was found that it was best explained by the disordered nucleation and its growth model, and nuclei were randomly generated from crystal nuclei such as the substrate interface. The validity of the model of crystal growth from nuclei was confirmed.

The same measurement as described above was carried out for the one to which lead was added. Then, when the temperature is raised at a rate of 10 ° C./min, crystallization starts from 625.5 ° C., and the activation energy of crystal growth obtained from the series of measurements is about 2.3 eV, It has also been numerically clarified that crystal growth is easy.

Here, it is relatively easy to consider that the crystallization start temperature is lowered as an effect of the foreign matter as described above. What is the cause of lowering the activation energy for crystal growth? . As the reason for this, the inventors consider the following reasons.

The nucleation rate equation and the crystal growth rate equation in the crystallization of amorphous material have very excellent work left by Avrami et al. According to these equations, both equations at the interface between the matrix phase and the crystal phase are left. The atomic diffusion constant is included in the form of a first-order product, and it is shown that the growth rate is mainly determined by the diffusion rate at a temperature much lower than the melting point. Therefore, it is understood that crystallization can be promoted by increasing the diffusion constant of atoms. As a method for that,
1. The viscosity of the amorphous film is changed to create an environment in which silicon atoms are easier to move. 2. A large number of defects or vacancies are introduced to create an environment in which silicon atoms are easy to move. There are two possibilities. And the lead addition this time is 1. It is assumed that the film viscosity is lowered, or that crystal growth is caused by the liquid phase of lead.

Considering that crystallization is promoted by the above mechanism, it is necessary that at least lead is present in the film, and as described above, lead was formed on the amorphous silicon film. In this case, it is considered that only that portion melts and the amorphous silicon is hardly affected, and it can be understood that low temperature crystallization was not achieved. Further, in the case of the ion implantation or the sputtering method, the treatment is similarly performed from above the amorphous silicon film, but it is possible to perform the low temperature crystallization because it is added with a certain depth in the film. It can be explained consistently by considering.

Next, the crystal morphology of the crystalline silicon film obtained by adding the lead will be described. Lead added to the inside of amorphous silicon diffuses in a fairly wide region at the crystallization temperature. This has been confirmed by SIMS (Secondary Ion Mass Spectroscopy). As a result, the crystallization temperature is lowered in these diffusion regions as well. Then, it has been clarified that the crystal morphology is different between the lead directly added region and the diffusion region. In other words, the crystal morphology of the directly added region isotropically grows relatively randomly in the same manner as in the non-added region, whereas in the peripheral diffusion region, the crystal is almost horizontal to the substrate. It was confirmed that the material grew radially from the added region. It is speculated that these may be due to the difference in the initial nucleation of crystals. That is, the directly added portion is
These foreign matters become crystal nuclei, and the growth occurs randomly from there, whereas in the peripheral diffusion region, the crystal nuclei are the crystals of the directly added portion that grew in the above-mentioned vertical direction, and the growth starts from there. Therefore, it is considered that the crystals are necessarily grown radially. This radial crystal growth is considered to be pseudo-epitaxial because it is close to the crystal growth from the liquid phase because the lead melt is interposed. In addition, the reason why it becomes almost parallel to the substrate is that, except for those parallel to the substrate, it collides with the interface and crystal growth ends there, and as a result only parallel ones are observed. thinking. Hereinafter, in this specification, the lateral crystal growth region extending from the direct addition region of lead to the periphery will be referred to as a “lateral growth” region.

Next, the correlation between the amount of lead added and the crystallinity will be described. Taking the ion implantation method, which is considered to have the highest accuracy as a method capable of controlling the amount, as an example, regarding the amount of lead added, low temperature crystallization was confirmed when the amount of lead added was 1 × 10 ¹⁷ atoms / cm ³ or more. Yes, but 5 × 10
^{When the} amount added is ²¹ atoms / cm ³ or more, the shape of the peak of the Raman spectrum tends to be slightly different from that of the simple substance of silicon. Therefore, 1 × 10 ¹⁷ atoms / cm ^{3 to} 5 × 10 ²¹ atoms can be actually used.
It seems to be in the range of ms / cm ³ . Also, considering that it is used as an active layer of a TFT as a semiconductor property,
It is necessary to suppress this amount to 1 × 10 ²¹ atoms / cm ³ or less. Next, the electrical characteristics of the directly added portion and the lateral growth portion in the vicinity thereof when lead is added will be described. Regarding the electrical characteristics of the directly added portion, regarding the conductivity, a film not added, for example, a film that has been used for crystallization at about 600 ° C. for several tens of hours, or 1000 ° C.
When the activation energy was calculated from the temperature dependence of the conductivity, the amount of lead added was 10 ¹⁷ atoms /
When it was set to about cm ³ to 10 ¹⁸ atoms / cm ³ , it was determined to be about 0.54 eV, and no shift of the Fermi surface was observed. That is, it can be considered that the behavior that is considered to be caused by lead has not occurred. This is presumably because lead has the same genus as silicon and does not have an extra valence electron, so that an amount of this amount has no particular adverse effect. Of course, it is fully conceivable that the addition of an excessively large amount of lead cannot neglect the movement of charges due to the difference in electronegativity and the shape of the electron cloud changes to adversely affect the physical properties. However, no problems have been observed with this amount. That is, from this experimental fact, it is considered that the above concentration can be used as an active layer of a TFT or the like.

On the other hand, the lateral growth portion has a conductivity of about one digit higher than that of the portion to which lead is directly added, and has a considerably high value as a crystalline silicon semiconductor. It is considered that this is because the current passing direction coincided with the lateral growth direction of the crystal, so that there were few or almost no grain boundaries existing between the electrodes while the electrons passed therethrough. In other words, it can be considered that the carriers move along the grain boundaries of the crystals grown in the lateral direction, so that the carriers are easily moved. The lead concentration in the laterally grown region was about one digit lower than that in the region to which lead was directly added. This is useful for utilizing the crystalline silicon film while minimizing the influence of lead.

Finally, a method of applying to a TFT based on the above-mentioned various characteristics will be described. Where TF
As an application field of T, an active matrix type liquid crystal display device using a TFT for driving a pixel is assumed.

As described above, in the recent large-screen active matrix type liquid crystal display device, it is important to suppress the shrinkage of the glass substrate. However, by using the lead addition process of the present invention, the strain point of the glass is reduced. It is possible to crystallize at a sufficiently low temperature as compared with the above, and it is particularly preferable. According to the present invention, in the portion where the amorphous silicon is conventionally used,
By adding a trace amount of lead and crystallizing it at about 500 to 550 ° C. for about 4 to 8 hours, it is possible to easily replace it with crystalline silicon. Needless to say, it is necessary to change the design rules and the like accordingly, but it is considered that the existing equipment for both the equipment and the process can suffice, and its merit is great.

Moreover, according to the present invention, the TFT used for the pixel and the TFT forming the driver of the peripheral circuit are used.
It is also possible to separately form and using the crystal forms according to the characteristics, which is particularly advantageous for application to the active liquid crystal display device. A TFT used for a pixel does not require so much mobility, and a smaller off-current is more advantageous than that. Therefore, when the present invention is used, by directly adding lead to a region to be a channel of a TFT used for a pixel,
It is possible to grow crystals randomly and, as a result, form a large number of grain boundaries in the channel direction to reduce the off current. On the other hand, T which forms the driver of the peripheral circuit
The FT will require extremely high mobility when it is considered to be applied to workstations in the future. Therefore, in the case of applying the present invention, lead is added in the vicinity of the channel of the TFT forming the driver of the peripheral circuit, and a crystal is grown in the lateral direction from that, and the crystal growth direction is aligned with the current path direction of the channel. This makes it possible to fabricate a TFT having extremely high mobility.

In the present invention, a trace amount of lead, which is a trace element for crystallization, is added, and two-dimensional crystal growth is carried out in the direction parallel to the substrate from which a substantially parallel portion is formed. That is, it is characterized in that the electronic device is constructed by utilizing the region where the one-dimensional crystal growth is performed. In particular, when an insulating gate type field effect transistor is formed by using a thin film silicon semiconductor having crystallinity in this region, by roughly aligning the carrier moving direction and the crystal growth direction of the silicon film in the channel forming region thereof. Therefore, a TFT having high mobility can be obtained. Further, it is useful to integrate and form a diode and a transistor by using a crystalline silicon film which is crystal-grown in a direction parallel to this substrate. Furthermore, capacitors, resistors and the like can be integrated on the same substrate. Further, these have another feature that they can be constructed by using an inexpensive glass substrate.

[0028]

As a first function, it is possible to obtain a crystalline silicon film having characteristics equal to or higher than those of conventional ones at low temperature in a short time.

As a second action, in a semiconductor device using a thin film silicon semiconductor, the movement of carriers is made to be a direction along a crystal grain boundary by roughly aligning the crystal growth direction of a crystalline silicon film with the movement direction of carriers. The carrier can be moved with high mobility.

[0030]

【Example】

[Embodiment 1] This embodiment is an example of forming a circuit in which a P-channel TFT (referred to as PTFT) using crystalline silicon and an N-channel TFT (referred to as NTFT) are combined in a complementary type on a glass substrate. . The structure of this embodiment can be used for a switching element of a pixel electrode of an active type liquid crystal display device, a peripheral driver circuit, an image sensor and an integrated circuit.

In particular, a TFT capable of moving carriers at high speed
Since the TFT can be manufactured,
It is extremely meaningful to apply the circuit to the peripheral driver circuit of the active matrix type liquid crystal display device.

FIG. 1 shows a sectional view of the manufacturing process of this embodiment. First, a 2000-Å-thick silicon oxide base film 102 was formed on a substrate (Corning 7059) 101 by a sputtering method. Next, a mask 103 formed of a metal mask or a silicon oxide film is provided. The mask 103 exposes the base film 102 in a slit shape. That is, when the state of FIG. 1A is viewed from above, the underlying film 102 is exposed in a slit shape, and the other portions are masked.

After the mask 103 is provided, a thin film of lead having a thickness of 5 to 200 Å, for example, 20 Å is selectively formed in 100 regions by the sputtering method.

Next, an intrinsic (I type) having a thickness of 500 to 1500 Å, for example, 1000 Å, is formed by the plasma CVD method.
The amorphous silicon film 104 is formed. Then, in a hydrogen reducing atmosphere (preferably, the hydrogen partial pressure is 0.1 to 1 atm) at 550 ° C., or in an inert atmosphere (atmospheric pressure), 5
Crystallize by annealing at 50 ° C. for 4 hours. On this occasion,
In the 100 region where lead is selectively formed, the crystalline silicon film 104 is crystallized in the direction perpendicular to the substrate 101. In the areas other than the area 100, the arrow 1
As indicated by 05, crystal growth is performed from the region 100 in the lateral direction (direction parallel to the substrate).

Further, after this, lamp annealing may be performed by irradiation of infrared light to promote crystallization. Annealing with infrared light (for example, infrared light with a wavelength of 1.2 μm)
Infrared rays are selectively absorbed by the silicon semiconductor, the glass substrate is not heated so much, and the heating of the glass substrate can be suppressed by shortening the irradiation time once, which is extremely useful. When performing lamp annealing, the surface to be irradiated should be kept at about 600 ° C to 1000 ° C.
The lamp is irradiated for several minutes at 600 ° C. and for several seconds at 1000 ° C.

As a result of the above process, the crystalline silicon film 104 can be obtained by crystallizing the amorphous silicon film. After that, a silicon oxide film 106 having a thickness of 1000 Å is formed as a gate insulating film by a sputtering method. For sputtering, silicon oxide is used as a target, and the substrate temperature during sputtering is 200 to 400 ° C., for example 350.
The sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example, 0.1 or less. Subsequently, a thickness of 6000 to 8 is obtained by a sputtering method.
000Å, for example 6000Å aluminum (0.1 to
2% silicon) is deposited. It is desirable that the steps of forming the silicon oxide film 106 and the aluminum film are continuously performed.

Then, the silicon film 104 is patterned to form gate electrodes 107 and 109. Further, the surface of the aluminum electrode is anodized to form oxide layers 108 and 110 on the surface. This anodic oxidation was performed in an ethylene glycol solution containing 1-5% tartaric acid. The resulting oxide layers 108, 110 have a thickness of 200.
It was 0Å. The oxides 108 and 110 are
The thickness of the offset gate region is formed in the subsequent ion doping process, so that the length of the offset gate region can be determined by the anodizing process.

Next, an impurity imparting one conductivity type is added to the active layer region (which constitutes the source / drain and the channel) by the ion doping method. In this doping process, the gate electrode 107 and the oxide layer 10 around it are formed.
8. Impurities (phosphorus and boron) are implanted using the gate electrode 109 and the oxide layer 110 around it as a mask. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as the doping gas, and the acceleration voltage was 60 in the former case.
~ 90 kV, for example 80 kV, in the latter case 40-8
It is set to 0 kV, for example, 65 kV. The dose is 1 × 10 ¹⁵
~ 8 × 10 ¹⁵ cm ^-2 , for example, phosphorus is 2 × 10 ¹⁵ cm ^-2 ,
Boron is 5 × 10 ¹⁵ . Upon doping, one region is covered with a photoresist to selectively dope each element. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 113 are formed, and a P-channel type TFT (PTFT) region and an N-channel type TFT (NTFT) region can be formed. .

After that, annealing is performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but another laser may be used. The laser light irradiation conditions are energy density of 200 to 400 mJ / cm ² ,
For example, 250 mJ / cm ² and ² to 10 per place
Irradiate a shot, for example, two shots. It is useful to heat the substrate to about 200 to 450 ° C. during the irradiation with the laser light. In this laser annealing step, since lead has diffused into the previously crystallized region, recrystallization is easily promoted by irradiation with this laser beam, and impurities doped with P-type imparting impurities are doped. Area 111 and 1
13, and the impurity regions 114 and 116 doped with the impurity imparting N can be easily activated.

This activation may be performed by lamp annealing by irradiation with infrared light. Alternatively, known heating may be used. However, as described above, the annealing by infrared light can suppress the heating of the glass substrate and is extremely useful. When performing lamp annealing, the temperature of the surface to be irradiated should be adjusted to about 600 ° C to 1000 ° C.
When the temperature is 00 ° C., the lamp irradiation is performed for several minutes, and when the temperature is 1000 ° C., the lamp irradiation is performed for several seconds.

Then, a silicon oxide film 11 having a thickness of 6000Å is formed.
8 is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed therein, and a TF is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
T electrodes / wirings 117, 120, and 119 are formed. Finally, annealing was carried out at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete a semiconductor circuit having a complementary TFT structure. (Fig. 1 (D))

The circuit shown above has a CMOS structure in which PTFT and NTFT are provided in a complementary type, but in the above process, two independent TFTs are formed at the same time by forming two TFTs at the same time and cutting them at the center. It is also possible to produce.

FIG. 2 shows an outline of FIG. 1 (D) as seen from above. The reference numerals in FIG. 2 correspond to those in FIG. Figure 2
As shown in FIG. 3, the crystallization direction is the direction indicated by the arrow, and the crystal growth is performed in the direction of the source / drain region (the line direction connecting the source region and the drain region). During operation of the TFT having this structure, carriers move between the source / drain along the crystal growth direction of lateral growth. That is, the carriers move in parallel along the grain boundaries of the laterally grown crystal. Therefore, the resistance received when the carriers move can be reduced, and a TFT having high mobility can be obtained.

In this embodiment, as a method of introducing lead, lead is selectively thinned on the base film 102 under the amorphous silicon film 104 (it is extremely thin, so it is difficult to observe it as a film). However, it is also possible to selectively add lead after the amorphous silicon film 104 is formed. However, in this case, since it is necessary for lead to exist inside the amorphous silicon film, it is preferable to use a technique such as sputtering, ion doping, or ion implantation rather than vapor deposition.
In this case, the lead concentration can be controlled.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active type liquid crystal display device. Although one pixel will be described below, a large number of pixels (generally several hundreds of thousands) are formed in the same structure. Also, N
It goes without saying that the P-channel type may be used instead of the channel type. Further, instead of being provided in the pixel portion of the liquid crystal display device, it can be used in the peripheral circuit portion. It can also be used for image sensors and other devices. That is, if it is used as a thin film transistor, its use is not particularly limited.

An outline of the manufacturing process of this embodiment is shown in FIG.
In this embodiment, Corning 70 is used as the substrate 201.
59 glass substrate (thickness 1.1 mm, 300 x 400 m
m) was used. First, the base film 203 (silicon oxide) is formed to a thickness of 2000 Å by a sputtering method. After that, in order to selectively introduce lead, a mask 203 is formed with a metal mask, a silicon oxide film, a photoresist, or the like. Then, by the sputtering method, the thickness of 5
A thin film of 200 Å, for example, 20 Å lead was formed.

After this, the LPCVD method or plasma C
An amorphous silicon film 205 is formed to a thickness of 1000 Å by the VD method, dehydrogenated at 400 ° C. for 1 hour, and then crystallized by heating annealing. This annealing step was performed at 550 ° C. for 4 hours in a hydrogen reducing atmosphere (preferably, the partial pressure of hydrogen is 0.1 to 1 atm). Further, this heat annealing step may be performed in an inert atmosphere such as nitrogen.

In this annealing step, lead is formed in a part of the region under the amorphous silicon film 205, and that part is in a state close to a molten state, so that the diffusion rate of silicon increases and the temperature becomes low. The crystal growth starts from. During this crystallization, FIG.
As shown by the arrow in (B), a portion 2 where lead is deposited
In 04, silicon crystal growth proceeds in the direction perpendicular to the substrate 201. Similarly, as indicated by an arrow, in a region where lead is not formed (a region other than the region 205), crystal growth is performed in a direction parallel to the substrate.

Thus, the semiconductor film 2 made of crystalline silicon
05 can be obtained. Next, the semiconductor film 205 is patterned to form an island-shaped semiconductor region (active layer of TFT).
To form. Furthermore, tetra-ethoxy-silane (TEO
S) as a raw material by a plasma CVD method in an oxygen atmosphere by a silicon oxide gate insulating film (thickness 70 to 120 n
m, typically 100 nm) 206. The substrate temperature is 400 ° C. or lower, preferably 200 to 350 ° C., in order to prevent the glass from shrinking or warping.

Next, a known film containing silicon as a main component is formed by the CVD method, and patterning is performed.
A gate electrode 207 is formed. After that, phosphorus is implanted as an N-type impurity by an ion doping method to form the source region 208, the channel formation region 209, and the drain region 210 in a self-aligned manner. Then, by irradiating the KrF laser beam, the crystallinity of the silicon film whose crystallinity is deteriorated due to the ion doping is improved. At this time, the energy density of the laser light is 250 to 300 mJ /
cm ² By this laser irradiation, this TFT
Source / drain sheet resistance is 300-800Ω /
It becomes cm ² .

After that, the interlayer insulator 21 is made of silicon oxide.
1 is formed, and the pixel electrode 212 is further formed of ITO. Then, a contact hole is formed and TF
Electrodes 213 and 214 are formed in the source / drain regions of T by a chromium / aluminum multilayer film, and one of these electrodes 213 is also connected to the ITO 121. Finally, anneal in hydrogen at 200-300 ° C for 2 hours,
Complete hydrogenation of silicon. In this way, the TFT
To complete. This step is simultaneously performed on many other pixel regions at the same time.

The TFT manufactured in this example uses a crystalline silicon film which is crystal-grown in the carrier flow direction as an active layer forming a source region, a channel forming region and a drain region. Since the carriers do not cross over, that is, the carriers move radially, and even within them, move along the crystal grain boundaries of the crystals that are substantially parallel to each other, it is possible to obtain a TFT with high carrier mobility. The TFT manufactured in this example is an N-channel type,
The mobility was 90 to 130 (cm ² / Vs). Compared with the conventional migration of 80 to 100 (cm ² / Vs) to an N-channel TFT using a crystalline silicon film obtained by crystallization by thermal annealing at 600 ° C. for 48 hours, this is This is a great improvement in characteristics.

A P-channel TFT was manufactured by the same manufacturing method as in the above step, and its mobility was measured to be 50 to 80 (cm ² / Vs). This is also a P-channel TFT using a crystalline silicon film obtained by crystallization by conventional thermal annealing at 600 ° C. for 48 hours.
This is a great improvement in characteristics in comparison with the movement of 30 to 60 (cm ² / Vs).

[Embodiment 3] This embodiment is an example in which the source / drain is provided in the TFT shown in Embodiment 2 in a direction substantially perpendicular to the crystal growth direction. That is, this is an example in which the moving direction is perpendicular to the crystal growth direction and the carriers move so as to cross the crystal grain boundaries of the crystals in the lateral growth portion. With such a structure, the resistance between the source and the drain can be increased. this is,
This is because the carriers must move so as to cross the crystal grain boundaries of the crystals radially extending in the lateral growth portion.
In order to realize the structure of this embodiment, it is sufficient to simply set the orientation of the TFT in the structure shown in the second embodiment.

[Embodiment 4] In this embodiment, in the structure shown in Embodiment 2, the direction in which a TFT is provided (source / source here)
It is defined by the line connecting the drain regions. That is, the characteristic of the TFT is selected by setting the direction of the TFT depending on the direction of carrier flow) at an arbitrary angle with the crystal growth direction of the crystalline silicon film with respect to the substrate surface.

As described above, when carriers are moved in the crystal growth direction, the carriers move along the crystal grain boundaries, so that the mobility can be improved. on the other hand,
When carriers are moved in a direction perpendicular to the crystal growth direction, the carriers have to cross a large number of grain boundaries, so that the mobility of carriers decreases.

Therefore, between these two states, that is, the angle between the crystal growth direction and the moving direction of carriers is 0 to 90.
The carrier mobility can be controlled by setting in the range of °. From another point of view, the resistance between the source / drain regions can be controlled by setting the angle between the crystal growth direction and the carrier movement direction. Of course, this structure can also be used for the structure shown in the first embodiment. In this case, the slit-shaped lead trace amount addition region 100 shown in FIG. 2 rotates in the range of 0 to 90 °, and the angle between the crystal growth direction shown by the arrow 105 and the line connecting the source / drain regions is 0 to 90. ° will be selected in the range. When the angle is close to 0 °, the mobility is high and the electric resistance between the source / drain can be low. When this angle is close to 90 °, the mobility can be low and the resistance between the source and the drain can be large .

[0058]

[Effect] When a non-single crystal silicon semiconductor film having crystallinity provided on a substrate and crystal-grown in a direction parallel to the substrate surface is used for a TFT, the direction of carrier flow moving in the TFT is crystal-grown. It is possible to adopt a configuration in which the carrier movement moves along (parallel to) the grain boundary of the laterally grown crystal by combining with the direction in which
A TFT having high mobility can be obtained. As for the manufacturing method, the conventional process can be used almost as it is, except that a small amount of lead is added, and the crystallization is required as compared with the conventional manufacturing method of the non-single crystal silicon semiconductor film having crystallinity. It is possible to lower the temperature and shorten the time.

In this specification, a planar type example is used as the element structure. Therefore, as a substrate,
An example in which a glass substrate or a substrate on which an insulating base film is formed is used is shown. However, as is clear from the idea, the substrate in the present invention is a glass substrate on which a conductive film is formed, and in the case of a bottom gate type TFT, a gate and a gate insulating film are provided. Even if it exists, it can be used as a substrate.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of an example.

FIG. 2 shows an outline of an example.

FIG. 3 shows an outline of an example.

[Explanation of symbols] 101 glass substrate 102 Base film (silicon oxide film) 103 mask 104 Silicon film 105 Crystallization direction 106 Gate insulation film 107 Gate electrode 108 anodized layer 109 Gate electrode 110 Anodized layer 111 source / drain region 112 channel formation region 113 drain / source region 114 source / drain region 115 channel formation region 116 drain / source region 117 electrodes 118 Interlayer insulation 120 electrodes 119 electrodes 201 glass substrate 202 Base film (silicon oxide film) 203 mask 204 Lead trace addition area 205 Silicon film 206 Gate insulation film 207 Gate electrode 208 source / drain region 209 channel formation region 210 drain / source region 211 Interlayer insulator 213 electrode 214 electrodes 212 ITO (pixel electrode)

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/20 H01L 21/265

Claims (8)

(57) [Claims] 1. An amorphous silicon film is formed on an insulating surface, lead is selectively added to the amorphous silicon film by ion doping or ion implantation, and the amorphous silicon film is heated. A thin film transistor characterized in that a crystalline silicon film is formed by growing crystals from the lead-added region in a direction parallel to a substrate, and a source region, a drain region, and a channel formation region are formed from the crystalline silicon film. A method for manufacturing a semiconductor device having: 2. An amorphous silicon film is formed on an insulating surface, lead is selectively added to the amorphous silicon film by ion doping or ion implantation, and the amorphous silicon film is heated. Crystals are grown in a direction parallel to the substrate from the lead-added region to form a crystalline silicon film, the crystalline silicon film is irradiated with infrared light, and the crystalline silicon film is used as a source region and a drain region. And a method for manufacturing a semiconductor device having a thin film transistor, which comprises forming a channel formation region. 3. An amorphous silicon film is formed on an insulating surface, and lead is selectively added to the amorphous silicon film at a concentration of 1 × 10 ¹⁷ atom.
s / cm ³ to 1 × 10 ¹⁸ atoms / cm ³ , and the amorphous silicon film is heated to grow crystals in the direction parallel to the substrate from the region to which the lead is added to obtain crystalline silicon. A method for manufacturing a semiconductor device having a thin film transistor, which comprises forming a film, and forming a source region, a drain region, and a channel formation region from the crystalline silicon film. 4. An amorphous silicon film is formed on an insulating surface, and lead is selectively added to the amorphous silicon film at 1 × 10 ¹⁷ atom.
s / cm ³ to 1 × 10 ¹⁸ atoms / cm ³ , and the amorphous silicon film is heated to grow crystals in the direction parallel to the substrate from the region to which the lead is added to obtain crystalline silicon. A method for manufacturing a semiconductor device having a thin film transistor, which comprises forming a film, irradiating the crystalline silicon film with infrared light, and forming a source region, a drain region, and a channel formation region from the crystalline silicon film. 5. An amorphous silicon film is formed on an insulating surface, and lead is selectively added to the amorphous silicon film by ion doping or ion implantation at 1 × 10 ¹⁷ atoms / cm ³ -1.
A concentration of × 10 ¹⁸ atoms / cm ³ , and the amorphous silicon film is heated to grow a crystal in a direction parallel to the substrate from the lead-added region to form a crystalline silicon film. A method for manufacturing a semiconductor device having a thin film transistor, which is characterized in that a source region, a drain region, and a channel formation region are formed from a crystalline silicon film. 6. An amorphous silicon film is formed on an insulating surface, and lead is selectively added to the amorphous silicon film by ion doping or ion implantation at 1 × 10 ¹⁷ atoms / cm ³ -1.
A concentration of × 10 ¹⁸ atoms / cm ³ , and the amorphous silicon film is heated to grow a crystal in a direction parallel to the substrate from the lead-added region to form a crystalline silicon film. A method for manufacturing a semiconductor device having a thin film transistor, which comprises irradiating a crystalline silicon film with infrared light to form a source region, a drain region and a channel formation region from the crystalline silicon film. 7. The method according to any one of claims 1 to 6,
The method for manufacturing a semiconductor device having a thin film transistor, wherein the channel formation region is different from the lead-added region. 8. forming a thin film of lead selection択的over an insulating surface, wherein the insulating surface and an amorphous silicon film is formed in contact with a thin film of the lead, heating the amorphous silicon film, Crystals are grown from the lead thin film in a direction parallel to the substrate to form a crystalline silicon film, the crystalline silicon film is irradiated with infrared light, and an impurity region and a channel region are formed from the crystalline silicon film. A method of manufacturing a semiconductor device for forming a CMOS including a P-channel thin film transistor and an N-channel thin film transistor, wherein an interface between the impurity regions of the P-channel thin film transistor and the N-channel thin film transistor overlaps with the lead thin film. A method for manufacturing a semiconductor device having a thin film transistor, wherein the channel formation region does not overlap with the lead thin film.