JP3926335B2 - Flip chip mounting body and circuit board therefor - Google Patents

Flip chip mounting body and circuit board therefor Download PDF

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JP3926335B2
JP3926335B2 JP2004016423A JP2004016423A JP3926335B2 JP 3926335 B2 JP3926335 B2 JP 3926335B2 JP 2004016423 A JP2004016423 A JP 2004016423A JP 2004016423 A JP2004016423 A JP 2004016423A JP 3926335 B2 JP3926335 B2 JP 3926335B2
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electrode
circuit board
circuit
chip mounting
semiconductor element
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JP2004120000A (en
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謙治 森本
博 越智
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

本発明はフリップチップ実装体およびそのための回路基板に関し、詳しくはフリップチップ実装に適した電極構造に関する。   The present invention relates to a flip chip mounting body and a circuit board therefor, and more particularly to an electrode structure suitable for flip chip mounting.

近年、電子回路は高密度化が進んでおり、実装されるデバイスには面積および接続抵抗の低減が強く求められている。高密度実装を達成する１つの手段にフリップチップ実装があり、そのための実装方法が各種あるなかで、リペアの容易さや近年クローズアップされている無鉛化を考えると、ＳＢＢ方式（Stud Bump Bonding ）は望ましい工法である。ＳＢＢ方式とは、半導体素子上に金などの材料を用いてワイヤーボンディング手法により突起電極を形成し、その突起電極と回路基板上の電極とを導電性樹脂により接続する工法である。   In recent years, electronic circuits have been increased in density, and devices to be mounted are strongly required to reduce area and connection resistance. One of the means to achieve high-density mounting is flip-chip mounting, and there are various mounting methods for that purpose. Considering the ease of repair and lead-free products that have been highlighted recently, the SBB method (Stud Bump Bonding) is This is a desirable method. The SBB method is a method of forming a protruding electrode by a wire bonding method using a material such as gold on a semiconductor element, and connecting the protruding electrode and an electrode on a circuit board with a conductive resin.

図３は従来のフリップチップ実装体を示す。実装に際しては、回路基板１１上にスクリーン印刷などの方法によってペースト状電極材料を印刷し、この電極材料が焼結する温度で回路基板１１を焼成することにより、回路基板１１上に回路電極１２を形成する。一方で、半導体素子１３上にワイヤーボンディングなどの方法により突起電極１４を形成し、その突起電極１４上に転写などの方法によって導電性樹脂１５の層を形成する。そして、回路基板１１と半導体素子１３とを高精度に位置合わせし、適当な荷重をかけることにより、回路基板１１上に半導体素子１３を実装する。   FIG. 3 shows a conventional flip chip mounting body. In mounting, the circuit electrode 11 is printed on the circuit board 11 by printing a paste-like electrode material on the circuit board 11 by a method such as screen printing, and firing the circuit board 11 at a temperature at which the electrode material is sintered. Form. On the other hand, a protruding electrode 14 is formed on the semiconductor element 13 by a method such as wire bonding, and a layer of the conductive resin 15 is formed on the protruding electrode 14 by a method such as transfer. Then, the semiconductor element 13 is mounted on the circuit board 11 by aligning the circuit board 11 and the semiconductor element 13 with high accuracy and applying an appropriate load.

しかしながら、上記した従来の実装方法には次のような問題があった。第１に、近年は半導体素子１３の電極ピッチが狭くなる一方であり、それに伴って回路基板１１上の電極ピッチも狭くすることが要求されている。ところが、従来のスクリーン印刷方法ではピッチを３００μｍとするのが限界であって、それ以下のピッチでの印刷は非常に困難であり、ショートや断線が多発して歩留まりが低くなる原因となっている。   However, the conventional mounting method described above has the following problems. First, in recent years, the electrode pitch of the semiconductor element 13 is becoming narrower, and accordingly, the electrode pitch on the circuit board 11 is also required to be narrowed. However, in the conventional screen printing method, the limit is to set the pitch to 300 μm, and printing at a pitch smaller than that is very difficult, causing frequent shorts and disconnections, resulting in a low yield. .

第２に、半導体素子１３の電極ピッチが狭くなると、半導体素子１３の突起電極１４上に転写する導電性樹脂１５の量のコントロールが非常に困難になり、特にショートの危険性が増す。ショートを防ぐために導電性樹脂１５の量を従来よりも低減するようにしているが、回路電極１２は電極材料が横に拡がってしまうため、例えば電極ピッチ１００μｍ以下では断面が半円状を呈しており、このような形状の回路電極１２に対してフリップチップ実装を行うと、図３に示したように回路電極１２から導電性樹脂１５がはみ出し、隣接した回路電極１２からはみ出した導電性樹脂１５とショートすることがある。   Secondly, when the electrode pitch of the semiconductor element 13 is narrowed, it becomes very difficult to control the amount of the conductive resin 15 transferred onto the protruding electrode 14 of the semiconductor element 13, and the risk of a short circuit increases. In order to prevent short circuit, the amount of the conductive resin 15 is reduced as compared with the conventional case. However, since the electrode material of the circuit electrode 12 spreads sideways, for example, when the electrode pitch is 100 μm or less, the cross section has a semicircular shape. When flip-chip mounting is performed on the circuit electrode 12 having such a shape, the conductive resin 15 protrudes from the circuit electrode 12 as shown in FIG. 3, and the conductive resin 15 protrudes from the adjacent circuit electrode 12 as shown in FIG. May be shorted.

このため、半導体素子の電極ピッチが狭い場合も安定してフリップチップ実装できるようにすることが課題となっていた。   For this reason, it has been a problem to enable stable flip-chip mounting even when the electrode pitch of the semiconductor element is narrow.

上記課題を解決するために本発明は、(ａ)光重合性物質を含んだペースト状の電極材料を用いて回路基板上に電極材料膜を所定の乾燥膜厚にて形成する工程、(ｂ)電極材料膜を露光し現像する工程、(ｃ)現像した電極材料膜を焼成する工程、(ｄ)上記工程により形成された回路電極上に半導体素子をフリップチップ実装する工程を行なうもので、これにより、回路基板上に周縁部が反った回路電極を形成して、その凹面を受け皿として、導電性樹脂のはみ出しを来たすことなく、半導体素子をフリップチップ実装することが可能になる。その結果、ショートの発生を皆無にすることができ、信頼性の高いフリップチップ実装体を実現できる。   In order to solve the above problems, the present invention includes (a) a step of forming an electrode material film on a circuit board with a predetermined dry film thickness using a paste-like electrode material containing a photopolymerizable substance, (b) ) Exposing and developing the electrode material film, (c) firing the developed electrode material film, (d) performing a step of flip-chip mounting the semiconductor element on the circuit electrode formed by the above steps, As a result, a circuit electrode having a curved peripheral edge is formed on the circuit board, and the semiconductor element can be flip-chip mounted without causing the conductive resin to protrude using the concave surface as a tray. As a result, the occurrence of a short circuit can be eliminated and a highly reliable flip chip mounting body can be realized.

すなわち、本発明のフリップチップ実装体は、突起電極が形成された半導体素子を導電性樹脂を用いて回路基板上に実装したフリップチップ実装体であって、前記半導体素子の突起電極が接続された回路基板上の回路電極が、金属材料とガラスを無機成分として含有し、かつ重合性物質と光重合開始剤を有機成分として含有した電極材料膜を焼成することにより周縁部が基板表面から離間する方向に反った凹状に形成され、電極どうし当接させるに先立っていずれかの電極に配置された前記導電性樹脂を当接後も凹面に保持したことを特徴とする。 That is, the flip chip mounting body of the present invention is a flip chip mounting body in which a semiconductor element on which a protruding electrode is formed is mounted on a circuit board using a conductive resin, and the protruding electrode of the semiconductor element is connected to the flip chip mounting body. A circuit electrode on a circuit board contains a metal material and glass as inorganic components, and a peripheral portion is separated from the substrate surface by firing an electrode material film containing a polymerizable substance and a photopolymerization initiator as organic components. The conductive resin is formed in a concave shape that is warped in the direction, and the conductive resin disposed on any of the electrodes is held on the concave surface after the contact before contacting the electrodes.

また本発明の回路基板は、突起電極が形成された半導体素子を導電性樹脂を用いてフリップチップ実装するための回路基板であって、前記半導体素子の突起電極が接続される回路電極が、電極領域に成膜した、金属材料とガラスを無機成分として含有し、かつ重合性物質と光重合開始剤を有機成分として含有した電極材料膜を焼成することにより周縁部が基板表面から離間する方向に反った凹状に形成され、電極どうし当接させるに先立っていずれかの電極に配置される前記導電性樹脂を当接後も凹面に保持するように構成されたことを特徴とする。 The circuit board of the present invention is a circuit board for flip-chip mounting a semiconductor element on which a protruding electrode is formed using a conductive resin, and the circuit electrode to which the protruding electrode of the semiconductor element is connected is an electrode. In the direction in which the peripheral part is separated from the substrate surface by firing an electrode material film containing a metal material and glass as inorganic components and containing a polymerizable substance and a photopolymerization initiator as organic components, formed in a region The conductive resin is formed in a warped concave shape, and is configured to hold the conductive resin disposed on any of the electrodes prior to contact between the electrodes even after the contact.

回路基板としてはセラミックを用いることができる。この回路基板には、上記したような半導体素子を搭載するための回路電極を備えた回路はもちろんのこと、半導体素子以外の部品を搭載するための回路や、別の基板への接続のための回路を設けることができる。   Ceramic can be used as the circuit board. In this circuit board, not only a circuit having a circuit electrode for mounting a semiconductor element as described above, but also a circuit for mounting a component other than a semiconductor element, or for connection to another board A circuit can be provided.

電極材料は少なくとも、金や銀や銅などの金属材料とガラスを無機成分として含み、重合性物質であるモノマーやポリマー、光重合開始剤を有機成分として含有したものを用いる。形成した回路電極の表面にニッケルや金などのメッキを施してもよい。   The electrode material includes at least a metal material such as gold, silver, or copper and glass as inorganic components and a monomer or polymer that is a polymerizable substance, or a photopolymerization initiator as an organic component. The surface of the formed circuit electrode may be plated with nickel or gold.

半導体素子は、金、アルミニウム、銅、半田などの金属材料で突起電極が形成されたものを用いることができる。突起電極の形成方法は、ワイヤーボンディングやメッキなど、工法を問わない。   As the semiconductor element, one having a protruding electrode formed of a metal material such as gold, aluminum, copper, or solder can be used. The method for forming the protruding electrode may be any method such as wire bonding or plating.

導電性樹脂は、半導体素子上の突起電極と回路基板上の回路電極とを接続する金や銀や銅など導電性成分を含有していればよく、樹脂自体は熱硬化性でも熱可塑性でもよく、その種類は問わない。   The conductive resin only needs to contain a conductive component such as gold, silver, or copper that connects the protruding electrode on the semiconductor element and the circuit electrode on the circuit board. The resin itself may be thermosetting or thermoplastic. The type is irrelevant.

詳細には、上記した工程(ａ)では、回路基板上にペースト状の電極材料を印刷して電極材料膜を形成する。電極材料は半導体素子が実装される実装領域のみ印刷すればよく、それ以外の領域については、従来法により予め回路パターンを形成しておくなどの工法をとればよい。実装領域にベタ印刷すればよいので、従来のスクリーン印刷などのラフな印刷法で十分である。印刷後に電極材料の流動を防ぐために適度な温度で乾燥させる。ただし、乾燥後に所定の膜厚、望ましくは１０〜２０μｍになるように印刷版および印刷条件を設定する。   Specifically, in the step (a) described above, an electrode material film is formed by printing a paste-like electrode material on a circuit board. The electrode material may be printed only in the mounting region where the semiconductor element is mounted, and in other regions, a method of forming a circuit pattern in advance by a conventional method may be taken. A rough printing method such as conventional screen printing is sufficient because solid printing may be performed in the mounting area. In order to prevent the electrode material from flowing after printing, it is dried at an appropriate temperature. However, the printing plate and printing conditions are set so as to have a predetermined film thickness after drying, preferably 10 to 20 μm.

工程(ｂ)では、印刷・乾燥後の回路基板に、半導体素子が搭載される電極領域のみ光が透過するように形成されたガラスマスクなどを位置合わせし、波長３２０〜３７０ｎｍの紫外線を３００〜５００ｍＪ照射して、紫外線が透過する電極領域の重合性物質を光重合開始剤により反応開始させてポリマー化させる。適当時間後に未反応の重合性物質が溶解する溶液を用いて基板全体を現像することにより、電極領域以外の膜を除去し、電極領域の膜を残留させる。なおこの時、膜厚を調整しておくことにより、光が届きにくい基板寄り部分の重合性物質を重合不十分のまま残留させ、現像時に非電極領域の膜除去跡から侵食させて、電極領域の電極材料膜を断面形状が台形を呈するように形成する。膜厚が薄いと電極領域の重合性物質が全て重合して台形断面形状が得られないので、前述した膜厚が必要となる。   In the step (b), a glass mask or the like formed so that light is transmitted only through the electrode region on which the semiconductor element is mounted is aligned with the printed / dried circuit board, and ultraviolet rays having a wavelength of 320 to 370 nm are 300 to 300 nm. Irradiation with 500 mJ is performed to polymerize the polymerizable substance in the electrode region through which ultraviolet rays are transmitted by using a photopolymerization initiator. The entire substrate is developed using a solution in which the unreacted polymerizable substance dissolves after an appropriate time, thereby removing the film other than the electrode region and leaving the film in the electrode region. At this time, by adjusting the film thickness, the polymerizable material in the portion near the substrate where light is difficult to reach remains with insufficient polymerization, and is eroded from the film removal trace of the non-electrode area during development, so that the electrode area The electrode material film is formed so that the cross-sectional shape has a trapezoidal shape. If the film thickness is thin, all the polymerizable substances in the electrode region are polymerized and a trapezoidal cross-sectional shape cannot be obtained, so the above-described film thickness is required.

工程(ｃ)では、露光・現像後の回路基板を前記電極材料が焼結する温度で焼成して、回路基板上に回路電極を焼き付ける。このとき台形断面形状の電極材料膜がやや収縮するため、形成される回路電極は端部がやや反り返り（この部分はエッジカールと呼ばれる）、断面が円弧状をなる形状となる。焼成後に電極表面の保護を目的としてニッケルや金などのメッキを施してもよい。   In step (c), the circuit board after exposure and development is baked at a temperature at which the electrode material sinters, and the circuit electrode is baked on the circuit board. At this time, since the electrode material film having a trapezoidal cross-sectional shape slightly contracts, the end of the formed circuit electrode slightly warps (this portion is called an edge curl), and the cross-section has a circular arc shape. After firing, plating such as nickel or gold may be performed for the purpose of protecting the electrode surface.

工程(ｄ)では、回路電極が焼き付けられた回路基板上に、突起電極が形成された半導体素子を導電性樹脂を用いてフリップチップ実装する。このときには、回路電極のエッジカールが壁として機能するため、導電性樹脂のはみ出しは防止される。   In the step (d), the semiconductor element on which the protruding electrode is formed is flip-chip mounted on the circuit board on which the circuit electrode is baked using a conductive resin. At this time, since the edge curl of the circuit electrode functions as a wall, the conductive resin is prevented from protruding.

本発明によれば、回路基板上にエッジカールした回路電極を形成し、この回路電極に半導体素子の突起電極を導電性樹脂を用いて接続するようにしたため、回路電極を受け皿として導電性樹脂のはみ出しを防止することができ、ショートが発生しない、信頼性の高いフリップチップ実装体を実現できる。   According to the present invention, the edge-curled circuit electrode is formed on the circuit board, and the protruding electrode of the semiconductor element is connected to the circuit electrode by using the conductive resin. It is possible to prevent a protrusion and to realize a highly reliable flip chip mounting body that does not cause a short circuit.

以下、本発明の実施の形態を図面を参照しながら具体的に説明する。
図１は本発明の一実施形態におけるフリップチップ実装体を製造する第１の実装方法を説明する工程断面図である。 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a process cross-sectional view illustrating a first mounting method for manufacturing a flip chip mounting body according to an embodiment of the present invention.

図１(ａ)に示すように、回路基板１上の半導体素子搭載エリアに光重合性物質を含んだペースト状の電極材料２を印刷し、印刷後の電極材料２が流動しないように適度な温度にて乾燥させる。このとき電極材料２は、乾燥後の膜厚が１０〜２０μｍになるように印刷版、条件を設定して印刷する。   As shown in FIG. 1 (a), a paste-like electrode material 2 containing a photopolymerizable substance is printed on a semiconductor element mounting area on a circuit board 1 so that the electrode material 2 after printing does not flow. Dry at temperature. At this time, the electrode material 2 is printed by setting the printing plate and conditions so that the film thickness after drying becomes 10 to 20 μm.

次に、図１(ｂ)に示すように、電極材料２の膜の上に所望の回路パターン形状にて光が透過するように開口部３ａが形成されたガラスマスク３を、回路基板１に対して位置合わせして設置する。ここでは開口部３ａは電極領域に相応する５０μｍ幅、１００μｍピッチである。そして、ガラスマスク３の上方から波長３２０〜３７０ｎｍのＵＶ（紫外線）を３００〜５００ｍＪ照射する。   Next, as shown in FIG. 1B, a glass mask 3 having an opening 3 a formed on the film of the electrode material 2 so that light is transmitted in a desired circuit pattern shape is formed on the circuit board 1. Install it in alignment. Here, the openings 3a have a width of 50 μm and a pitch of 100 μm corresponding to the electrode region. Then, 300 to 500 mJ of UV (ultraviolet light) having a wavelength of 320 to 370 nm is irradiated from above the glass mask 3.

このことにより、開口部３ａを通過したＵＶによって、図１(ｃ)に示すように、電極領域２ａの電極材料２で光重合性物質（光重合開始剤，モノマー，ポリマー）が反応してポリマー化が進み、非電極領域２ｂの電極材料２では重合反応は起こらない。回路基板１付近にはＵＶは侵入し難いため、この部分の電極材料２では重合反応は起こりにくい。   As a result, as shown in FIG. 1C, the photopolymerizable substance (photopolymerization initiator, monomer, polymer) reacts with the electrode material 2 in the electrode region 2a by the UV that has passed through the opening 3a. The polymerization reaction does not occur in the electrode material 2 in the non-electrode region 2b. Since UV hardly penetrates into the vicinity of the circuit board 1, the polymerization reaction hardly occurs in this portion of the electrode material 2.

次に、アルカリ性の水溶液などを用いて現像を行なうことにより、重合反応が全く、あるいは十分に起こらなかった電極材料２を溶解・除去する。このことにより、図１(ｄ)に示すように、非電極領域２ｂの電極材料２が除去され、電極領域２ａの電極材料２は、表面付近は浸食されずガラスマスク３の開口部３ａ形状に相応した形状で残留する一方で、回路基板１付近では開口部３ａ形状よりも大きく浸食され、結果として、電極領域２ａの電極材料２の断面は台形を呈する。   Next, development is performed using an alkaline aqueous solution or the like to dissolve and remove the electrode material 2 in which the polymerization reaction has not occurred at all or sufficiently. As a result, as shown in FIG. 1 (d), the electrode material 2 in the non-electrode region 2b is removed, and the electrode material 2 in the electrode region 2a is not eroded in the vicinity of the surface so that the shape of the opening 3a of the glass mask 3 is obtained. While remaining in a corresponding shape, it is eroded more in the vicinity of the circuit board 1 than the shape of the opening 3a, and as a result, the cross section of the electrode material 2 in the electrode region 2a has a trapezoidal shape.

その後に、電極材料２が焼結する温度で回路基板１を焼成することにより、図１(ｅ)に示すように、回路基板１上の電極材料２を回路電極４として焼き付ける。図からわかるように、焼き付けられた回路電極４は、焼成時の電極材料２の収縮によって周縁部が回路基板１から離れる方向に反り入る（エッジカールする）形となり、円弧状の断面を呈する。   Thereafter, the circuit board 1 is fired at a temperature at which the electrode material 2 is sintered, so that the electrode material 2 on the circuit board 1 is baked as a circuit electrode 4 as shown in FIG. As can be seen from the figure, the baked circuit electrode 4 is warped (edge curled) in a direction in which the peripheral edge is separated from the circuit board 1 due to contraction of the electrode material 2 during firing, and exhibits an arc-shaped cross section.

最後に、図１(ｆ)に示すように、突起電極５に導電性樹脂６を転写した半導体素子７を回路基板１上に、突起電極５と回路電極４とが対向するように高精度に位置合わせし、適当な荷重をかけて電極どうし互いに当接させ、この状態で導電性樹脂６を硬化させることにより、半導体素子７のフリップチップ実装を完了する。   Finally, as shown in FIG. 1 (f), the semiconductor element 7 having the conductive resin 6 transferred to the protruding electrode 5 is placed on the circuit substrate 1 with high accuracy so that the protruding electrode 5 and the circuit electrode 4 face each other. By aligning, applying an appropriate load, bringing the electrodes into contact with each other, and curing the conductive resin 6 in this state, the flip chip mounting of the semiconductor element 7 is completed.

このようにして製造されたフリップチップ実装体では、エッジカールした回路電極４が受け皿となって導電性樹脂６のはみ出しを防ぐので、電極ピッチを１００μｍピッチとした半導体素子７を実装する際も隣接する電極どうしがショートすることはない。   In the flip-chip mounting body manufactured in this way, the edge-curled circuit electrode 4 serves as a tray to prevent the conductive resin 6 from protruding, so that it is adjacent even when the semiconductor element 7 having an electrode pitch of 100 μm is mounted. There is no short circuit between electrodes.

なおここで、回路電極４についてさらに説明する。
図１(ｅ)に示したように、回路基板１表面からエッジカールした回路電極４までの最大距離をエッジカール量Ｌと定義すると、エッジカール量Ｌは、図１(ａ)に示した電極材料２の乾燥膜厚に大きく依存する。乾燥膜厚が１０〜２０μｍの場合にはエッジカール量Ｌは２〜１０μｍとなり、回路電極４は受け皿としての機能を果たす。 Here, the circuit electrode 4 will be further described.
As shown in FIG. 1E, when the maximum distance from the surface of the circuit board 1 to the edge-curled circuit electrode 4 is defined as an edge curl amount L, the edge curl amount L is the electrode shown in FIG. This greatly depends on the dry film thickness of material 2. When the dry film thickness is 10 to 20 μm, the edge curl amount L is 2 to 10 μm, and the circuit electrode 4 functions as a tray.

これに対し乾燥膜厚を２０μｍ以上とすると、未重合部分が多くなったり、あるいは現像後に消滅すべき非電極領域２ｂで電極材料２が十分除去されず残留し、ショートを引き起こす。逆に乾燥膜厚を１０μｍ以下とすると、エッジカール量Ｌが２μｍ以下となり、受け皿としての機能が充分に発揮されない。   On the other hand, when the dry film thickness is 20 μm or more, the number of unpolymerized portions increases, or the electrode material 2 is not sufficiently removed in the non-electrode region 2b that should disappear after development, causing a short circuit. On the contrary, when the dry film thickness is 10 μm or less, the edge curl amount L is 2 μm or less, and the function as a tray is not sufficiently exhibited.

図２は本発明のフリップチップ実装体を製造する第２の実装方法を説明する工程断面図である。
図２(ａ)に示すように、第１の実装方法と同様にして、回路基板１上にエッジカールした回路電極４を形成する。次に、回路電極４に相応する部分が開口されたマスクを位置合わせし印刷などの手法を用いて、図２(ｂ)に示すように回路電極４に導電性樹脂６を塗布する。その後に、図２(ｃ)に示すように、回路基板１に対して、突起電極５が形成された半導体素子７を位置合わせし、適当な荷重をかけることにより、半導体素子７のフリップチップ実装を完了する。 FIG. 2 is a process cross-sectional view illustrating a second mounting method for manufacturing the flip chip mounting body of the present invention.
As shown in FIG. 2A, edge curled circuit electrodes 4 are formed on the circuit board 1 in the same manner as in the first mounting method. Next, a conductive resin 6 is applied to the circuit electrode 4 as shown in FIG. 2B by aligning a mask having an opening corresponding to the circuit electrode 4 and using a method such as printing. Thereafter, as shown in FIG. 2 (c), the semiconductor element 7 on which the protruding electrodes 5 are formed is aligned with the circuit board 1, and an appropriate load is applied, whereby the flip chip mounting of the semiconductor element 7 is performed. To complete.

このようにして製造されたフリップチップ実装体でも、第１の実装方法におけるのと同様に、エッジカールした回路電極４が受け皿となって導電性樹脂６のはみ出しを防ぐので、ショートの発生がなくなる。
（実施例）
本発明構造のフリップチップ実装体を以下の回路基板とＩＣとを用いて製造し、性能を評価した。 Even in the flip-chip mounting body manufactured in this way, the edge-curled circuit electrode 4 serves as a tray to prevent the conductive resin 6 from protruding, as in the first mounting method, so that no short circuit occurs. .
(Example)
The flip chip mounting body of the present invention structure was manufactured using the following circuit board and IC, and the performance was evaluated.

回路基板：低温焼成セラミック多層基板（テストパターン）
基板サイズ：３０×３０×０．６５(ｍｍ)
電極ピッチ：１００（μｍ)
電極数：３６０ピン
ＩＣ：ダミーＩＣ
ＩＣサイズ１０×１０×０．５(ｍｍ)
ＩＣ電極パッドピッチ：１００（μｍ)
ピン数：３６０ピン
回路基板上の回路電極は、金属成分として銀を含んだ電極材料を成膜して乾燥膜厚１５μｍとし、約５０μｍ幅の開口部を形成したガラスマスクを用いて露光・現像した後、約８００〜１０００℃で焼成して形成した。得られた回路電極のエッジカールは４μｍであった。表面保護のためＮｉメッキ、Ａｕメッキを施した。ＩＣの突起電極は電極パッド上に金線を用いて形成した。 Circuit board: Low-temperature fired ceramic multilayer board (test pattern)
Substrate size: 30 x 30 x 0.65 (mm)
Electrode pitch: 100 (μm)
Number of electrodes: 360 pins IC: Dummy IC
IC size 10 x 10 x 0.5 (mm)
IC electrode pad pitch: 100 (μm)
Number of pins: 360 pins The circuit electrodes on the circuit board were exposed and developed using a glass mask having an electrode material containing silver as a metal component to a dry film thickness of 15 μm and an opening having a width of about 50 μm. And then baked at about 800 to 1000 ° C. to form. The edge curl of the obtained circuit electrode was 4 μm. Ni plating and Au plating were applied to protect the surface. The protruding electrode of the IC was formed on the electrode pad using a gold wire.

ＩＣの実装は、突起電極に金属成分としての銀と樹脂成分としてのエポキシとを含有する導電性樹脂を転写した後、回路基板と位置あわせし、１つの突起電極あたり数ｇの荷重をかけ、導電性樹脂を加熱硬化させることで行った。得られたフリップチップ実装体をショート・オープンについて評価した。結果を従来のフリップチップ実装体と対比して表１に示す。   For mounting the IC, a conductive resin containing silver as a metal component and epoxy as a resin component is transferred to the projecting electrode, then aligned with the circuit board, and a load of several grams per one projecting electrode is applied. This was done by heat-curing the conductive resin. The obtained flip chip mounting body was evaluated for short / open. The results are shown in Table 1 in comparison with the conventional flip chip mounting body.

Figure 0003926335
表１からわかるように、本発明のフリップチップ実装体ではオープン、ショートとも全く発生しなかったのに対し、従来のフリップチップ実装体では４／５にショートが発生し、本発明の有効性が確認された。
Figure 0003926335
 As can be seen from Table 1, in the flip chip mounting body of the present invention, neither open nor short circuit occurred, whereas in the conventional flip chip mounting body, 4/5 short circuit occurred, and the effectiveness of the present invention was confirmed. confirmed.

本発明の一実施形態におけるフリップチップ実装体を製造する第１の実装方法を説明する工程断面図Process sectional drawing explaining the 1st mounting method which manufactures the flip chip mounting body in one Embodiment of this invention 同フリップチップ実装体を製造する第２の実装方法を説明する工程断面図Process sectional drawing explaining the 2nd mounting method which manufactures the flip chip mounting body 従来のフリップチップ実装体を示した断面図Sectional view showing a conventional flip chip mounting body

符号の説明Explanation of symbols

１ 回路基板
２ 電極材料
2a 電極領域
2b 非電極領域
３ ガラスマスク
４ 回路電極
５ 突起電極
６ 導電性樹脂
７ 半導体素子
Ｌ エッジカール量 1 Circuit board 2 Electrode material
2a Electrode area
2b Non-electrode region 3 Glass mask 4 Circuit electrode 5 Projection electrode 6 Conductive resin 7 Semiconductor element L Edge curl amount

Claims (2)

突起電極が形成された半導体素子を導電性樹脂を用いて回路基板上に実装したフリップチップ実装体であって、前記半導体素子の突起電極が接続された回路基板上の回路電極は、金属材料とガラスを無機成分として含有し、かつ重合性物質と光重合開始剤を有機成分として含有した電極材料膜を焼成することにより周縁部が基板表面から離間する方向に反った凹状に形成され、電極どうし当接させるに先立っていずれかの電極に配置された前記導電性樹脂を当接後も凹面に保持したフリップチップ実装体。 A flip-chip mounting body in which a semiconductor element on which a protruding electrode is formed is mounted on a circuit board using a conductive resin, and the circuit electrode on the circuit board to which the protruding electrode of the semiconductor element is connected includes a metal material and By baking an electrode material film containing glass as an inorganic component and containing a polymerizable substance and a photopolymerization initiator as an organic component, a peripheral portion is formed in a concave shape that warps away from the substrate surface. A flip chip mounting body in which the conductive resin disposed on any of the electrodes is held on the concave surface after the contact before the contact. 突起電極が形成された半導体素子を導電性樹脂を用いてフリップチップ実装するための回路基板であって、前記半導体素子の突起電極が接続される回路電極は、電極領域に成膜した、金属材料とガラスを無機成分として含有し、かつ重合性物質と光重合開始剤を有機成分として含有した電極材料膜を焼成することにより周縁部が基板表面から離間する方向に反った凹状に形成され、電極どうし当接させるに先立っていずれかの電極に配置される前記導電性樹脂を当接後も凹面に保持するように構成された回路基板。 A circuit board for flip-chip mounting a semiconductor element on which a protruding electrode is formed using a conductive resin, the circuit electrode to which the protruding electrode of the semiconductor element is connected is a metal material formed in an electrode region And an electrode material film containing a polymerizable substance and a photopolymerization initiator as an organic component, and a peripheral portion formed into a concave shape warped in a direction away from the substrate surface. A circuit board configured to hold the conductive resin disposed on any one of the electrodes prior to contact with each other even after the contact.
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