JP3901328B2 - Signal transmission circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal transmission circuit that is provided in, for example, an exchange device or a signal transmission device in a communication system and performs high-speed transmission by converting signal levels between devices having different signal levels.
[0002]
[Prior art]
Conventionally, as a technique in such a field, for example, there are those described in the following documents.
Literature: Japanese Patent Laid-Open No. 8-228142 FIG. 2 is a circuit diagram showing a configuration example of a conventional signal transmission circuit described in the above literature.
[0003]
The signal transmission circuit is supplied with a power supply potential VCC of 3.3 V, for example, and is a drive unit configured by an emitter-coupled logic (hereinafter referred to as ECL) circuit that inputs an input signal IN and outputs an output signal S1. 1 The drive unit 1 has an input unit 1a composed of a transistor or the like that performs a switching operation according to the level of the input signal IN. The base of the NPN transistor 1b is connected to the output side of the input unit 1a, and the collector of the transistor 1b is connected to the power supply potential VCC. The emitter of the transistor 1b is connected to the node N1 in the level shift unit 2. Node N1 is connected to power supply potential VCC through resistor 2a, and is connected to node N2 through resistor 2b. The node N2 is connected to the ground via the resistor 2c, and is connected to the gate of a P-channel MOSFET (hereinafter referred to as PMOS) 3a in the amplifying unit 3. The source of the PMOS 3a is connected to the source of the PMOS 3b and to the power supply potential VCC. A reference potential Vr is input to the gate of the PMOS 3b. The drain of the PMOS 3a is connected to the drain of an N-channel MOSFET (hereinafter referred to as NMOS) 3c, and the drain of the PMOS 3b is connected to the drain and gate of the NMOS 3d and the gate of the NMOS 3c. The sources of the NMOSs 3c and 3d are connected to the ground. Further, the input side of the buffer 3e is connected to the drain of the PMOS 3a, and the output signal S3 is output from the output side of the buffer 3e.
[0004]
In this signal transmission circuit, an input signal IN is input to the drive unit 1, and an output signal S 1 corresponding to the input signal IN is output from the drive unit 1. The output signal S1 is input to the level shift unit 2, and level-shifted by the resistors 2a, 2b, 2c and output as the output signal S2. The output signal S2 is input to the amplifying unit 3, and the voltage difference from the reference potential Vr is amplified by the amplifying unit 3 and input to the buffer 3e. An output signal S3 is output from the buffer 3e.
[Problems to be solved by the invention]
However, in the conventional signal transmission circuit of FIG. 2, the level shift unit 2 performs level shift by dividing the output signal S1 by the resistors 2a, 2b, and 2c, so that the amplitude of the output signal S2 is greater than the amplitude of the output signal S1. Becomes smaller. Therefore, the drain level of the PMOS 3a becomes lower than the threshold value of the buffer 3e, and there is a problem that the output signal S3 may not be normally output due to fluctuations in the operating environment such as the power supply voltage and temperature.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problem, a first invention of the present invention is a signal transmission circuit, wherein an input signal having a first level and a second level complementary to the first level is input. A drive unit for outputting a first output signal in which a signal having a first amplitude corresponding to the input signal is superimposed on a predetermined DC level from an output stage having a high input impedance and a low output impedance; and the first output signal A level shift unit that shifts the direct current level and outputs a second output signal having a second amplitude, and an amplification unit that amplifies the second output signal and outputs a third output signal having a third amplitude And has.
[0007]
The level shift unit receives the first output signal and outputs a fourth output signal having a fourth amplitude larger than the first and second amplitudes, and the fourth output signal. And a drive circuit for outputting a positive-phase drive signal having a fifth amplitude larger than the first and second amplitudes and an inverted drive signal complementary to the positive-phase drive signal, and based on the second amplitude The first electrode to which the set first power supply potential is applied, the second electrode connected to the output terminal, and the positive phase drive signal are input, and the first and second electrodes are A first output transistor having a control electrode for controlling a conduction state; a first electrode connected to the output terminal; and a second power supply different from the first power supply potential set based on the second amplitude A second electrode to which a potential is applied, and the inversion drive signal are input; A second output transistor having a control electrode for controlling the conduction state between the first and the second electrode comprises.
[0008]
By adopting such a configuration, an input signal is input to the drive unit, and a first output signal is output from the drive unit. The first output signal is input to the receiver circuit, and a fourth output signal is output from the receiver circuit. The fourth output signal is input to the drive circuit, and a normal phase drive signal and an inverted drive signal are output from the drive circuit. The normal phase drive signal is input to the control electrode of the first output transistor, and the inverted drive signal is input to the control electrode of the second output transistor. Therefore, the conduction states of the first and second output transistors are complementarily controlled, and the second output signal having the second amplitude corresponding to the first and second power supply potentials is output from the output terminal. The second output signal is amplified by the amplifying unit and output as a third output signal.
[0009]
In the second invention, the drive unit of the first invention is constituted by an ECL circuit, and the first and second output transistors are constituted by MOSFETs.
By adopting such a configuration, an input signal is input to a drive unit configured by an ECL circuit, and a first output signal is output from the drive unit. The first output signal is input to the receiver circuit, and a fourth output signal is output from the receiver circuit. The fourth output signal is input to the drive circuit, and a normal phase drive signal and an inverted drive signal are output from the drive circuit. The positive phase drive signal is input to the gate of the first MOSFET, and the inverted drive signal is input to the gate of the second MOSFET. Therefore, the conduction states of the first and second MOSFETs are complementarily controlled, and a second output signal having a second amplitude corresponding to the first and second power supply potentials is output from the output terminal. The second output signal is amplified by the amplifying unit and output as a third output signal.
[0010]
In the third invention, the drive unit, the level shift unit, and the amplification unit of the first or second invention are formed inside the semiconductor integrated circuit.
By adopting such a configuration, the signal transmission circuit of the first or second invention is realized in the semiconductor integrated circuit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram of a signal transmission circuit showing an embodiment of the present invention.
This signal transmission circuit is formed inside a semiconductor integrated circuit and supplied with a power supply potential VCC of, for example, 3.3 V, and has a first level (for example, a high level, hereinafter referred to as “H”) and a second level ( For example, the driving unit 10 includes an ECL circuit 10a that inputs an input signal IN having a low level (hereinafter referred to as "L") and outputs a first output signal S10 from the output stage of the emitter follower. ing. The input side of the receiver circuit 21 in the level shift unit 20 is connected to the output side of the drive unit 10. The receiver circuit 21 is connected between the power supply potential VCC and the ground, receives the output signal S10, and outputs the fourth output signal S21. The input side of the drive circuit 22 a in the driver circuit 22 is connected to the output side of the receiver circuit 21. Driving circuit 22a is connected between the power supply potential VCC and the ground, based on the output signal S21, the complementary from the positive phase output terminal outputs a positive phase drive signal S22a _1, a positive phase drive signal S22a ₁ from the inverted output terminal a circuit for outputting a reversal driving signal S22a _2. The gate of the first output transistor (for example, NMOS) 22b is output to the positive phase output terminal of the drive circuit 22a, and the gate of the second output transistor (for example, NMOS) 22c is connected to the inverted output terminal. . The drain of the NMOS 22 b is connected to a power supply potential Vtt of 1.2 V, for example, and the source of the NMOS 22 b is connected to the output terminal 23. The drain of the NMOS 22c is connected to the output terminal 23, and the source of the NMOS 22c is connected to the ground. The output terminal 23 outputs a second output signal S20.
[0012]
The output terminal 23 is connected to the gate of the PMOS 31 in the amplification unit 30.
The source of the PMOS 31 is connected to the source of the PMOS 32 and to the power supply potential VCC. A reference potential Vr is input to the gate of the PMOS 32. The PMOS 31 and 32 constitute a differential amplifier. The drain of the NMOS 31 is connected to the drain of the PMOS 31, and the drain and gate of the NMOS 34 and the gate of the NMOS 33 are connected to the drain of the PMOS 32. The sources of the NMOSs 33 and 34 are connected to the ground. The NMOS 33 and 34 constitute a current mirror circuit for supplying the same current to the PMOSs 31 and 32. Further, the input side of the buffer 35 is connected to the drain of the PMOS 31, and the third output signal S30 is output from the output side of the buffer 35.
[0013]
FIG. 3 is a time chart of signals of respective parts for explaining the operation of FIG. 1, with the vertical axis representing voltage and the horizontal axis representing time.
The operation of FIG. 1 will be described with reference to this figure.
For example, an input signal IN in which “H” is 3.3 V and “L” is 0 V is input to the drive unit 10. The drive unit 10 outputs an output signal S10 having a first amplitude (for example, “H” is 2.5 V and “L” is 1.6 V). The output signal S10 is input to the receiver circuit 21, and the receiver circuit 21 outputs an output signal S21 having a fourth amplitude (for example, “H” is 3.3V and “L” is 0V). The output signal S21 is the fifth amplitude driving circuit 22a (e.g., "H""L" is at 3.3V is 0V) is converted to the positive-phase drive signals S22a ₁ and the inverted driving signal S22a ₂ of NMOS22b, 22c Is input to each gate. NMOS22b is turned on when the positive phase drive signal S22a ₁ is "H", turns off when "L". The NMOS 22c is turned on and off in a complementary manner to the NMOS 22b. When the NMOS 22c and 22b are in the ON state, assuming that the voltage drop due to the ON resistance is 0.3V, for example, output of the second amplitude (for example, “H” is 0.9V and “L” is 0.3V) from the output terminal 23. A signal S20 is output. The output signal S20 is input to the amplifying unit 30, and after the difference voltage from the reference potential Vr is amplified by the differential amplifier constituted by the PMOSs 31 and 32, the drain level of the PMOS 31 is input to the buffer 35. Since the drain level of the PMOS 31 is equal to or higher than the threshold value of the buffer 35, the buffer 35 normally outputs the output signal S30 having the third amplitude (eg, “H” is 3.3V and “L” is 0V). Is done.
[0014]
As described above, in the present embodiment, the drive unit the output signal S10 of 10 is converted to an output signal S21 at the receiver circuit 21, a positive phase drive signal S22a ₁ was generated based on the output signal S21 and the inverted driving signal S22a ₂ Since the NMOSs 22c and 22b are respectively driven, the output signal S20 having an amplitude at which the amplifying unit 30 operates normally and a level lower than “L” (that is, 1.6 V) of the output signal S10 is output. Is done. In addition, in the present embodiment, since the drive unit 10, the level shift unit 20, and the amplification unit 30 are formed inside the semiconductor integrated circuit, the output signal S20 can be transmitted at high speed and a low power consumption signal transmission circuit is integrated in the semiconductor integrated circuit. It can be realized inside the circuit.
[0015]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of such modifications include the following.
(A) The drive unit 10 may be configured with an output stage of, for example, a MOSFET source follower.
(B) The NMOSs 22b and 22c may be composed of PMOS. However, in this case, an output signal having an opposite phase to the output signal S20 in FIG. 3 is output.
(C) The amplifying unit 30 in FIG. 1 may be composed of a junction FET, a bipolar transistor, or the like.
[0016]
【The invention's effect】
As described above in detail, according to the first and second aspects of the invention, the first output signal output from the drive unit is converted into the fourth output signal by the receiver circuit, and the fourth output signal is converted into the fourth output signal. Since the first and second transistors are driven by the positive-phase drive signal and the inverted drive signal generated based on the first-phase drive signal and the inverted drive signal, the amplification unit has an amplitude at which the amplifier operates normally and the first output signal is “L”. The second output signal whose level is lower than the level of can be output. Therefore, a signal transmission circuit that converts the signal level and transmits at high speed can be realized.
According to the third aspect of the invention, since the level shift unit is formed inside the semiconductor integrated circuit, the second output signal can be transmitted at high speed and a low power consumption signal transmission circuit can be realized inside the semiconductor integrated circuit. .
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a signal transmission circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a conventional signal transmission circuit.
FIG. 3 is a time chart of FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Drive part 20 Level shift part 21 Receiver circuit 22a Drive circuit 22b, 22c NMOS (output transistor)
30 Amplifying part S22a ₁ Normal phase drive signal S22a ₂ Inverted drive signal

Claims (3)

An input signal having a first level and a second level complementary to the first level is input, and a signal having a first amplitude corresponding to the input signal from an output stage having a high input impedance and a low output impedance A drive unit that outputs a first output signal superimposed on a predetermined DC level;
A level shift unit that shifts a DC level of the first output signal to output a second output signal having a second amplitude;
An amplification unit for amplifying the second output signal and outputting a third output signal having a third amplitude;
The level shift unit includes:
A receiver circuit that receives the first output signal and outputs a fourth output signal having a fourth amplitude larger than the first and second amplitudes;
A drive circuit for outputting a positive-phase drive signal having a fifth amplitude larger than the first and second amplitudes and an inverted drive signal complementary to the positive-phase drive signal based on the fourth output signal;
A first electrode to which a first power supply potential set based on the second amplitude is applied, a second electrode connected to an output terminal, and the positive phase drive signal are input, and the first and A first output transistor having a control electrode for controlling a conduction state between the second electrodes;
A first electrode connected to the output terminal; a second electrode to which a second power supply potential different from the first power supply potential set based on the second amplitude is applied; and the inverted drive signal And a second output transistor having a control electrode that controls a conduction state between the first electrode and the second electrode. The drive unit is composed of an emitter-coupled logic circuit,
The signal transmission circuit according to claim 1, wherein the first and second output transistors are MOSFETs. The signal transmission circuit according to claim 1, wherein the drive unit, the level shift unit, and the amplification unit are formed inside a semiconductor integrated circuit.

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