JP3892798B2 - Display device and drive circuit thereof - Google Patents

Description

【００２４】
このように、表示モード切替信号ＣがＨｉレベルの場合、つまりフルカラー表示モードが選択された場合は、電流のプッシュプル動作が可能なオペアンプで階調電圧を出力することにし、Ｌｏｗレベルの場合、つまり８色表示モードが選択された場合は、ＭＯＳトランジスタ３０１、あるいは３０２のみで階調電圧を出力することにする。なお、８色表示モードが選択された場合、出力する階調電圧は極性信号Ａと表示階調データの最上位ビット信号Ｂで決定されるものとする。
【００２５】
図４（ｂ）は８色表示モード選択時のスイッチ制御についてまとめたものである。ここで、図３、４（ｂ）をもとに、オペアンプ回路のより詳細な動作について説明する。フルカラー表示モード選択時は、スイッチ３０５、３０６をオフ、スイッチ３０７、３０８、３０９をオン、スイッチ３１０、３１１をオフ、スイッチ３０３、３０４をオンすることでオペアンプを稼働状態にして、デコーダ部２０３で変換されたアナログの階調電圧をバッファ出力する。一方、８色表示モード選択時は、スイッチ３０５、３０６をオフしてオペアンプ回路への電流供給を遮断し、さらにスイッチ３０７、３０８、３０９をオンにすることで、オペアンプ回路内を貫通電流が流れない状態に安定させる。その上で、スイッチ３０３、３０４、３１０、３１１の動作を制御することで、出力する階調電圧レベルが決定されるものとする。例えば、高電位側の階調電圧を出力する場合は、スイッチ３０４をオフ、スイッチ３１１をオンすることで、ＭＯＳトランジスタ３０１のゲート端子を電源電圧ＶＤＤとショートさせる。また、低電位側の階調電圧を出力する場合は、スイッチ３０３をオフ、スイッチ３１０をオンすることで、ＭＯＳトランジスタ３０２のゲート端子を電源電圧ＶＤＤとショートさせる。なお、この例では、出力増幅回路を構成するＭＯＳトランジスタがＮＭＯＳトランジスタであることから、ゲート端子を電源電圧ＶＤＤとショートすることで電流を流す状態になり、液晶パネル内のドレイン線に階調電圧を印加することになる。
【００２６】
図５は、ＲＧＢそれぞれの表示階調データを６ビットとした場合の、８色表示モード選択時における、ドットクロック、ラインクロック、極性信号Ａ、表示階調データＢｍとその最上位ビット信号Ｂ、表示モード切替信号Ｃ、ドレイン線に印加される階調電圧波形のタイミングチャートをまとめたものである。
【００２７】
ドットクロックは１画素ずつシリアルに入力される表示階調データを順次取り込むために使用され、ラインクロックは１ライン分の表示階調データの同期出力や、極性信号Ａの生成にも使用される。極性信号Ａは、タイミング発生回路２１０内部のラインカウンタ出力をもとに生成され、また、表示階調データＢｍ、最上位ビット信号Ｂはラッチ回路２ ２０７の出力であることから、いずれもラインクロックの立ち下がりに同期して変動する。したがって、本実施例で出力部２０４のオペアンプ回路内に新規設けたスイッチ素子は、ラインクロックに同期して制御することになる。
【００２８】
以上、説明した構成と動作により、本発明第一の形態にかかわる液晶のドレイン線駆動回路２０１は出力部２０４のオペアンプ内の出力増幅回路を構成するＭＯＳトランジスタ３０１、３０２を使用して２レベルの階調電圧を出力し、低消費電力化が可能な８色表示モードを実現する。
【００２９】
したがって、本発明の目的である、大規模な新規回路を追加することなく、低消費電力化が可能な８色表示モードを実現することができる。
【００３０】
以下、本発明第二のドレイン線駆動回路の実施の形態を図２、６〜１０を用いて説明する。
【００３１】
図６は、ドレイン線とコモン電極に印加される階調電圧と画素電極に書き込まれる電位の関係を示したものである。
【００３２】
第一の実施例で述べたように、液晶に直流電圧が長時間印加されると、残像現象や劣化が発生するため、実際の駆動では、一定の周期で印加電圧の極性を反転する交流化が必要となる。また、液晶パネル内の画素電極に印加される電圧レベルは、液晶パネル内のゲート線選択波形の立ち下がり時に、ゲート線−コモン電極間の容量結合の影響で、図６に示すようにドレイン線に印加された階調電圧からΔＶｇｓ減衰する。また、このΔＶｇｓは印加する階調電圧レベルにより異なることもわかっている。したがって、図６の例では、実際に液晶に印加される実効値は正極時にＡ、負極時にＢとなり、正極と負極時での電圧実効値にＡ−Ｂの差が出てしまう。
【００３３】
直流電圧が印加されることに対する耐性が高い液晶パネルの場合は、第一の実施例が適用可能であるが、直流電圧に対する耐性が低い液晶パネルの場合は、第一の実施例を適用することで、液晶が劣化してしまう恐れがある。そこで、２レベルの階調電圧のうち、いずれかの階調電圧を調整可能とすることにした。
【００３４】
図７は、高電位側の階調電圧を調整可能にした場合のドレイン線、コモン電極に印加する階調電圧、そして、実際に液晶に印加される実効電圧を示したものである。このように２レベルの階調電圧のうち、いずれかの階調電圧を調整可能にすることで、白表示と黒表示、いずれの場合においても、正極電圧印加時と負極電圧印加時とでの電圧実効値差を低減することができ、液晶の劣化を抑制できる。
【００３５】
本発明第二の実施の形態に関わるドレイン線駆動回路のブロック図は第一の実施例で挙げた図２と同じである。
【００３６】
ドレイン線駆動回路２０１を構成する各ブロックを説明する。
【００３７】
ラッチ回路１ ２０６は、ラッチ回路２ ２０７、レベルシフタ２０８、デコーダ部２０３、タイミング発生回路２１０は第一の実施例と同様である。
【００３８】
階調電圧生成部２０２は、８色表示モード選択時においても、表示階調データに対応する複数の階調電圧を生成するものとする。
【００３９】
デコーダ部２０３へは、レベルシフタ２０８から表示階調データが入力される。そして、デコーダ部２０３は、８色表示モードが選択された場合でも、表示階調データに対応した階調電圧生成部２０２で生成された階調電圧を選択し、出力部２０４へ出力するものとする。
【００４０】
出力部２０４へは、レベルシフタ２０８を介して、表示モード切替信号、極性信号、表示階調データの最上位ビット信号が入力され、デコーダ部２０３から階調電圧が入力される。そして、８色表示モードが選択された場合、出力部２０４は、２レベルの階調電圧うち、一方の階調電圧はオペアンプ回路内の、電流源を有する回路が分離された出力増幅回路のみで出力し、もう一方の階調電圧はオペアンプでバッファ出力することで、電圧レベルの調整を可能とする。
【００４１】
なお、本実施例では、表示モード選択信号は２ビット信号とし、前述した２レベルの階調電圧のうち、一方の階調電圧をオペアンプで出力するモードと、第一の実施例で述べた、出力増幅回路のみで２レベルの階調電圧を出力するモードを選択できることにする。これにより、液晶パネルの直流電圧に対する耐性等、特性に応じた８色表示モードの実現が可能となる。
【００４２】
次に、出力部２０４のより詳細な動作について説明する。
【００４３】
図８は、本実施例を実現する出力部２０４内のオペアンプ回路の一例を示したものである。オペアンプ回路は図３に示したものと変わらないが、各スイッチを制御するための信号生成回路が異なる。
【００４４】
図９は、極性信号Ａと表示階調データＢmの最上位ビットＢと表示モード切替信号を２ビット信号ＣＤとした場合に、出力する階調電圧制御を行う場合の真理値表である。この真理値表に従い、表示モード切替信号ＣＤは、フルカラー表示モードと８色表示モードとの切り替え、さらに、８色表示モードの中でも、階調電圧を出力する回路として、オペアンプ回路とＭＯＳトランジスタのみの回路とを指定できるものとする。これによれば、例えば、表示モード切替信号ＣＤ＝１０の場合には、高電位側の階調電圧レベルをオペアンプ回路で出力、低電位側の階調電圧レベルを出力増幅回路のみで出力する設定となる。その上で、極性信号Ａと表示階調データの最上位ビットＢをもとに、任意の階調電圧を出力することになる。
【００４５】
ここで、ドットクロック、ラインクロック、極性信号Ａ、表示階調データＢmの最上位ビット信号Ｂ、表示モード切替信号ＣＤ、ドレイン線印加電圧波形のタイミングチャートを図１０にまとめる。詳細説明は割愛するが、本実施例も第一の実施例と同様、出力部２０７内のオペアンプ回路内のスイッチ素子は、ラインクロックの立ち下がりに同期して制御することになる。
【００４６】
以上、説明した構成と動作により、本発明第二の形態に関わる液晶のドレイン線駆動回路２０１は、低消費電力を実現する８色表示モードにおいて、表示輝度制御で使用する２レベルの階調電圧うち、いずれか一方をオペアンプで出力することで階調電圧レベルを調整可能とし、液晶パネルに直流電圧が印加されて残像現象や劣化が発生することを防ぐことができる。
【００４７】
したがって、本発明の目的である、液晶を劣化させることなく、低消費電力化が可能な８色表示モードを実現することができる。
【００４８】
以下、本発明第三のドレイン線駆動回路の実施の形態を図１１を用いて説明する。
【００４９】
本発明はオペアンプを使用しない８色表示モード時に、出力増幅回路を構成するＭＯＳトランジスタの特性がばらついたとしても一定の階調電圧を出力可能とするものである。
【００５０】
例えば、図３、８に示すように、出力増幅回路をＮＭＯＳトランジスタで構成するオペアンプ回路で８色表示を実現した場合、低電位側の階調電圧はソース接地構成のＭＯＳトランジスタで電源電圧ＶＳＳを出力するのに対し、高電位側の階調電圧はソースフォロア構成のＭＯＳトランジスタで電源電圧ＶＤＤ−Ｖｔｈ（ＭＯＳトランジスタのしきい値電圧）を出力することになる。
【００５１】
ソースフォロア構成のＭＯＳトランジスタが電源電圧からＶｔｈずれた電圧を出力するのは、例えば、ＮＭＯＳトランジスタだと、ゲートとソース間の電位差Ｖｇｓがその素子の持つしきい値電圧Ｖｔｈ以上になった時、はじめて電流を流し始めることに起因している。つまり、ソース端子はゲート端子の電源電圧ＶＤＤからしきい値電圧Ｖｔｈ下がった電圧以上にはならない。
【００５２】
また、一般的にＭＯＳトランジスタのしきい値電圧Ｖｔｈは素子間でばらつくことが知られている。ソースフォロア構成のＭＯＳトランジスタの出力可能な電圧は、前述したように、しきい値電圧Ｖｔｈで規定されることから、この値がばらつくと、階調電圧が変動してしまう恐れがある。
【００５３】
このように、高電位側の階調電圧が一定の電圧レベルを出力できなければ、たとえ、本発明第二の実施例に従い、８色表示モードにおいて、一方の階調電圧が調整可能であっても、もう一方の階調電圧が一定でないため、液晶パネルに直流電圧が印加されてしまう恐れがある。したがって、直流電圧が印加されることに対する耐性が低い液晶パネルだと、オペアンプ回路毎に出力電圧を調整する必要が出てくる。
【００５４】
図１１は本発明第三の実施の形態に関わるドレイン線駆動回路内の出力部を構成するオペアンプ回路を示したものである。
【００５５】
このオペアンプの回路は、出力増幅回路をＮＭＯＳトランジスタ１１０１、１１０２で構成するオペアンプと、出力増幅回路をＰＭＯＳトランジスタ１１０３、１１０４で構成するオペアンプを組み合わせた構成としている。この構成では、出力増幅回路のみで階調電圧を出力する８色表示モードでも、ソース接地型のＭＯＳトランジスタ１１０３で電源電圧ＶＤＤ、ＭＯＳトランジスタ１１０２で電源電圧ＶＳＳを出力することになるため、仮にＭＯＳトランジスタのしきい値電圧Ｖｔｈがばらついたとしても一定の階調電圧が出力可能となる。
【００５６】
したがって、本発明の目的である、ドレイン線駆動回路の構成素子の特性ばらつきによらず、設定した階調電圧レベルを出力することが可能であり、液晶を劣化させることなく、低消費電力化が可能な８色表示モードを実現することができる。
【００５７】
【発明の効果】
本発明によれば、既存のオペアンプ回路内の出力増幅回路で液晶駆動を可能とした。これにより、８色表示モード用の駆動回路を新規に設ける必要がなく、回路規模の増大を抑えることができる。さらに、２つの階調電圧のうち、一方の階調電圧をオペアンプで出力することで、調整可能とした。これにより、液晶に直流電圧が印加されることを防ぐことができる。
【図面の簡単な説明】
【図１】液晶表示装置の構造を説明する図である。
【図２】本発明第一の実施の形態に関わる、ドレイン線駆動回路の構成を示すブロック図である。
【図３】本発明第一の実施の形態に関わる、ドレイン線駆動回路出力部内のオペアンプの回路構成を示す図である。
【図４】本発明第一の実施の形態に関わる、オペアンプ回路内に設けたスイッチ素子の制御信号と出力する階調電圧との関係を示す真理値表である。
【図５】本発明第一の実施の形態に関わる、ドレイン線駆動回路の動作を示すタイミング図である。
【図６】本発明第二の実施の形態に関わる、液晶パネル内のドレイン線とコモン電極、画素電極に印加される電圧の関係を示した図である。
【図７】本発明第二の実施の形態に関わる、高電位側の階調電圧を調整可能にした場合のドレイン線、コモン電極に印加する階調電圧、そして、実際に液晶に印加される実効電圧を示した図である。
【図８】本発明第二の実施の形態に関わる、ドレイン線駆動回路出力部内のオペアンプの回路構成を示す図である。
【図９】本発明第二の実施の形態に関わる、オペアンプ回路内に設けたスイッチ素子の制御信号と出力する階調電圧との関係を示す真理値表である。
【図１０】本発明第二の実施の形態に関わる、ドレイン線駆動回路部の動作を示すタイミング図である。
【図１１】本発明第酸の実施の形態に関わる、ドレイン線駆動回路出力部内のオペアンプの回路構成を示す図である。
【符号の説明】
２０１…ドレイン線駆動回路、２０２…階調電圧生成部、２０３…デコーダ部、２０４…出力部、２０５…レジスタ、２０６…ラッチ回路１、２０７…ラッチ回路２、２０８…レベルシフタ、２０９…システムインタフェース、３０１…ＭＯＳトランジスタ、３０２…ＭＯＳトランジスタ、３０３…スイッチ、３０４…スイッチ、３０５…スイッチ、３０６…スイッチ、３０７…スイッチ、３０８…スイッチ、３０９…スイッチ、３１０…スイッチ、３１１…スイッチ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device for displaying a dot matrix type liquid crystal.
[0002]
[Prior art]
As a drain line driving circuit that applies a gradation voltage corresponding to display data to a drain line in a liquid crystal panel and controls display luminance, there is a method described in Japanese Patent Laid-Open No. 2001-345828. This method has a simple display mode (8-color display mode) that reduces the number of colors to be displayed when the user does not perform an operation. The 8-color mode reduces power consumption.
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-345828
[Problems to be solved by the invention]
In the above method, in order to realize the 8-color display mode, two levels of VDD and VSS which are power supply voltages of the operational amplifier provided for each output are output. In this method, a switching element for cutting the steady-state current of the operational amplifier and a MOS transistor are newly required for the 8-color display mode. Therefore, there is a problem that the circuit scale increases.
[0005]
An object of the present invention is to provide a display device and a driving circuit thereof in which an increase in circuit scale is suppressed.
[0006]
[Means for Solving the Problems]
The MOS transistor used in the output amplifier circuit in the operational amplifier circuit provided for each output is also used in the 8-color display mode. Note that the output amplifier circuit of the operational amplifier circuit originally employs a sufficiently large MOS transistor for driving the panel load capacitance, and it is sufficient to control the gate voltage of the MOS transistor without increasing the new circuit scale. A good convergence time.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the first drain line driving circuit of the present invention will be described below with reference to FIGS.
[0008]
FIG. 1 shows a liquid crystal display device of a TFT composed of a drain line driving circuit, a power supply circuit, and a gate line driving circuit for a liquid crystal panel. In this liquid crystal panel, a TFT is arranged for each pixel, and drain lines and gate lines connected to the TFT are wired in a matrix. The source terminal of the TFT is connected to the pixel electrode, and the display luminance is controlled by the difference in applied voltage with the common electrode on the opposite side across the liquid crystal. Note that this liquid crystal display device controls the gradation voltage applied to each electrode by display gradation data transferred from the CPU.
[0009]
FIG. 2 is a block diagram of the drain line driving circuit according to the first embodiment of the present invention. Reference numeral 201 denotes a drain line driving circuit, 202 denotes a gradation voltage generation unit, 203 denotes a decoder unit, 204 denotes an output unit, 206 denotes a latch circuit 1, 207 denotes a latch circuit 2, 208 denotes a level shifter, and 210 denotes a timing generation circuit.
[0010]
The input to the drain line driving circuit 201 is display gradation data, a display mode switching signal, a dot clock, and a line clock sent from the CPU.
[0011]
The display gradation data is digital data indicating the gradations of RGB. The display mode switching signal is a signal for selecting the full color display mode and the 8-color display mode for the purpose of low power consumption. The Hi-level is the full-color display mode, and the Low-level is the 8-color display mode. Further, it is assumed that the display mode switching signal can control current supply to a part of the circuits constituting the gradation voltage generation unit 202 and the output unit 204 or to all the circuits. The dot clock is used in the latch circuit 1 206, and the line clock is used in the latch circuit 2 207 and the timing generation circuit 210.
[0012]
Next, each block constituting the drain line driving circuit 201 will be described.
[0013]
The timing generation circuit 210 has a line counter, counts a line clock input from the outside, and generates a polarity signal based on the counter value. This polarity signal is an AC timing for AC driving that is performed to prevent the afterimage phenomenon and deterioration of the liquid crystal. It is known that these afterimage phenomena and deterioration occur when a direct current voltage is applied to the liquid crystal for a long time, and are suppressed by alternating the gradation voltage applied to each electrode. When the polarity signal is at the Hi level, a negative gradation voltage is applied, and when the polarity signal is at the Low level, a positive gradation voltage is applied. For the AC cycle, for example, the polarity of the voltage applied for each line is switched. The voltage level of the polarity signal is switched by the least significant bit signal of the counter output.
[0014]
The latch circuit 1206 operates at the falling timing of the dot clock, and converts the display gradation data sent serially from the CPU for each pixel into parallel data for one line.
[0015]
The latch circuit 2207 operates at the falling timing of the line clock, and transfers display gradation data for one line to the level shifter 208.
[0016]
The level shifter 208 receives the display mode switching signal from the CPU, the display gradation data transferred from the latch circuit 2207, and the polarity signal generated by the timing generation circuit 210 from the Vcc-GND level that is the power supply voltage of the logic circuit. The gradation voltage generation unit 202, the decoder unit 203, and the output unit 204 are converted to the VDD-VSS level which is the operation power supply. The reason for this level conversion is that each block needs to be controlled at a voltage level corresponding to the operating power supply.
[0017]
A display mode switching signal is input to the gradation voltage generation unit 202 via the level shifter 208. When the display mode switching signal is Hi level and the full color display mode is selected, the gradation voltage generation unit 202 generates a plurality of gradation voltages corresponding to digital display gradation data. Note that the gradation voltage generator 202 includes a block composed of resistors connected in series. By supplying a current to the series resistance and outputting a terminal corresponding to the number of gradations, the gradation voltage is Generated. On the other hand, when the display mode switching signal is Low level and the 8-color display mode is selected, the display luminance of the liquid crystal panel is controlled only by the two-level gradation voltage, and the two-level gradation voltage is The gradation voltage generator 202 is not used because it is defined by the power supply voltages VDD and VSS of the operational amplifier. Therefore, when the 8-color display mode is selected, that is, when the display mode switching signal is at the low level, the current flowing through the series resistor described above can be stopped, and the power consumption consumed by the gradation voltage generation unit 202 can be reduced. Shall.
[0018]
The decoder unit 203 serves as a DA converter that converts the digital display gradation data from the level shifter 208 into an analog gradation voltage generated by the gradation voltage generation unit 202. Therefore, the output unit 204 outputs a gradation voltage corresponding to each display gradation data.
[0019]
To the output unit 204, the display mode switching signal, the polarity signal, and the most significant bit signal of the display gradation data are input from the level shifter 208, and the gradation voltage corresponding to the display gradation data is input from the decoder unit 203. When the display mode switching signal is Hi level and the full color display mode is selected, the output unit 204 outputs the gradation voltage converted by the decoder unit 203 as a buffer. On the other hand, when the display mode switching signal is at the low level and the 8-color display mode is selected, one of the two levels of gradation voltages based on the most significant bit signal and the polarity signal of the display gradation data. Shall be selected and output.
[0020]
Next, a more detailed operation of the output unit 204 will be described. The output unit 204 is provided with an operational amplifier circuit for voltage follower use for each output.
[0021]
FIG. 3 shows an example of an operational amplifier circuit constituting the output unit 204. This operational amplifier includes an output amplifier circuit composed of MOS transistors 301 and 302, switches 303 and 304 for separating circuits having current sources, and switches 305 and 306 for cutting off a steady current to the operational amplifier circuit. In order to prevent a through current from flowing in the operational amplifier circuit, switches 307, 308 and 309 for short-circuiting the internal terminal with the power supply voltage VDD or VSS, and two MOS transistors 301 and 302 constituting the output amplifier circuit Of these, switches 309 and 310 for short-circuiting the respective gate terminals to the power supply voltage VDD are provided in order to pass a current through one and not through the other.
[0022]
4A is a truth table for controlling the gradation voltage level output by the polarity signal A, the most significant bit signal B of the display gradation data, and the display mode switching signal C, and the expression (1) realizes it. This shows an arithmetic expression to be performed.
[0023]
[Expression 1]

[0024]
As described above, when the display mode switching signal C is at the Hi level, that is, when the full color display mode is selected, the gradation voltage is output by an operational amplifier capable of a current push-pull operation. That is, when the 8-color display mode is selected, the gradation voltage is output only by the MOS transistor 301 or 302. When the 8-color display mode is selected, the gradation voltage to be output is determined by the polarity signal A and the most significant bit signal B of the display gradation data.
[0025]
FIG. 4B summarizes the switch control when the 8-color display mode is selected. Here, a more detailed operation of the operational amplifier circuit will be described with reference to FIGS. When the full-color display mode is selected, the operational amplifier is activated by turning off the switches 305 and 306, turning on the switches 307, 308, and 309, turning off the switches 310 and 311, and turning on the switches 303 and 304. The converted analog gradation voltage is output as a buffer. On the other hand, when the 8-color display mode is selected, the switches 305 and 306 are turned off to cut off the current supply to the operational amplifier circuit, and the switches 307, 308 and 309 are turned on so that a through current flows in the operational amplifier circuit. To stabilize. Then, the gradation voltage level to be output is determined by controlling the operations of the switches 303, 304, 310, and 311. For example, in the case of outputting a high-potential-side gradation voltage, the switch 304 is turned off and the switch 311 is turned on, so that the gate terminal of the MOS transistor 301 is short-circuited with the power supply voltage VDD. In addition, when outputting a grayscale voltage on the low potential side, the gate terminal of the MOS transistor 302 is short-circuited to the power supply voltage VDD by turning off the switch 303 and turning on the switch 310. In this example, since the MOS transistor that constitutes the output amplifier circuit is an NMOS transistor, the gate terminal is short-circuited to the power supply voltage VDD so that a current flows, and the grayscale voltage is applied to the drain line in the liquid crystal panel. Will be applied.
[0026]
FIG. 5 shows the dot clock, line clock, polarity signal A, display gradation data Bm, and the most significant bit signal B when the 8-color display mode is selected when the display gradation data for each of RGB is 6 bits. The timing chart of the display mode switching signal C and the gradation voltage waveform applied to the drain line is summarized.
[0027]
The dot clock is used to sequentially capture display gradation data that is serially input pixel by pixel, and the line clock is also used to synchronize display gradation data for one line and generate a polarity signal A. The polarity signal A is generated based on the line counter output in the timing generation circuit 210, and the display gradation data Bm and the most significant bit signal B are the outputs of the latch circuit 2207. It fluctuates in synchronization with the fall of. Therefore, the switch element newly provided in the operational amplifier circuit of the output unit 204 in this embodiment is controlled in synchronization with the line clock.
[0028]
With the configuration and operation described above, the liquid crystal drain line drive circuit 201 according to the first embodiment of the present invention uses the MOS transistors 301 and 302 constituting the output amplifier circuit in the operational amplifier of the output unit 204 to achieve two levels. An 8-color display mode capable of outputting gradation voltages and reducing power consumption is realized.
[0029]
Therefore, an 8-color display mode capable of reducing power consumption can be realized without adding a large-scale new circuit, which is an object of the present invention.
[0030]
The second embodiment of the drain line driving circuit of the present invention will be described below with reference to FIGS.
[0031]
FIG. 6 shows the relationship between the gradation voltage applied to the drain line and the common electrode and the potential written to the pixel electrode.
[0032]
As described in the first embodiment, when a DC voltage is applied to the liquid crystal for a long time, an afterimage phenomenon or deterioration occurs. Therefore, in actual driving, alternating current that reverses the polarity of the applied voltage at a constant cycle is used. Is required. Further, the voltage level applied to the pixel electrode in the liquid crystal panel is affected by capacitive coupling between the gate line and the common electrode at the fall of the gate line selection waveform in the liquid crystal panel, as shown in FIG. ΔVgs attenuates from the grayscale voltage applied to. It is also known that ΔVgs varies depending on the applied gradation voltage level. Therefore, in the example of FIG. 6, the effective value actually applied to the liquid crystal is A at the positive electrode and B at the negative electrode, and a difference of A−B appears between the effective voltage values at the positive electrode and the negative electrode.
[0033]
In the case of a liquid crystal panel having high resistance against application of a DC voltage, the first embodiment can be applied. However, in the case of a liquid crystal panel having low resistance to DC voltage, the first embodiment should be applied. Therefore, the liquid crystal may be deteriorated. Therefore, any one of the two levels of gradation voltages can be adjusted.
[0034]
FIG. 7 shows the drain line, the gradation voltage applied to the common electrode, and the effective voltage actually applied to the liquid crystal when the gradation voltage on the high potential side can be adjusted. As described above, by adjusting any one of the two levels of gradation voltages, white display and black display can be performed in both cases when the positive voltage is applied and the negative voltage is applied. The voltage effective value difference can be reduced, and deterioration of the liquid crystal can be suppressed.
[0035]
The block diagram of the drain line driving circuit according to the second embodiment of the present invention is the same as FIG. 2 mentioned in the first embodiment.
[0036]
Each block constituting the drain line driving circuit 201 will be described.
[0037]
The latch circuit 1 206 is the same as that of the first embodiment in the latch circuit 2 207, the level shifter 208, the decoder unit 203, and the timing generation circuit 210.
[0038]
It is assumed that the gradation voltage generation unit 202 generates a plurality of gradation voltages corresponding to display gradation data even when the eight-color display mode is selected.
[0039]
Display gradation data is input from the level shifter 208 to the decoder unit 203. The decoder unit 203 selects the grayscale voltage generated by the grayscale voltage generation unit 202 corresponding to the display grayscale data and outputs it to the output unit 204 even when the 8-color display mode is selected. To do.
[0040]
A display mode switching signal, a polarity signal, and the most significant bit signal of display gradation data are input to the output unit 204 via the level shifter 208, and a gradation voltage is input from the decoder unit 203. When the eight-color display mode is selected, the output unit 204 outputs only one of the two levels of gradation voltages, that is, the output amplifier circuit in the operational amplifier circuit in which the circuit having the current source is separated. The other gradation voltage is output and buffered with an operational amplifier, thereby enabling adjustment of the voltage level.
[0041]
In this embodiment, the display mode selection signal is a 2-bit signal, and the mode in which one of the two levels of gradation voltages described above is output by the operational amplifier and the first embodiment described above. A mode for outputting a two-level gradation voltage can be selected only by the output amplifier circuit. As a result, it is possible to realize an eight-color display mode according to characteristics such as resistance to a direct current voltage of the liquid crystal panel.
[0042]
Next, a more detailed operation of the output unit 204 will be described.
[0043]
FIG. 8 shows an example of an operational amplifier circuit in the output unit 204 that implements the present embodiment. The operational amplifier circuit is the same as that shown in FIG. 3, but the signal generation circuit for controlling each switch is different.
[0044]
FIG. 9 is a truth table in the case where the output gradation voltage control is performed when the polarity signal A, the most significant bit B of the display gradation data Bm, and the display mode switching signal are the 2-bit signal CD. In accordance with this truth table, the display mode switching signal CD switches between the full-color display mode and the 8-color display mode, and even in the 8-color display mode, only the operational amplifier circuit and the MOS transistor are used as a circuit for outputting the gradation voltage. A circuit can be specified. According to this, for example, in the case of the display mode switching signal CD = 10, the setting is made such that the gradation voltage level on the high potential side is output by the operational amplifier circuit and the gradation voltage level on the low potential side is output only by the output amplifier circuit. It becomes. Then, an arbitrary gradation voltage is output based on the polarity signal A and the most significant bit B of the display gradation data.
[0045]
Here, a timing chart of the dot clock, the line clock, the polarity signal A, the most significant bit signal B of the display gradation data Bm, the display mode switching signal CD, and the drain line applied voltage waveform is summarized in FIG. Although a detailed description is omitted, in this embodiment as well as the first embodiment, the switch elements in the operational amplifier circuit in the output unit 207 are controlled in synchronization with the fall of the line clock.
[0046]
With the configuration and operation described above, the liquid crystal drain line driving circuit 201 according to the second embodiment of the present invention has two levels of gradation voltages used for display luminance control in the eight-color display mode realizing low power consumption. Of these, the grayscale voltage level can be adjusted by outputting one of them with an operational amplifier, and it is possible to prevent an afterimage phenomenon or deterioration due to a DC voltage being applied to the liquid crystal panel.
[0047]
Therefore, an 8-color display mode capable of reducing power consumption without deteriorating the liquid crystal, which is an object of the present invention, can be realized.
[0048]
The third embodiment of the drain line driving circuit of the present invention will be described below with reference to FIG.
[0049]
In the present invention, a constant gradation voltage can be output even if the characteristics of the MOS transistors constituting the output amplifier circuit vary in the 8-color display mode without using an operational amplifier.
[0050]
For example, as shown in FIGS. 3 and 8, when an 8-amplifier display is realized by an operational amplifier circuit in which an output amplifier circuit is configured by an NMOS transistor, the gradation voltage on the low potential side is set to the source voltage VSS by a MOS transistor having a source ground configuration. On the other hand, the gradation voltage on the high potential side outputs the power supply voltage VDD-Vth (the threshold voltage of the MOS transistor) by the MOS transistor having the source follower configuration.
[0051]
For example, in the case of an NMOS transistor, the source follower configuration MOS transistor outputs a voltage shifted by Vth from the power supply voltage. When the potential difference Vgs between the gate and the source becomes equal to or higher than the threshold voltage Vth of the element, This is because the current starts to flow for the first time. That is, the source terminal does not exceed the voltage lower than the threshold voltage Vth from the power supply voltage VDD of the gate terminal.
[0052]
Further, it is generally known that the threshold voltage Vth of a MOS transistor varies between elements. As described above, the voltage that can be output from the MOS transistor having the source follower is defined by the threshold voltage Vth. Therefore, if this value varies, the gradation voltage may fluctuate.
[0053]
Thus, if the high potential side gradation voltage cannot output a constant voltage level, one gradation voltage can be adjusted in the 8-color display mode according to the second embodiment of the present invention. However, since the other gradation voltage is not constant, a DC voltage may be applied to the liquid crystal panel. Therefore, in the case of a liquid crystal panel having low resistance against application of a DC voltage, it is necessary to adjust the output voltage for each operational amplifier circuit.
[0054]
FIG. 11 shows an operational amplifier circuit constituting the output section in the drain line driving circuit according to the third embodiment of the present invention.
[0055]
This operational amplifier circuit is configured by combining an operational amplifier whose output amplifier circuit is composed of NMOS transistors 1101 and 1102 and an operational amplifier whose output amplifier circuit is composed of PMOS transistors 1103 and 1104. In this configuration, even in the 8-color display mode in which the gradation voltage is output only by the output amplifier circuit, the power supply voltage VDD is output by the source grounded MOS transistor 1103 and the power supply voltage VSS is output by the MOS transistor 1102. Even if the threshold voltage Vth of the transistor varies, a constant gradation voltage can be output.
[0056]
Therefore, it is possible to output the set gradation voltage level regardless of the characteristic variation of the constituent elements of the drain line driving circuit, which is the object of the present invention, and the power consumption can be reduced without deteriorating the liquid crystal. Possible 8 color display modes can be realized.
[0057]
【The invention's effect】
According to the present invention, it is possible to drive a liquid crystal with an output amplifier circuit in an existing operational amplifier circuit. Thereby, it is not necessary to newly provide a driving circuit for the 8-color display mode, and an increase in circuit scale can be suppressed. Further, one of the two gradation voltages can be adjusted by outputting it with an operational amplifier. Thereby, it is possible to prevent a DC voltage from being applied to the liquid crystal.
[Brief description of the drawings]
FIG. 1 illustrates a structure of a liquid crystal display device.
FIG. 2 is a block diagram showing a configuration of a drain line driving circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a circuit configuration of an operational amplifier in a drain line drive circuit output unit according to the first embodiment of the present invention;
FIG. 4 is a truth table showing a relationship between a control signal of a switch element provided in an operational amplifier circuit and an output gradation voltage according to the first embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of the drain line driving circuit according to the first embodiment of the present invention.
FIG. 6 is a diagram showing the relationship between the drain lines in the liquid crystal panel, the voltages applied to the common electrode, and the pixel electrode according to the second embodiment of the present invention.
FIG. 7 shows the gradation voltage applied to the drain line and the common electrode when the gradation voltage on the high potential side according to the second embodiment of the present invention is adjustable, and is actually applied to the liquid crystal. It is the figure which showed the effective voltage.
FIG. 8 is a diagram showing a circuit configuration of an operational amplifier in a drain line drive circuit output unit according to the second embodiment of the present invention.
FIG. 9 is a truth table showing a relationship between a control signal of a switch element provided in an operational amplifier circuit and an output gradation voltage according to the second embodiment of the present invention.
FIG. 10 is a timing chart showing an operation of the drain line drive circuit unit according to the second embodiment of the present invention.
FIG. 11 is a diagram showing a circuit configuration of an operational amplifier in a drain line drive circuit output unit according to the embodiment of the present invention acid.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 201 ... Drain line drive circuit, 202 ... Gradation voltage generation part, 203 ... Decoder part, 204 ... Output part, 205 ... Register, 206 ... Latch circuit 1, 207 ... Latch circuit 2, 208 ... Level shifter, 209 ... System interface, 301 ... MOS transistor, 302 ... MOS transistor, 303 ... switch, 304 ... switch, 305 ... switch, 306 ... switch, 307 ... switch, 308 ... switch, 309 ... switch, 310 ... switch, 311 ... switch.

Claims (6)

For each of a plurality of drain lines and gate lines, and a common electrode on the opposite side of the liquid crystal layer,
A display panel that realizes display by applying a predetermined voltage;
In a display device including a drain line driving circuit, a gate line driving circuit, and a power supply circuit,
The drain line driving circuit includes an operational amplifier circuit for each output terminal,
The operational amplifier circuit includes an output amplifier circuit having a configuration in which a differential circuit at the front stage and a MOS transistor having a size for driving a panel load capacitance of a source ground and source follower configuration at the rear stage are combined,
The output amplifier circuit of the operational amplifier circuit,
A first color mode for realizing a push-pull operation of a current according to a signal level output from the differential circuit;
Apart from this, in accordance with the display data inputted, comprising a second mode for outputting a two-level power supply and GN D,
Ri switchable der in response to a signal input of the two modes from the outside,
In the first color mode, the differential circuit in the operational amplifier circuit and the output amplifier circuit are operated,
In the second mode, the output amplifier circuit in the operational amplifier circuit is operated, the operation of the differential circuit is stopped, and a steady current is cut off.
A display device characterized by that. The display device according to claim 1 .
Of the two levels of the power supply and GND that the operational amplifier circuit outputs in the second mode,
Either level changes the voltage level at regular intervals.
A display device characterized by that. The display device according to claim 1 .
Of the two levels output by the operational amplifier circuit in the second mode,
Either the levels provided a mode in which the voltage level changes every predetermined period, the mode does not change with two levels,
The two modes can be switched according to a signal input from the outside.
Viewing device you wherein a. In a display driving circuit that applies a gradation voltage of a level corresponding to display gradation data to a drain line of a display panel,
Each output terminal has an operational amplifier circuit,
The operational amplifier circuit includes an output amplifier circuit having a configuration in which a differential circuit at the front stage and a MOS transistor having a size for driving a panel load capacitance of a source ground and source follower configuration at the rear stage are combined,
The output amplifier circuit of the operational amplifier circuit,
A first color mode for realizing a push-pull operation of a current according to a signal level output from the differential circuit;
Apart from this, in accordance with the display data inputted, comprising a second mode for outputting a two-level power supply and GN D,
Ri switchable der in response to a signal input of the two modes from the outside,
In the first color mode, the differential circuit in the operational amplifier circuit and the output amplifier circuit are operated,
In the second mode, the output amplifier circuit in the operational amplifier circuit is operated, the operation of the differential circuit is stopped, and a steady current is cut off.
A display drive circuit characterized by the above. The display driving circuit according to claim 4 , wherein
Of the two levels of the power supply and GND that the operational amplifier circuit outputs in the second mode,
Either level changes the voltage level at regular intervals.
A display drive circuit characterized by the above. The display driving circuit according to claim 4 , wherein
Of the two levels output by the operational amplifier circuit in the second mode,
Either the levels provided a mode in which the voltage level changes every predetermined period, the mode does not change with two levels,
The two modes can be switched according to a signal input from the outside.
A display drive circuit characterized by the above.

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