JP3891498B2 - Method for probing a semiconductor wafer - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for probing a semiconductor wafer.
[0002]
[Prior art]
When a large number of chips are formed on a semiconductor wafer in a semiconductor process step, the electrical characteristics of each chip are inspected as they are, and defective products are screened. A probe device is usually used for this inspection. In this probe apparatus, a probe needle of a probe card is brought into contact with an electrode pad of each chip of a semiconductor wafer, and a predetermined voltage is applied from the probe needle to perform an electrical test such as a continuity test of each chip. It is a device that tests whether a chip has basic electrical characteristics through a tester.
[0003]
In the case of a conventional probe device,FIG.As shown in (a) and (b), for example, the plurality of probe needles 31 have a cantilever structure in which the base ends are fixed with synthetic resin or the like at the periphery of the central opening of a probe card (not shown). . Therefore, for example, in the case where eight chips T are simultaneously inspected by the oblique probe needles 31 shown in FIG. 5A, the probe card is structured so that the cantilevered probe needles 31 face each other. As shown in FIG. 4C, the chip T in which the electrode pads of each chip T are juxtaposed so as to be arranged in two rows, and the chip T in which two vertically and four horizontally (2 × 4) are arranged horizontally is arranged in one index area. After that, all the chips T on the semiconductor wafer are divided according to the index area, and all the chips T are inspected while the probe card is indexed according to each divided index area.
[0004]
[Problems to be solved by the invention]
However, since the conventional probe device has the cantilever structure of the probe needle 31 as described above, for example, in order to simultaneously inspect eight chips T.FIG.As shown in (c), since all the chips T are sequentially inspected with 2 × 4 chips T in a horizontally long array as one index feed amount, all the chips T on the semiconductor wafer are inspected sequentially. For example, as shown in FIG. 2B, at the right end of the semiconductor wafer W, the number of inspection chips by one probing is small, and conversely, a large number of index areas where the area without the chip T becomes wider are generated. Along with this, there is a problem that the number of index feeds increases, the inspection efficiency deteriorates, and the throughput decreases. Further, in the case of the probe needle 31 having such a cantilever structure, since the probe needle 31 is elongated with an oblique needle, the probe needle 31 repeatedly applies a pressing force from the semiconductor wafer while the index feed of the probe card is repeated. For example, the probe needle 31A is deformed by receiving an excessive force by being caught on unevenness on the surface of the semiconductor wafer during index feeding, for example, and the probe needle 31A is deformed from the electrode pad P. Without changing the probe cardNotThere was a problem of further decreasing the throughput.
[0005]
Therefore, for example, as shown in FIG. 18C, by arranging four chips T in the vertical direction and two (4 × 2) in the horizontal direction in one index area, the shape of the index area is changed to that of the semiconductor wafer. If it is made as close to a square as possible in accordance with the shape, the number of index feeds can be reduced as shown in FIG. However, in this case, since the electrode pads P are arranged in four rows, the cantilevered probe needles 31 are not simultaneously brought into contact with both the outer two rows of electrode pads P and the inner two rows of electrode pads P. must not. For this purpose, the probe card is structured so that the probe needle can come into contact with the inner electrode pad P (the left electrode pad in FIGS. 18A and 18B) P as shown in FIG. The probe needles are attached to the upper and lower two stages, and the upper probe needle 31 must be longer than the lower probe needle 32. In this case, the upper probe needle 31 is more easily deformed than the lower probe needle 32, and the upper probe needle 32 is, for example, as shown in FIG. There is a problem that the probe card 32 must be replaced by deforming upward on the semiconductor wafer to lift the probe needle 32 from the electrode pad P, and the throughput is further reduced.
[0006]
  The present invention has been made to solve the above problems,A plurality of contacts and a plurality of chips can be brought into electrical contact simultaneously and reliably,An object of the present invention is to provide a semiconductor wafer probing method capable of reducing the number of times of index feeding and improving the inspection efficiency.
[0007]
[Means for Solving the Problems]
  According to claim 1 of the present inventionMethod for probing a semiconductor waferIsMulti having a plurality of contacts corresponding to a plurality of chips that are continuous evenly and vertically and horizontally and that are continuous 4 or more in at least one of the longitudinal and lateral directionsWhen inspecting the electrical characteristics of chips arranged on a semiconductor wafer using a probe card,On the computer, the multi-probe card is allocated to the entire surface of the semiconductor wafer, and an automatic setting mode for automatically setting a rectangular contact area with which the multi-probe card contacts is selected, and the multi-probe is selected using the automatic setting mode. Multiple contacts on the cardFor electrode pads of multiple chipsSameSometimes touchingOf the semiconductor waferA method for probing a semiconductor wafer in which the above contacts are brought into contact with all chips by sequentially performing index feedingBecause,The automatic setting mode includes a step of setting an area to be simultaneously inspected by the multi-probe card as one index zone, a step of assigning X and Y coordinate values to each of the plurality of chips in the semiconductor wafer, and the semiconductor wafer. After obtaining the number of chips in the longest chip row in the X-axis direction based on the maximum value and the minimum value of the X coordinate, the above-described number of chips and the number of chips in the X-axis direction of the index area are described above. The number of allocations in the X-axis direction of the index area covering all the chips in the longest chip row is obtained, and the contactor contacts the number of chips corresponding to the portion of the allocated index area protruding from the longest chip row. The number of blank chips to be obtained, and the number of blank chips obtained by dividing the number of blank chips into two equal parts. The X-coordinate value of the blank probe at one end is arranged in contact with the multi-probe card in the X-axis direction. The step of obtaining the start position, the step of obtaining the contact start position in the Y-axis direction of the multi-probe card in the same procedure as the contact start position in the X-axis direction for the chip row in the Y-axis direction, and the X and Y axes Setting the contact area by allocating the index area to the entire surface of the semiconductor wafer on the basis of the X and Y coordinate values indicating the contact start position in each direction, and setting the automatic setting mode.The semiconductor wafer is index-fed in the contact area along the shortest path from the first index area to the last index area.
[0008]
  In addition, the present inventionClaim 2The method for probing a semiconductor wafer according to claim 1,1In the described invention, a probe needle held vertically at the center of the wiring board is used as the contact.
[0009]
[Action]
  According to the first aspect of the present invention, when inspecting the electrical characteristics of the chips arranged on the semiconductor wafer, an even number of probe cards are continued in the vertical and horizontal directions and at least one of the vertical and horizontal directions. When an automatic setting mode is selected on a computer when a semiconductor wafer is inspected by using a multi-probe card having a plurality of contacts that make contact with a plurality of chips that are continuous in four or more directions, the multi-probe By automatically setting a rectangular contact area including the entire surface of the semiconductor wafer with which the card contacts, the semiconductor wafer is then indexed according to the shortest path by contacting the contact from the first index area in the contact area. All the chips above can be inspected.
  In addition, the present inventionClaim 2According to the invention described in claim1In the described invention, by using a plurality of probe needles held vertically at the center of the wiring board as the contact, the plurality of contacts can be brought into contact with the semiconductor wafer more reliably.
[0011]
【Example】
Hereinafter, the present invention will be described based on the embodiments shown in FIGS.
If the semiconductor wafer probing method of the present invention is used, all chips on the semiconductor wafer can be inspected in the order shown in FIGS. And when implementing the probing method of this invention, the probe card shown in FIG. 3, FIG. 4 can be used suitably.
[0012]
First, before explaining the semiconductor wafer probing method of the present embodiment, a probe card suitably used in the present embodiment will be described with reference to FIGS. As shown in the figure, the probe card 1 includes a printed circuit board 2 having an opening in the center, and a large number of probe needles 3 that pass through the central opening 2A of the printed circuit board 2 and are connected to the printed wiring on the surface. And is attached to a fixed head of a probe device (not shown). A cup-shaped intermediate block 4 having a flange portion 4 </ b> A is fixed to the back surface side of the printed circuit board 2 by screws 5.
[0013]
An upper block 6 that closes the central opening 2A of the printed circuit board 2 and the upper opening of the intermediate block 4 is fixed to the upper surface of the flange portion 4A of the intermediate block 4 by screws 7, and a cooling chamber 8 to be described later is placed in the intermediate block 4. Is forming. Further, a thick portion 4B having a diameter smaller than the outer diameter is formed on the lower surface of the intermediate block 4, and holding blocks 9 for holding a plurality of probe needles 3 vertically are fitted to the thick portion 4B. The holding block 9 is fixed to the lower surface of the intermediate block 4 by screws 10. Further, openings 6A, 4C and 9A are formed at the bottom of the upper block 6, the intermediate block 4 and the center of the holding block 9, and a large number of probe needles 3 pass through these openings 6A, 4C and 9A. Yes.
[0014]
The probe needle 3 is held vertically by guide plates 11, 12, and 13 attached to the openings 6A, 4C, and 9A, respectively. That is, pores corresponding to the number of probe needles 3 are formed in these guide plates 11, 12, 13, and a large number of probe needles 3 are guided from the upper surface of the probe card 1 to the center of the lower surface by these pores. At the same time, they are held vertically. Further, these probe needles 3 are fixed to the opening 6A of the upper block 6 with a synthetic resin 14 such as an epoxy resin, and the lower ends of the probe needles 3 are each electrode pads (for example, 8 × 2) of the chips T to be inspected (for example, 8 × 2). (Not shown) so that they are in contact with each other at the same time. Of course, the probe card 1 has a number of probe needles 3 corresponding to the electrode pads of 8 × 2 chips T as shown in FIG. Therefore, in the following description, the probe card 1 is referred to as a multi-probe card 1.
[0015]
In addition, an inlet pipe 16 that guides a cooling gas such as compressed air or compressed nitrogen from the gas supply device 15 into the cooling chamber 8 is connected to the side surface of the intermediate block 4, and cooling is provided near the opening of the upper block 6. A lead-out pipe 17 is connected to guide the cooling gas introduced into the chamber 8 to the outside. As a result, the gas for cooling is introduced from the gas supply device 15 into the cooling chamber 8 of the multi-probe card 1 through the introduction pipe 16, and the gas after cooling the probe needle 3 in the cooling chamber 8 is sent through the outlet pipe 17. To exhaust outside. Further, the thermocouple 18 passes through the opening 6A of the upper block 4 and reaches the cooling chamber 8, and the thermocouple 18 is configured to monitor the temperature in the cooling chamber 8, that is, the temperature of the probe needle 3. Yes. The thermocouple 18 is connected to the cooling chamber monitoring control device 20 via the wiring 19, and an electric signal 21 is sent from the cooling chamber monitoring control device 20 to the gas supply device 15 based on the temperature in the cooling chamber 8 detected by the thermocouple 18. To control the supply of the cooling gas.
[0016]
Next, a preferred embodiment of the semiconductor wafer probing method of the present invention for inspecting the electrical characteristics of the chip T on the semiconductor wafer W using the multi-probe card 1 will be described with reference to FIGS.
[0017]
That is, as described above, the multi-probe card used in this embodiment is an even number, that is, 8 in the vertical direction and 2 in the horizontal direction, and in at least one of the vertical and horizontal directions (vertical direction in this embodiment). It has a plurality of vertical probe needles 3 corresponding to each electrode pad of 8 × 2 chips T which are continuous. When the chip T of the semiconductor wafer W is inspected using the multi-probe card 1, the multi-probe card 1 is set with the orientation flat O in the vertical direction as shown in FIG. Then, 8 × 2 chip areas to be inspected by the multi-probe card 1 are set as one index area 22, and then the index areas 22 are spread vertically and horizontally with respect to the semiconductor wafer W so that all the areas on the semiconductor wafer W are covered. A region having a minimum area formed when the chip T is covered is set as a contact region 23 on the semiconductor wafer W. In this case, the contact region 23 is formed by covering 15 index areas 22. After that, the shortest path from the first index section (1) to the last index section (15) in the contact area 23 is used, and the index area 22 at the upper left end in the contact area 23 is moved from the upper right end to the upper right end, and further from just below the left end. Number each position in the direction meandering to the side from (1) to (15) in order. These numbers are set as the index feed order. The order of the index area 22, the contact area 23, and the index feed is registered in a control device (not shown).
[0018]
After that, the mounting table (not shown) of the semiconductor wafer W is moved according to the index order registered via the control device, and the electrode pads of the 16 chips T in each index area 22 on the semiconductor wafer W are moved to each electrode pad. The probe needle 3 of the multi-probe card 1 is brought into contact and 16 chips T are inspected simultaneously for each index feed, and the inspection for all the chips T on the semiconductor wafer W is completed by repeating this inspection 15 times. it can.
[0019]
However, in the case of the probing method using the conventional multi-probe card, due to the structure of the probe card, as shown in FIG. 1 (b), chips T arranged in two vertically long and eight horizontally long chips are arranged. You must use a multi-probe card that tests at the same time. Therefore, the number of index feeds of the multi-probe card is 20 as shown in FIG. In addition, in the conventional probing method, the number of idle probe needles in the index area 22 on the right half of the semiconductor wafer W is far greater than that in the chip to be inspected, and the inspection efficiency is extremely low. I understand that.
[0020]
As described above, according to the present embodiment, the number of index feeds is reduced by 5 times compared to the conventional probing method using a multi-probe card, and the number of feeds can be reduced by 25%. The inspection cost can be greatly reduced. In addition, by using the vertical probe needles 3 as in this embodiment, the probe needles 3 can be in contact with a plurality of tips T simultaneously in an arbitrary arrangement and inspected. 3 can be remarkably suppressed, the position of the probe needle 3 from the electrode pad can be prevented from being displaced, and a highly accurate inspection can be performed. The inspection cost can be further reduced by reducing the number of times the card 1 is replaced.
[0021]
FIG. 2A is a diagram showing a case where 4 × 2 chips T are simultaneously inspected using the semiconductor wafer probing method of the present invention. In this case, all the chips T on the semiconductor wafer W can be inspected by 28 index feeds. In contrast to this, in the conventional method, the index feed must be performed 31 times as shown in FIG. Therefore, according to the present embodiment, the number of index feeds can be reduced by 10% compared to the conventional case. In addition, the same effects as those of the above embodiment can be expected.
[0022]
In the above description, the multi-probe card 1 which inspects 16 or 8 chips T at the same time is assumed. However, the multi-number and the minimum contact area of the multi-probe card 1 are not known from the beginning. When setting the number of multiples and the minimum contact area, a computer can be used to significantly save the time required to set the number of multiples and the minimum contact area. When using a computer, first, as shown in the flowchart of FIG. 5, wafer information such as wafer size and orientation flat (orientation flat) direction and chip information such as vertical and horizontal (x, y) size of the chip. (S1), and then card information regarding the multi-probe card such as the number of chips (multi-number) that can be inspected simultaneously and the chip arrangement thereof is input (S2). Thereafter, the contact area of the multi-probe card with respect to the semiconductor wafer is simulated by a computer a plurality of times based on these input data (S3). Based on the result, the number of blank chips to be blanked out of the semiconductor wafer and its blank shots are calculated. The coordinates of the chip are obtained (S4), and the result is registered in the computer and stored (S5). Then, the quality of the index feed count and the number of blank chips is determined based on the respective results (S6), the probing method considered to be the best is determined and displayed on the display unit (S7). After determining the probing method by the computer in this way, the semiconductor wafer W is actually probed using the probe apparatus.
[0023]
When setting the contact area of the multi-probe card by computer simulation, there are three simulation methods of “automatic setting mode”, “optimum setting mode”, and “arbitrary setting mode”, as described later. Can be appropriately selected by an operator based on wafer information, chip information, card information, and the like. When the contact region is placed in the semiconductor wafer as in this embodiment, a simulation is performed using an “arbitrary setting mode” as will be described later. As a result of simulation in the “arbitrary setting mode”, when the multi-probe card 1 having 16 or 8 multis is used as in this embodiment, the above-described method can be most efficiently inspected. In the following description with reference to FIGS. 6 to 16, a simulation for setting the contact area of the multi-probe card 1 shown in FIG. 1A will be described.
[0024]
As shown in FIG. 6, the computer 50 used in this embodiment is based on input means 51 for inputting data such as wafer information, chip information, card information, and the like, and on the basis of the wafer information and card information from the input means 51. A card allocating device 52 for allocating index areas of a multi-probe card on a semiconductor wafer, and a display means 53 for displaying the image and numerical data of the semiconductor wafer and the chip for allocating the index areas by the allocating device 52 are provided. ing. The allocation device 52 includes a coordinate calculation unit 54, a chip coordinate storage unit 55, a file storage unit 56, a card allocation mode storage unit 57, a menu storage unit 58, a card allocation unit 59, and a card allocation position storage unit 60. Yes. The input unit 51 includes, for example, a keyboard 51A and a mouse 51B. The display unit 53 includes a display unit 53A such as an LCD or CRT that displays graphic information and the like, and a display control unit 53B that controls the display information of the display unit 53A. As shown in FIG. 4, the display unit 53A displays the semiconductor wafer and the chips in graphic form, and displays the wafer information and the card information in characters.
[0025]
The coordinate calculation means 54 automatically arranges rectangular image-like chips on an image-like semiconductor wafer based on the wafer information and chip information input from the input means 51, and position coordinates for each chip. Is given. The chip coordinate storage unit 55 includes a RAM or the like, and stores each chip obtained by the coordinate calculation means 54 and each coordinate in association with each other. The information stored in the chip coordinate storage unit 54 is graphically displayed as a wafer map on the display unit 53A via the display control unit 53B as described above. This wafer map is displayed as shown in FIG. The file storage unit 56 is composed of a storage device such as a ROM connected to the coordinate calculation means 54, in which various pieces of information relating to a plurality of types such as wafer information, chip information and card information are registered in advance. Therefore, the coordinate calculation means 54 reads the information stored in the file storage section 54, performs the above-described calculation processing in the same manner as the information from the input means 51 based on this information, and displays a wafer map based on the information on the display section 53A. It is designed to display graphics.
[0026]
The card allocation mode storage unit 57 includes a storage device such as a ROM. For example, three types of modes, an automatic allocation mode, an optimal allocation mode, and an arbitrary allocation mode, are stored in advance, and an operator can select an appropriate mode. It is like that. Here, the automatic allocation mode is a mode in which the contact area is automatically allocated so that the multi-probe card contacts in the vertical and horizontal directions of the semiconductor wafer evenly, for example, vertically and horizontally. The optimum allocation mode is a mode in which contact areas are automatically allocated so that the number of times the multi-probe card contacts on the wafer is minimized. The arbitrary allocation mode is a mode in which the contact position of the multi-probe card can be arbitrarily set by moving the contact position with the cursor movement key of the keyboard 31A or the mouse 31B.
[0027]
The menu storage unit 58 stores various operation menus necessary for operating the computer 50, menu initialization necessary for setting measurement conditions, and card allocation used for card allocation. It is. Menu contents can be increased or decreased as necessary. Then, as shown in FIG. 16, when “initialize map” displayed on the display unit 53A is selected with the mouse 52B, all chips in the semiconductor wafer become test targets, and when “card allocation” is selected, card allocation is performed. The mode is supposed to work.
[0028]
The card allocating unit 59 sets the contact area between the chip of the semiconductor wafer and the multi-probe card based on the storage information in the chip coordinate storage unit 55, the storage information in the card allocation mode storage unit 57, and the command from the input unit 51. I have to do it. The card allocating means 59 has an automatic allocation unit 61 shown in FIG. 7, an optimum allocation unit 62 shown in FIG. 8, and an arbitrary allocation unit 63 shown in FIG.
[0029]
As shown in FIG. 7, the automatic allocation unit 61 includes an X-axis minimum unit 64A for obtaining a minimum value in the X-axis direction on the wafer map displayed on the display unit 53A, and an X-axis maximum for obtaining a maximum value in the X-axis direction. It has a value part 64B, a Y-axis minimum part 65A for obtaining a minimum value in the Y-axis direction, and a Y-axis maximum value part 65B for obtaining a maximum value in the Y-axis direction. The X-direction minimum value portion 64A and the X-axis maximum value portion 64B are each connected with an X-direction protrusion amount (number of X-direction empty chips) calculation portions 66A. Of these pieces of information and card information, X of the multi-probe card The number of blank chips at the end when a multi-probe card is arranged in an integer multiple at the row position of the maximum width in the X direction from the number of chips Nx in the direction (chips assuming that the chip is protruding from the wafer and there is a chip in that portion Number) Xh is obtained. The state at this time is shown in FIG. 14B and FIG. 15A. In FIG. 15A, the upper row shows the maximum width chip row in the X direction, and the lower row shows the hypothetical card allocation position. Show. A left end start position determination unit 67A is connected to the X direction blank chip number calculation unit 66A, and the left end start position determination unit 67A determines the left and right (X direction) of the graphic wafer based on the output value of the X direction blank chip number calculation unit 66A. The card allocation position is determined by obtaining the left end start position xs so that the cards protrude as evenly as possible and the number of left and right empty chips is as even as possible. FIG. 15B shows this state.
[0030]
Similarly, the Y-axis minimum value portion 65A and the Y-axis maximum value portion 65B are respectively connected to the Y-direction blank chip number calculation unit 66B, and the number of blank chips Yh at the end in the Y-direction is the same as described above. Is to ask. An upper end start position determination unit 67B is connected to the Y direction blank chip number calculation unit 66B, and the upper end start position determination unit 67B moves the graphic wafer up and down (Y direction) based on the output value of the Y direction blank chip number calculation unit 66B. ) To determine the card allocation position by obtaining the upper end start position ys so that the card protrudes as evenly as possible. The left end start position determination unit 67A and the lower end start position determination unit 67B are connected to an automatic allocation calculation unit 68. The automatic allocation calculation unit 68 is graphically based on output values from the start position determination units 67A and 67B. Multi-probe cards are automatically allocated on the basis of the left and lower ends of the wafer, and the result is stored in the card allocation storage unit 60. FIG. 14C shows the arrangement of the cards allocated in this way.
[0031]
Further, as shown in FIG. 8, the optimum allocation unit 62 has the increment unit 69 connected to the X-axis minimum and maximum value units 64A and 64B and the Y-axis minimum and maximum value units 65A and 65B, respectively. The automatic allocation unit 61 is configured in the same manner. The optimal allocation unit 62 determines the card allocation position by determining the left end and top end start position of each row when a plurality of cards are arranged in the Y direction in each row of chips on the graphic wafer. At this time, the increment unit 69 indicates a row to be allocated in order to perform automatic allocation for each row or every plurality of rows. Thus, the multi-probe card can be contacted to all chips with the minimum number of contacts, that is, the minimum contact area. FIG. 14D shows the arrangement of the cards allocated in this way.
[0032]
Further, as shown in FIG. 9, the arbitrary allocation unit 63 has a card reference position determination unit 70. In the case of a multi-probe card that simultaneously inspects the card reference position, for example, eight chips, the leftmost channel Is used as a reference position, and the coordinates on the graphic wafer are determined by inputting with the mouse 52B as shown in FIG. 14 (e). Thereby, the card allocation position can be arranged at an arbitrary position on the semiconductor wafer. In other words, the automatic allocation unit 61 and the optimal allocation unit 62 allocate cards regardless of whether or not the card protrudes from the graphic wafer. In the arbitrary allocation unit 63, the operator looks at the display unit 53A while viewing the graphic wafer. The contact area can be arbitrarily set so that the card can be stored in the card.
[0033]
The card allocation position and the chip set by the card allocation means 59 as described above are associated with each other and stored in the card allocation position storage unit 60 shown in FIG. Further, the card allocation position storage unit 60 is configured to store the number of empty chips and their respective coordinates. Accordingly, based on the stored contents, the card allocation position is superimposed on the graphic wafer and the chip on the display unit 53A and displayed, for example, as shown in (c) and (d) of FIG. Each coordinate can be seen on the display unit 53A.
[0034]
  Next, using the computer 50As shown in (a) to (e) of FIG.Multi-probe card allocation when testing four chips simultaneouslySwingSimulate contact areaDoThe case will be described with reference to FIGS.The multi-probe card used in the present invention is for inspecting a plurality of rows and columns of chips. In FIGS. 14A to 14E, there are four in the X direction, that is, one row and four columns. These chips are shown in a simplified manner to be inspected simultaneously. This is because the display becomes complicated when the relationship between the multi-probe card of multiple rows and columns and the chip of the semiconductor wafer is illustrated. 15A and 15B more specifically show the relationship between the multi-probe card of 2 rows and 8 columns and the chip on the semiconductor wafer. Therefore, in the following, the present embodiment will be described with reference to FIGS. 15A and 15B showing the relationship between the multi-probe card of 2 rows and 8 columns and the chip of the semiconductor wafer as necessary.First, wafer information, chip information, and card information are input using the input means 51 as in S1 and S2 described above. Then, based on this input information, the coordinate calculation means 54 of the allocating device 52 allocates the chips on the image on the wafer on the image, stores the result, and sets the wafer and chips suitable for the image to the graphic wafer GW and The graphic chip GT is displayed on the display unit 53A as shown in FIG. Thereafter, the operator operates the mouse 52B to execute the above-described simulation as shown in FIGS.
[0035]
At that time, in the area above the graphic wafer GW of the display unit 53A, a menu for mode selection necessary for card allocation such as “automatic setting mode”, “optimum setting mode”, and “arbitrary setting mode” is displayed (S11). ). When a desired mode is selected on the display unit 53A from the three card allocation modes using the mouse 52B, the computer 50 always determines whether or not the mouse 52B is pressed (S12). It is determined whether or not the mouse pointer 71 (see FIG. 16) points to one of three types of modes (S13). This is performed until any mode is instructed.
[0036]
  For example, when the automatic setting mode is selected in S14, the simulation is executed as follows. That is, the card allocating means 59 calculates the card contact area (layout) so that the cards are allocated substantially evenly in the horizontal direction of the graphic wafer GW (S15). As a calculation procedure, first, the minimum value Xmin and the maximum value Xmax in the X-axis direction are obtained from all the chip coordinates of the wafer map based on the data stored in the chip coordinate storage unit 55 (see FIG. 14B). Of the card information in the X direction from the card informationN x TheHow many of the cards will protrude at the edge of the wafer when the cards are allocated at the row position where the maximum width in the X direction is used.TotalCalculate.At this time, the above calculation is performed based on the following formula using the relationship between the multi-probe card and the chip of the semiconductor wafer shown in FIG.FIG. 15 shows the calculation result.(B)become.In FIG. 15A, since the number of chips in the X direction of the multi-probe card is eight, N x = 8.still,In the following formulaThe reason why 1 is added to the difference between Xmax and Xmin is to add a chip of coordinates (0, 0). After executing this calculation, the process proceeds to S16. However, in the following formula, Q represents the quotient of division and R represents the remainder.
  {(Xmax-Xmin) +1} / Nx = Q... R
  Number of empty chips Xh = Nx-R
  This is calculated by substituting specific numerical values as follows.
  {(12-(-12) +1} / 8 = 3... 1
  Number of empty chips Xh = 8-1 = 7
[0037]
In S16, the left end start position xs at the time of card layout in the X-axis direction is calculated based on the following equation. The following equation is for setting the amount of protrusion from both ends of the wafer, that is, the number of blank chips, to be approximately equal when the card is laid out in the X direction. However, in the following formula, [Xh / 2] represents a rounded integer.
xs = Xmin- [Xh / 2]
If a specific numerical value is substituted for the calculation, for example, the result is as shown in FIG.
xs = -12- [7/2] =-15
That is, the coordinates (-15, 0) are the starting position of the card layout, and the length of three chips protrudes from the left end of the wafer, and the length of four chips protrudes from the right end. Although the layout is started from the left side here, it may be started from the right side.
[0038]
  Similarly, in S17, the contents executed in S15 and S16 are executed in the Y direction, and the upper end start position ys of the Y axis is obtained. When the start coordinates (xs, ys) on the wafer map are obtained in this way, the upper left part of the probe card (here, the upper left channel is because there are two rows in the Y direction) at the coordinates (xs, ys). Then, cards are allocated in the X direction (row direction) and Y direction (column direction) with reference to the start coordinates on the wafer map, the cards are spread on the wafer map, and the result is displayed as a contact area on the display unit 53A. (S18). This stateSimplify by assigning index area of multi-probe card that inspects 4 chips simultaneously in X directionWhat is shown is (c) in FIG. The result obtained here is stored in the card allocation position storage unit 60 (S19), and finally stored in the file storage unit 56 (S20).
[0039]
Next, the optimum setting mode will be described. In this mode, the card allocation position is automatically laid out so that the number of contacts of the probe card 1, that is, the number of index feeds, is minimized. For this purpose, first, the process returns to S14. When the answer is NO in this step and the "optimum setting mode" is selected in S21 shown in FIG. 12, the stored contents of the increment unit 69 indicating the row position of the chip to be allocated on the wafer map. Is set to “0” (S22), and the stored content i is then increased by “1” (S23).
[0040]
Next, an optimal card layout is performed in the i-th row (here, the first row) on the wafer map to set a contact area. In this case, in the coordinate calculation at the time of card layout, the steps of S15 shown in FIG. 10 and S16 and S17 shown in FIG. 11 are performed only for the first row to obtain the left end start position (S24). Thereafter, the card layout of the first row is determined based on the left end start position and displayed on the display unit 53A (S25). Further, it is determined whether or not the i-th line is the last line of the wafer map (S26). If it is not the last line, the process returns to S23, the content i of the increment unit 69 is incremented by 1, and the same calculation is performed. repeat. When the calculation is performed up to the last line of the chip and the card is laid out, the process proceeds to S19 in FIG. 11 and the contact area of each laid out card is stored. At this time, the display unit 53A displays (d) of FIG. 14 and determines the card allocation with the smallest card index feed count.
[0041]
Finally, a case where “optional setting mode” is selected will be described. In this arbitrary setting mode, the operator can assign a card to an arbitrary position and set a contact area. First, returning to FIG. 12, if “optional setting” is selected in S27 shown in FIG. 13 in this step, it is determined whether or not the mouse button is always pressed (S28, S29), and the mouse button is released. In this case, one layout is displayed by positioning the upper left end of the card layout at the chip coordinates (xn, yn) where the mouse pointer 71 is positioned at that time (S30). Then, the chip coordinates of the mouse pointer 71 are stored (S32). Next, it is determined whether or not the card layout has filled the entire wafer map (S33). If not, it is determined whether or not the end menu has been selected (S34). If the end menu has not been selected, the process returns to S28 again, and the above operation is repeated after waiting for an instruction. The layout during the card layout is displayed on the display unit 53A as shown in FIG. When the card layout fills the entire wafer map in this way, or when the end menu is selected, the process returns to S19 in FIG. 11, and the card layout position at that time is stored and filed.
[0042]
  Contact region in the probing method of this embodiment23In order to obtain the value, any of the three types of modes may be used. If the number and arrangement of multi-probe cards 1 are determined, the minimum contact area can be achieved in a short time using the optimum setting mode.23Can be requested. But its minimum contact area23Are not necessarily the minimum number of blank chips. Therefore, contact area23And contact area with the smallest number of blank chips23Is set using three modes, and the operator makes a decision based on the respective results. This determination can also be made by the computer 50. In that case, it is sufficient to incorporate determination software and input various conditions to be optimum conditions.
[0043]
In addition, by using the above-described computer 50, it is possible to design the number and layout of the multi-probe card. For this purpose, various semiconductor wafers to be inspected are registered in advance in the file storage unit, various card information is input for each semiconductor wafer, and the most efficient multi-probe card is obtained based on the obtained results. If selected, an optimum multi-probe card can be obtained.
[0044]
In each of the above embodiments, the present invention has been described with respect to the case where 8 × 2 chips T and 4 × 2 chips T are inspected simultaneously. Using a multi-probe card having a plurality of contacts corresponding to a plurality of chips that are continuous four or more in at least one direction, a plurality of chip areas to be inspected by the multi-probe card is set as one index area, Next, after setting the index area on the semiconductor wafer as a contact area, the area that is the minimum area formed when all the chips on the semiconductor wafer are covered vertically and horizontally is covered, and then the predetermined index area is set in the contact area. Index multi-probe cards along the shortest path from to the last index zone Any such method is encompassed by the present invention. Further, the present invention includes a case where a computer is used to project a wafer or chip on a display unit such as a CRT or LCD and a contact region is designed on the wafer. Moreover, although the said Example demonstrated what used the vertical probe card as the contactor of a multi-probe card | curd, when implementing this invention, a membrane card can also be used.
[0045]
【The invention's effect】
  As described above, according to the first aspect of the present invention, the probe card corresponds to a plurality of chips that are evenly arranged in the vertical and horizontal directions and that four or more chips are continuous in at least one of the vertical and horizontal directions. When inspecting electrical characteristics of chips arranged on a semiconductor wafer using a multi-probe card having a plurality of contacts, the multi-probe card is allocated to the entire surface of the semiconductor wafer on a computer. Select an automatic setting mode that automatically sets the contact area of the rectangular shape to contact, while using the automatic setting mode, while simultaneously contacting a plurality of contacts of the multi-probe card to the electrode pads of a plurality of chips The semiconductor wafer in which the contacts are brought into contact with all the chips by sequentially feeding the index of the semiconductor wafer. In the automatic probing method, the automatic setting mode includes a step of setting an area to be simultaneously inspected by the multi-probe card as one index area, and X and Y coordinate values for each of the plurality of chips on the semiconductor wafer. And determining the number of chips in the longest chip row in the X-axis direction based on the maximum and minimum values of the X coordinate among all the chips of the semiconductor wafer, and then the number of chips and the X-axis of the index area Based on the number of chips in the direction, the number of allocations in the X-axis direction of the index area covering all the chips in the longest chip row is obtained, and the chip corresponding to the portion where the allocated index area protrudes from the longest chip row Calculating the number as the number of blank chips that the contact does not contact, and dividing the number of blank chips into two equal parts. The number of blank chips obtained in this way are arranged separately to the outside of the chip having the maximum value and the chip having the minimum value in the X coordinate, and the X coordinate value of the blank chip at one end is set. The step of obtaining the contact start position in the X-axis direction of the multi-probe card and the start of contact in the Y-axis direction of the multi-probe card in the same procedure as the contact start position in the X-axis direction for the chip row in the Y-axis direction Determining the position; and setting the contact region by allocating the index area over the entire surface of the semiconductor wafer with reference to the X and Y coordinate values indicating the contact start positions in the X and Y axis directions, respectively. Prepared from the first index area to the last index area in the contact area set by the automatic setting mode. In order to index the semiconductor wafer along the shortest path, the contact area of the multi-probe card is set in a rectangular shape by using an automatic setting mode on a computer, and even numbers are continuously and vertically and horizontally in the index area. Provided is a method for probing a semiconductor wafer in which a contact is surely brought into contact with all chips in an index area even when four or more continuous chips are arranged in any one direction, thereby improving inspection efficiency. it can.
  In addition, the present inventionClaim 2According to the invention described in claim1In the described invention, since the probe needle held vertically at the center of the wiring board is used as the contactor, a plurality of probe needles can be simultaneously contacted vertically with a plurality of chips in the index area, It is possible to provide a method for probing a semiconductor wafer capable of reliably connecting a plurality of probe needles and a plurality of chips.
[0047]
  In addition, the present inventionClaim 2According to the invention described inClaim 1In the described invention, since the area as close to a square as possible is set as the index area by the plurality of chips, it is possible to provide a method for probing a semiconductor wafer that can further reduce the number of index feeds.
  In addition, the present inventionClaim 3According to the invention described in claim 1,Or claim 2In the invention according to claim 1, the contactor that makes vertical contactAs a probe needle held vertically in the center of the wiring boardFor,Multiple probe needles can be simultaneously and vertically contacted with multiple tips in the index area, ensuring reliable electrical connection between multiple probe needles and multiple tipsA method for probing a semiconductor wafer can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a method for simultaneously inspecting 16 chips on a semiconductor wafer one by one. FIG. 1A shows an inspection sequence of chips on a semiconductor wafer according to an embodiment of a probing method for a semiconductor wafer of the present invention. FIG. 2B is a plan view showing an inspection sequence of chips on a semiconductor wafer by a conventional semiconductor wafer probing method.
FIG. 2 is a view showing a method for simultaneously inspecting eight chips on a semiconductor wafer at a time, and FIG. 2A shows an inspection sequence of the chips on the semiconductor wafer according to one embodiment of the semiconductor wafer probing method of the present invention; FIG. 2B is a plan view showing an inspection sequence of chips on a semiconductor wafer by a conventional semiconductor wafer probing method.
FIG. 3 is a perspective view showing a probe card of a probe apparatus suitably used in the semiconductor wafer probing method of the present invention.
4 is a cross-sectional view showing the probe card shown in FIG. 3. FIG.
FIG. 5 is a flowchart showing an embodiment of the semiconductor wafer probing method of the present invention.
FIG. 6 is a block diagram showing a main part of a computer used when carrying out the semiconductor wafer probing method of the present invention.
7 is a block diagram showing an automatic allocation unit of the computer shown in FIG. 6;
FIG. 8 is a block diagram showing an optimal allocation unit of the computer shown in FIG. 6;
9 is a block diagram showing an arbitrary allocation unit of the computer shown in FIG. 6;
FIG. 10 is a flowchart showing a flow when allocating a multi-probe card.
FIG. 11 is a flowchart showing a flow when allocating a multi-probe card.
FIG. 12 is a flowchart showing a flow when allocating a multi-probe card.
FIG. 13 is a flowchart showing a flow when allocating a multi-probe card.
14 (a), (b), (c), (d), and (e) are diagrams showing a graphic display of a display unit when a multi-probe card is allocated. FIG.
FIGS. 15A and 15B are schematic views showing a part of a calculation process when allocating a multi-probe card.
FIG. 16 is a diagram showing an initial screen of the display unit.
FIG. 17 is a view showing a part of probe needles of a conventional probe card and an arrangement of chips to be inspected by the probe card, in which FIG. 17 (a) is a perspective view showing a part of probe needles in a normal state; FIG. 2B is a view corresponding to FIG. 1A showing the probe needle in a deformed state, and FIG. 2C is a plan view showing the arrangement of chips to be inspected by the probe needle of FIG.
FIG. 18 is a diagram showing a part of probe needles of another conventional probe card and an arrangement of chips to be inspected by the probe card, in which FIG. 18 (a) is a perspective view showing a part of the probe needles in a normal state. FIG. 2B is a diagram corresponding to FIG. 1A showing the probe needle in a deformed state, and FIG. 2C is a plan view showing the arrangement of chips to be inspected by the probe needle of FIG. .
[Explanation of symbols]
  1 Probe card
  3 Vertical probe needle (contact)
22 Index area
23 Contact area
50 computers
51 Input means
53A Display
  W Semiconductor wafer
  T chip
GW graphic wafer
GT graphic chip

Claims (2)

Electricity of chips arranged on a semiconductor wafer using a multi-probe card having a plurality of contacts corresponding to a plurality of chips that are evenly connected in the vertical and horizontal directions and that are four or more continuous in at least one of the vertical and horizontal directions When inspecting the physical characteristics, an automatic setting mode is selected in which the multi-probe card is allocated on the entire surface of the semiconductor wafer on a computer and a rectangular contact area in contact with the multi-probe card is automatically set. Using the setting mode, the semiconductor wafer is sequentially index-fed while simultaneously bringing the plurality of contacts of the multi-probe card into contact with the electrode pads of the plurality of chips, and the contacts of the semiconductor wafer are brought into contact with all the chips. A probing method,
The automatic setting mode is
Setting an area to be simultaneously inspected by the multi-probe card as one index area;
Providing X and Y coordinate values to each of the plurality of chips in the semiconductor wafer;
After obtaining the number of chips in the longest chip row in the X-axis direction based on the maximum and minimum values of the X coordinate among all the chips of the semiconductor wafer, the number of chips and the number of chips in the X-axis direction of the index area are The number of allocations in the X-axis direction of the index area covering all the chips of the longest chip row is determined based on the number of chips corresponding to the portion of the allocated index area protruding from the longest chip row. A step of obtaining the number of empty chips that the child does not contact;
The number of blank chips obtained by equally dividing the number of blank chips is divided and arranged outside the chip having the maximum value and the chip having the minimum value on the X coordinate, respectively, Obtaining the X-coordinate value of the empty chip in the X-axis contact start position of the multi-probe card;
For the chip row in the Y-axis direction, obtaining the contact start position in the Y-axis direction of the multi-probe card in the same procedure as the contact start position in the X-axis direction;
Setting the contact region by allocating the index area over the entire surface of the semiconductor wafer with reference to the X and Y coordinate values indicating the contact start positions in the X and Y axis directions, respectively,
A method for probing a semiconductor wafer, wherein the semiconductor wafer is index-fed along the shortest path from the first index area to the last index area in the contact area set by the automatic setting mode. 2. The method of probing a semiconductor wafer according to claim 1, wherein a plurality of probe needles held vertically at the center of the wiring board are used as the contact.

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