JPH07235572A - Probing method of semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce the number of times of index sending, and improve inspection efficiency. CONSTITUTION:A probe card having a plurality of vertical probe pins 3 corresponding with 8X2 chips T wherein 8 chips are continuously arranged in the longitudinal direction and 2 chips are continuously arranged in the transversal direction is used. A plurality of chip regions which are inspected with the probe card are set as an index zone 22. After a region turning to the minimum area formed when all of the chips T on a semiconductor wafer W are covered by tightly laying the index zones 22 in the longitudinal and the transversal directions is set as a contact region 23 on the semiconductor wafer, the semiconductor wafer W is subjected to index sending, from the index zone 22 on the left side upper end to the index zone 22 on the left side lower end.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer probing method.

[0002]

2. Description of the Related Art When a large number of chips are formed on a semiconductor wafer in a semiconductor process step, the electrical characteristics of individual chips are inspected as they are.
I try to screen for defective products. And
A probe device is usually used for this inspection. In this probe device, an electrode pad of each chip of a semiconductor wafer is brought into contact with a probe needle of a probe card, and a predetermined voltage is applied from the probe needle to perform an electrical test such as a continuity test of each chip to perform individual test. It is a device that tests whether a chip has basic electrical characteristics through a tester.

In the case of a conventional probe device, FIG.
As shown in (a) and (b), for example, a plurality of probe needles 31 have a cantilever structure in which the base ends are fixed by a synthetic resin or the like at the periphery of the central opening of a probe card (not shown). . Therefore, for example, when eight chips T are inspected at the same time by the oblique probe needle 31 shown in FIG. 3A, a probe card in which the probe needles 31 having a cantilever structure face each other is used because of the structure of the probe card. As shown in FIG. 3C, the electrode pads of each chip T are juxtaposed in two rows, and two chips vertically and four horizontally (2 × 4) are arranged in a horizontally long chip T to form one index area. After that, all chips T on the semiconductor wafer are divided according to this index area, and all chips T are inspected while index-feeding the probe card according to each divided index area.

[0004]

However, in the conventional probe apparatus, since the probe needle 31 has a cantilever structure as described above, for example, in order to inspect eight chips T at the same time, as shown in FIG. 2 x 4 in a horizontally long array as shown in
Since all chips T are sequentially inspected with one chip T as one index feed amount, when sequentially inspecting all the chips T on the semiconductor wafer, for example, FIG.
As shown in (b), at the right end of the semiconductor wafer W, the number of inspection chips by one-time probing is small, and conversely, a large number of index areas are generated in the region without the chips T, and accordingly, the index regions are generated. There was a problem that the number of feedings increased, the inspection efficiency deteriorated, and the throughput decreased. In addition, such a cantilever type probe needle 3
In the case of 1, since the probe needle 31 is slanted and long, the probe needle 31 is repeatedly pressed by the semiconductor wafer while the index feeding of the probe card is repeated, or in some cases, during index feeding. The probe needle 3 is caught by the unevenness of the semiconductor wafer surface.
1 receives an unreasonable force, for example, probe needle 31A
Is deformed and the probe needle 31A is displaced from the electrode pad P, the probe card must be replaced, and there is a problem that throughput is further reduced.

Therefore, for example, as shown in FIG. 18C, four chips T are vertically arranged in one index area,
By arranging two (4 × 2) pieces in the lateral direction so that the shape of the index area can be made as close to a square as possible in accordance with the shape of the semiconductor wafer, the number of index feeds can be increased as shown in FIG. Can be reduced. However, in this case, since the electrode pads P are arranged in four rows, it is not possible to simultaneously contact the probe needles 31 having a cantilever structure with both the outer two rows of the electrode pads P and the inner two rows of the electrode pads P. must not. To this end, the structure of the probe card is fixed so that the probe needle can contact the inner electrode pad (the left electrode pad in FIGS. 18A and 18B) P as shown in FIG. 18A. It is necessary to attach the probe needles to the upper and lower two stages and to make the upper probe needle 31 longer than the lower probe needle 32. In this case, the upper probe needle 31 is lower in the lower probe needle 32.
It is more easily deformed and, for example, while the pressing force is repeatedly applied to the probe needle 32 by the semiconductor wafer, for example, the upper probe needle 3
2 is deformed upward on the semiconductor wafer as shown in FIG. 2B and the probe needle 32 is lifted up from the electrode pad P, so that the probe card must be replaced and the throughput is further reduced. was there.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a probing method for a semiconductor wafer which can reduce the number of index feeds and improve the inspection efficiency.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor wafer probing method, wherein a plurality of chips are arranged on a semiconductor wafer when inspected for electrical characteristics using a probe card. In a probing method of a semiconductor wafer in which index needles are sequentially contacted with the electrode pads of the chips at the same time to bring the contacts into contact with all the chips, an even number of the probe cards are continuously connected vertically and horizontally and at least vertically and horizontally. Using a multi-probe card having a plurality of contacts corresponding to a plurality of chips that are continuous in one or more directions in any one direction, an area to be inspected at the same time by this multi-probe card is set as one index area. Spread all the chips on the semiconductor wafer by laying out the index areas vertically and horizontally. In this contact region, the semiconductor wafer is index-fed according to the shortest path from the first index area to the last index area after setting the area having the smallest area formed as a contact area on the semiconductor wafer. It is something that is done.

According to a second aspect of the present invention, there is provided a semiconductor wafer probing method, wherein electrode pads of a plurality of chips are used when inspecting electrical characteristics of chips arranged on the semiconductor wafer using a probe card. In the probing method of the semiconductor wafer in which the index needles are sequentially contacted with respect to all the chips to contact the contacts with respect to all the chips in the probing method of the semiconductor wafer, an even number of the probe cards are continuously connected in the vertical and horizontal directions and at least one of the vertical and horizontal directions. When a multi-probe card having a plurality of contacts corresponding to a plurality of chips continuous in four directions is used, the semiconductor wafer and the chips are graphically displayed on a display unit of a computer, and then the multi-probe card is displayed. Area to be inspected at the same time as one index area The contact area is set as the contact area, which is the minimum area formed when the index area is set in the display unit of the computer, and the index area is laid vertically and horizontally on the wafer on which graphic display is performed to cover all the chips displayed graphic. After setting in the display section, the semiconductor wafer is index-fed in the contact region according to the shortest path from the first index area to the last index area.

[0009]

According to the first aspect of the present invention, when inspecting the electrical characteristics of the chips arranged on the semiconductor wafer, an even number of probe cards are continuous vertically and horizontally and at least either vertically or horizontally. Using a probe card having a plurality of contacts corresponding to a plurality of four or more continuous chips in one direction, an area to be simultaneously inspected by this probe card is set as one index area, and then this index area is set. Set a region on the semiconductor wafer that is the minimum area that covers all the chips on the semiconductor wafer vertically and horizontally, and then sets the contact region on the semiconductor wafer as the contact region. By index feeding, all chips on the semiconductor wafer can be inspected with the minimum number of index feedings. It is possible.

Further, according to the second aspect of the present invention, the probe card corresponds to a plurality of chips which are continuous in the number of even number in the vertical and horizontal directions and which are continuous in four or more in at least one of the vertical and horizontal directions. When inspecting the electrical characteristics of the chips arranged on the semiconductor wafer using the multi-probe card having a plurality of contacts, after the semiconductor wafer and the chips are graphically displayed on the display unit of the computer, the multi-probe card is used simultaneously. The area to be inspected is set as one index area in the display unit of the computer, and then this index area is laid out vertically and horizontally on the wafer on which graphics are displayed to cover all the chips displayed on the graphics. The area that becomes the area is set as the contact area in the display unit, By indexing feed according shortest path by contacting the contacts of the contact area from the predetermined index area, it is possible to inspect all the chips on a semiconductor wafer with minimal index feed count.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in FIGS. By using the semiconductor wafer probing method of the present invention, all chips on the semiconductor wafer can be inspected in the order shown in FIGS. Then, when the probing method of the present invention is carried out, the probe card shown in FIGS. 3 and 4 can be preferably used.

Therefore, first, before explaining the semiconductor wafer probing method of this embodiment, a probe card preferably used in this embodiment will be described with reference to FIGS. As shown in FIG. 1, the probe card 1 includes a printed board 2 having an opening at the center and a large number of probe needles 3 penetrating the central opening 2A of the printed board 2 and connected to a printed wiring on the surface. And is attached to a fixed head of a probe device (not shown).
A cup-shaped intermediate block 4 having a flange portion 4A is fixed to the back surface side of the printed circuit board 2 by screws 5.

The flange portion 4A of the intermediate block 4
An upper block 6 that closes the central opening 2A of the printed circuit board 2 and the upper opening of the intermediate block 4 is fixed to the upper surface by screws 7, and a cooling chamber 8 to be described later is provided in the intermediate block 4.
Is formed. A thick portion 4B having a diameter smaller than the outer diameter is formed on the lower surface of the intermediate block 4.
A holding block 9 for vertically holding a large number of probe needles 3 is fitted to B, and the holding block 9 is fixed to the lower surface of the intermediate block 4 by a screw 10. Further, openings 6A, 4C and 9A are formed at the bottoms of the upper block 6, the intermediate block 4 and the holding block 9, respectively, and a large number of probe needles 3 penetrate through these openings 6A, 4C and 9A. There is.

The probe needle 3 has openings 6A, 4
Guide plate 1 attached to each of C and 9A
It is held vertically by 1, 12, and 13. That is,
Pores corresponding to the number of probe needles 3 are formed in these guide plates 11, 12 and 13, and these pores guide a large number of probe needles 3 from the upper surface of the probe card 1 to the center of the lower surface thereof. Is held vertically. Further, these probe needles 3 are fixed by synthetic resin 14 such as epoxy resin in the openings 6A of the upper block 6, and the lower ends of the probe needles 3 are electrode pads (of 8 × 2, for example) of the chips T to be inspected. (Not shown) are aligned for simultaneous contact. Of course, the probe card 1 has a number of probe needles 3 corresponding to the electrode pads of the 8 × 2 chips T as shown in FIG. Therefore, in the following description, the probe card 1
Is referred to as a multi-probe card 1.

Further, an introduction pipe 16 for guiding a cooling gas such as compressed air or compressed nitrogen from the gas supply device 15 into the cooling chamber 8 is connected to the side surface of the intermediate block 4, and the vicinity of the opening of the upper block 6 is connected. A lead-out pipe 17 for connecting the cooling gas introduced into the cooling chamber 8 to the outside is connected to the. As a result, the cooling gas is guided from the gas supply device 15 into the cooling chamber 8 of the multi-probe card 1 through the introduction pipe 16, and the gas after cooling the probe needle 3 in the cooling chamber 8 is led through the discharge pipe 17. I try to exhaust it to the outside. Further, the thermocouple 18 penetrates the opening 6A of the upper block 4 to reach the inside of the cooling chamber 8, and the thermocouple 18 is configured to monitor the temperature in the cooling chamber 8, that is, the temperature of the probe needle 3. There is. The thermocouple 18 is connected to the cooling chamber monitoring control device 20 via a wiring 19, and an electric signal 21 is sent from the cooling chamber monitoring control device 20 based on the temperature in the cooling chamber 8 detected by the thermocouple 18. To control the supply of cooling gas.

Next, referring to FIGS. 1 and 2, a preferred embodiment of a semiconductor wafer probing method of the present invention for inspecting the electrical characteristics of a chip T on a semiconductor wafer W using the multi-probe card 1 will be described. explain.

That is, the multi-probe card used in this embodiment has an even number, that is, eight vertically, as described above.
A plurality of vertical probe needles 3 corresponding to the respective electrode pads of 8 × 2 chips T, which are continuous two in the horizontal direction and continuous eight in at least one of the vertical and horizontal directions (the vertical direction in this embodiment), are provided. is doing. And this multi-probe card 1
When inspecting the chip T of the semiconductor wafer W using
As shown in FIG. 1, the orientation flat O of this multi-probe card 1 is oriented vertically. Then, 8 × 2 chip areas to be inspected by the multi-probe card 1 are set as one index area 22, and then the index area 22 is set for the semiconductor wafer W.
Is set on the semiconductor wafer W as a contact region 23, which is the minimum area formed when all the chips T on the semiconductor wafer W are covered in the vertical and horizontal directions. In this case, the contact region 23 is formed by spreading 15 index areas 22. After that, the contact area 23
As the shortest path from the first index area (1) to the last index area (15), the contact area 23
From the index area 22 at the upper end of the left end to the upper end of the right end, numbers are assigned to positions (1) to (15) in order in the meandering direction from directly below to the left end. Then, these numbers are set as the index feeding order. The order of the index area 22, the contact area 23 and the index feed is registered in a control device (not shown).

Thereafter, while moving a mounting table (not shown) of the semiconductor wafer W in accordance with the index order registered by the controller, each of the 16 chips T in each index area 22 on the semiconductor wafer W is moved. The probe needles 3 of the multi-probe card 1 are brought into contact with the electrode pads, 16 chips T are simultaneously inspected for each index feed, and this inspection is repeated 15 times to complete the inspection of all the chips T on the semiconductor wafer W. can do.

However, in the case of the conventional probing method using a multi-probe card, due to the structure of the probe card, the probe card is arranged in a horizontally long shape of two vertically and eight horizontally as shown in FIG. 1 (b). It is necessary to use a multi-probe card that simultaneously inspects the chip T. Therefore, the number of index feeds of the multi-probe card is 20 as shown in the figure. Moreover, in the conventional probing method, as compared with the present embodiment, in the right half index area 22 of the semiconductor wafer W, there are far more blank probe needles than probe needles that hit the chip to be inspected, and the inspection efficiency is extremely poor. I understand.

As described above, according to this embodiment, the number of index feedings is 5 times less than that of the conventional probing method using a multi-probe card, and the feeding number can be reduced by 25%. The inspection efficiency can be improved and the inspection cost can be significantly reduced. Moreover, by using the vertical probe needles 3 as in the present embodiment, the probe needles 3 can be simultaneously brought into contact with a plurality of chips T in an arbitrary arrangement to perform an inspection, and due to the structure of the vertical needles, the probe needles 3 can be inspected. 3 can be remarkably suppressed from being deformed, the displacement of the probe needle 3 from the electrode pad can be prevented, and highly accurate inspection can be performed. Consequently, the life of the probe needle 3 can be remarkably extended and the multi-probe The inspection cost can be further reduced by reducing the number of times the card 1 is replaced.

FIG. 2A is a diagram showing a case where 4 × 2 chips T are simultaneously inspected by using the semiconductor wafer probing method of the present invention. In this case, all the chips T on the semiconductor wafer W can be inspected by index feeding 28 times. On the other hand, in the case of the conventional method, index feeding must be performed 31 times as shown in FIG. Therefore, according to the present embodiment, the number of index feeds can be reduced by 10% compared to the conventional case. In addition, the same effects as those of the above-described embodiment can be expected.

In the above description, the multi-probe card 1 for simultaneously inspecting 16 or 8 chips T is premised, but the multi-probe card 1 and the minimum contact area are known from the beginning. Of course, by using a computer when setting the number of multiples and the minimum contact area, the time required to set the number of multiples and the minimum contact area can be significantly reduced. When a computer is used, first, as shown in the flowchart of FIG. 5, wafer information such as wafer size and orientation flat (orientation flat) direction, and chip information such as vertical and horizontal (x, y) size of the chip. (S1), and then card information about the multi-probe card such as the number of chips (multi) and the chip arrangement that can be inspected at the same time is input (S2).
Thereafter, the contact area of the multi-probe card with respect to the semiconductor wafer is simulated a plurality of times by the computer based on these input data (S3), and based on the result, the number of blank chips to be blank-blank out of the semiconductor wafer and the blank blanks thereof. The coordinates of each chip are obtained (S4), and the results are registered in the computer and stored (S5). Then, the quality of the number of index feeds and the number of blank shots is judged based on the respective results (S6), the probing method considered to be the best is determined and displayed on the display unit (S7). After the probing method is determined by the computer in this way, the semiconductor wafer W is actually probed by using the probe device.

When setting the contact area of the multi-probe card by computer simulation, there are three simulation methods of "automatic setting mode", "optimal setting mode" and "arbitrary setting mode", as will be described later. These modes can be appropriately selected by the operator based on wafer information, chip information, card information and the like. When the contact area is to be accommodated in the semiconductor wafer as in this embodiment, the simulation is performed using the "arbitrary setting mode" as described later. As a result of simulation in the "arbitrary setting mode", the number of multis is 16 or 8 as in the present embodiment.
When the multi-probe card 1 of 1 is used, the above-mentioned method can inspect most efficiently. In addition, the following FIG.
In the description using 6, the simulation for setting the contact region of the multi-probe card 1 shown in FIG. 1A will be described.

The computer 50 used in this embodiment, as shown in FIG.
By the input means 51 for inputting data such as card information, the card allocation device 52 for allocating the index area of the multi-probe card on the semiconductor wafer based on the wafer information and the card information from the input means 51, and the allocation device 52 Display means 53 for displaying images of semiconductor wafers and chips and numerical data for executing allocation of index areas. The allocation device 52 includes a coordinate calculation means 54, a chip coordinate storage section 55, a file storage section 56, a card allocation mode storage section 57, a menu storage section 58, a card allocation means 59 and a card allocation position storage section 60. There is. The input means 51 is, for example, the keyboard 5
1A and a mouse 51B. Also, the display means 5
3 is an LCD or CRT that displays graphic information
And the like, and a display control unit 53B for controlling the display information of the display unit 53A. Based on the input of the input means 51, the display unit 53A graphically displays the semiconductor wafer and the chips as shown in FIG. At the same time, the wafer information and the card information are displayed in characters.

The coordinate calculating means 54 automatically arranges quadrangular image-shaped chips on an image-shaped semiconductor wafer based on the above-mentioned wafer information and chip information inputted from the input means 51, and for each chip. Position coordinates are given. In addition, the chip coordinate storage unit 5
Reference numeral 5 is a RAM or the like, and is configured to store the respective chips and respective coordinates obtained by the coordinate calculation means 54 in association with each other. The information stored in the chip coordinate storage unit 54 is graphically displayed as a wafer map on the display unit 53A via the display control unit 53B as described above. This wafer map is displayed, for example, as shown in FIG. The file storage unit 56 is a ROM connected to the coordinate calculation unit 54.
Etc., each information relating to a plurality of types such as wafer information, chip information and card information is registered in advance. Therefore, the coordinate calculation means 54 reads the stored information in the file storage portion 54, and based on this information, performs the above-mentioned calculation processing in the same manner as the information from the input means 51, and displays the wafer map based on this information in the display portion 53A.
It is designed to be displayed graphically.

The card allocation mode storage unit 57 is
It is composed of a storage device such as a ROM, and for example, three kinds of modes of an automatic allocation mode, an optimum allocation mode and an arbitrary allocation mode are stored in advance so that an operator can select an appropriate mode. Here, the automatic allocation mode is a mode in which the contact areas are automatically allocated so that the multi-probe card makes uniform contact in both the vertical and horizontal directions of the semiconductor wafer, for example, the top, bottom, left, and right are substantially symmetrically contacted. The optimal allocation mode is a mode in which the contact areas are automatically allocated so that the number of contacts of the multi-probe card on the wafer is minimized. The arbitrary allocation mode is a mode in which the contact position of the multi-probe card can be arbitrarily set by moving the contact position with the cursor moving key of the keyboard 31A or the mouse 31B.

The menu storage unit 58 stores various operation menus required to operate the computer 50.
A map initialization menu required for setting measurement conditions and a card allocation menu used for card allocation are stored. The menu contents can be increased or decreased as needed. Then, as shown in FIG. 16, when "Map initialization" displayed on the display unit 53A is selected with the mouse 52B, all chips in the semiconductor wafer are tested, and when "Card allocation" is selected, card allocation is performed. The mode is working.

The card allocating means 59 makes contact between the chip of the semiconductor wafer and the multi-probe card based on the stored information of the chip coordinate storage section 55, the stored information of the card allocation mode storage section 57, and the command from the input means 51. The area is set. The card allocating means 59 includes an automatic allocating section 61 shown in FIG.
It has an optimum allocation unit 62 shown in FIG. 8 and an arbitrary allocation unit 63 shown in FIG.

As shown in FIG. 7, the automatic allocation unit 61 obtains the minimum value in the X-axis direction on the wafer map displayed on the display unit 53A, the minimum portion in the X-axis direction 64A, and the maximum value in the X-axis direction. X-axis maximum value portion 64B, Y-axis minimum portion 65A for obtaining the minimum value in the Y-axis direction, Y for obtaining the maximum value in the Y-axis direction
It has an axis maximum value portion 65B. The X-axis minimum value portion 64A and the X-axis maximum value portion 64B are respectively connected to an X-direction protrusion amount (X-direction blanking chip number) calculation portion 66A, and among these information and card information, the X-value of the multi-probe card is calculated. Number of chips in the X direction, the number of blank chips at the end when the multi-probe cards are arranged in an integer multiple at the row position having the maximum width in the X direction (chips protruding from the wafer and assuming that there are chips at that part) The number) Xh is calculated. The state at this time is shown in Figure 1.
4 (b) and FIG. 15 (a), and FIG.
In the upper row, the uppermost row shows a chip row having the maximum width in the X direction, and the lower row shows a hypothetical card allocation position. The left-end start position determination unit 67 is included in the X-direction blank shot chip number calculation unit 66A.
A is connected, and the left end start position determining unit 67A protrudes from the left and right (X direction) of the graphic wafer as evenly as possible on the basis of the output value of the X-direction blank ejection chip number calculation unit 66A, and the left and right blank ejection chip numbers are The left end start position xs is calculated so as to be as uniform as possible, and the card allocation position is determined. FIG. 15B shows this state.
Is.

Similarly, in the Y-axis minimum value section 65A and the Y-axis maximum value section 65B, the Y-direction blanking chip number calculation section 6 is respectively provided.
6B are connected to each other, and the number Yh of blank shot chips at the end in the Y direction is obtained as in the case described above. An upper end start position determination unit 67B is connected to the Y-direction blanking tip number calculation unit 66B, and the upper end start position determination unit 67B is connected.
Is to determine the card allocation position by obtaining the upper end start position ys based on the output value of the Y-direction blank ejection chip number calculation unit 66B so that the card protrudes as evenly as possible from above and below the graphic wafer (Y direction). . Then, the left end start position determination unit 67A and the lower end start position determination unit 67B
An automatic allocation calculation unit 68 is connected to the automatic allocation calculation unit 68, and the automatic allocation calculation unit 68 is connected to the start position determination units 67A and 67B.
The multi-probe card is automatically allocated on the basis of the output value from the left end and the lower end of the graphic wafer, and the result is stored in the card allocation storage unit 60. FIG. 14C shows the arrangement of the cards thus allocated.

The optimum allocation unit 62, as shown in FIG. 8, has X-axis minimum / maximum value units 64A, 64B and Y.
The configuration is the same as that of the automatic allocation unit 61 except that it has an increment unit 69 connected to each of the axis minimum and maximum value units 65A and 65B. This optimal allocation unit 6
2 is to determine the card allocation position by determining the left end and the upper end start position of each row of the chips on the graphic wafer, and when arranging a plurality of cards in the Y direction, The incrementing unit 69 indicates the lines to be allocated in order to automatically allocate each line or a plurality of lines. This allows the multi-probe card to contact all chips with a minimum number of contacts, i.e. a minimum contact area. FIG. 14D shows the arrangement of the cards thus allocated.

As shown in FIG. 9, the arbitrary allocating section 63 has a card reference position determining section 70, and in the case of a multi-probe card which simultaneously inspects a card reference position, for example, eight chips, As shown in FIG. 14 (e), the mouse 52 indicates which coordinate on the graphic wafer should be positioned with the leftmost channel as the reference position.
It is designed to be input by B and decided. Thereby, the card allocation position can be arranged at any position on the semiconductor wafer. That is, the automatic allocation unit 61
The optimal allocation unit 62 allocates the card regardless of whether the card protrudes from the graphic wafer. However, the arbitrary allocation unit 63 allows the operator to fit the card into the graphic wafer while looking at the display unit 53A. The contact area can be set arbitrarily.

Card allocation means 59 as described above.
The card allocation position storage unit 60 shown in FIG.
I am trying to memorize it. Further, the card allocation position storage unit 60 is configured to store the number of blank shot chips and their coordinates. Therefore, based on the stored contents, the display unit 53A displays the card allocation positions on the graphic wafer and the chips by superimposing them, for example, as shown in (c) and (d) of FIG.
The number of blank shots of the chip and the respective coordinates are known on the display section 53A.

Next, a case of simulating a contact area by allocating a multi-probe card when simultaneously inspecting four chips using the computer 50 will be described with reference to FIGS. 10 to 13. First, the wafer information, the chip information, and the card information are input using the input means 51 as in S1 and S2 described above. Then, based on this input information, the allocation device 52
The coordinate calculating means 54 allocates the chips on the image on the wafer, stores the result, and displays the wafer and the chips matching the image as the graphic wafer GW and the graphic chip GT on the display unit 53.
A is displayed as shown in FIG. After that, the operator operates the mouse 52B to execute the above-mentioned simulation as shown in FIGS.

At that time, a menu for mode selection necessary for card allocation such as "automatic setting mode", "optimum setting mode" and "arbitrary setting mode" is displayed in the area above the graphic wafer GW of the display section 53A. Yes (S1
1). Then, when a desired mode is selected from the three types of card allocation modes using the mouse 52B on the display unit 53A, the computer 50 constantly determines whether or not the mouse 52B has been pressed (S12). It is determined whether or not the mouse pointer 71 (see FIG. 16) is pointing to one of the three types of modes (S13). This is executed until one of the modes is instructed.

For example, when the automatic setting mode is selected in S14, the simulation is executed as follows. That is, the card allocating means 59 calculates the contact areas (layouts) of the cards so that the cards are substantially evenly distributed in the left-right direction of the graphic wafer GW (S15). As the calculation procedure, first, the minimum value Xmin and the maximum value Xmax in the X-axis direction are calculated among all the chip coordinates of the wafer map based on the storage data of the chip coordinate storage unit 55 (see FIG. 14B). From the difference of the card information, the number of chips in the X direction of the probe card Nx, where Nx = 4 in this case is used, and when the cards are allocated at the row position that has the maximum width in the X direction, how much the card protrudes at the wafer edge. The number of blank chips Xh is calculated based on the following formula. FIG. 15A shows the result of this calculation. Incidentally, the reason why 1 is added to the difference between Xmax and Xmin is to add the chip of the coordinate (0, 0). After executing this calculation, the process proceeds to S16. However,
In the following formula, Q represents the quotient of division, and R represents the remainder. {(Xmax-Xmin) +1} / Nx = Q ... R The number of blank chips Xh = Nx-R When this is calculated by substituting a specific numerical value, the result is as follows. {(12-(-12) +1} / 8 = 3 ... 1 Number of blank chips Xh = 8-1 = 7

In S16, the left end start position xs in the card layout in the X-axis direction is calculated based on the following formula. The following formula is for setting the amount of protrusion from both ends of the wafer, that is, the number of blank chips to be made substantially equal when the cards are laid out in the X direction. However,
In the following formula, [Xh / 2] represents a truncated integer. xs = Xmin− [Xh / 2] When numerical values are specifically substituted for this calculation, for example, FIG.
It becomes like (b). xs = -12- [7/2] =-15 That is, the coordinates (-15,0) are the start position of the card layout, the length of three chips is projected from the left edge of the wafer, and the chip is extended from the right edge. The length of four pieces protrudes.
Although the layout is started from the left side here, it may be started from the right side.

Similarly, in S17, the contents executed in S15 and S16 are executed in the Y direction to obtain the upper end start position ys of the Y axis. In this way, when the starting coordinates (xs, ys) on the wafer map are obtained, the upper left part of the probe card (here, there are two columns in the Y direction, so the channel on the upper left end) is arranged at these coordinates (xs, ys). Then, the cards are laid out on the wafer map by allocating the cards in the X direction (row direction) and the Y direction (column direction) with reference to the start coordinates on the wafer map, and displaying the result as a contact area on the display unit 53A. (S18). Figure 1 shows this state.
4 (c). The result obtained here is stored in the card allocation position storage unit 60 (S19) and finally stored in the file storage unit 56 (S20).

Next, the optimum setting mode will be described.
In this mode, the card allocation position is automatically laid out so that the number of contacts of the probe card 1, that is, the number of index feeds is minimized. To do so, firstly, the process returns to S14, and the result in this step is NO.
When the "optimum setting mode" is selected in S21 shown in FIG. 5, the storage content of the increment unit 69 indicating the row position of the allocation target chip on the wafer map is set to "0" (S22), and then the storage content i is set. Is incremented by "1" (S23).

Next, the optimum card layout is performed in the i-th row (here, the first row) on the wafer map to set the contact area. In this case, in the coordinate calculation during the card layout, the steps S15 shown in FIG. 10 and S16 and S17 shown in FIG. 11 are performed only for the first line to obtain the left end start position (S24). After that, the card layout of the first row is determined based on this left end start position, and it is displayed on the display section 53A (S
25). Further, it is determined whether the i-th row is the last row of the wafer map (S26).
And the content i of the increment unit 69 is incremented by 1,
Repeat the same calculation. After the cards have been laid out by calculating up to the last row of the chip, the process proceeds to S19 of FIG. 11 and the contact area of each laid out card is stored. At this time, (d) of FIG. 14 is displayed on the display unit 53A, and the allocation of the card with the smallest number of card index feeds is determined.

Finally, the case where the "arbitrary setting mode" is selected will be described. In this arbitrary setting mode, the operator can allocate the cards to arbitrary positions and set the contact area. To do that, first go back to FIG.
If "arbitrary setting" is selected in S27 shown in FIG. 13 in this step, it is determined whether or not the mouse button is always pressed (S28, S29). If the mouse button is released, the mouse pointer 71 at that time is Position of chip coordinates (xn,
One layout is displayed with the upper left corner of the card layout positioned at (yn) (S30). Then, the chip coordinates of the mouse pointer 71 are stored (S32). Next, it is determined whether the card layout has filled the entire wafer map (S33), and if not filled, it is determined whether the end menu has been selected (S34). If the end menu is not selected, the process returns to S28 again, waits for the next instruction, and repeats the above operation. The layout during the card layout is displayed on the display unit 53A as shown in FIG. In this way, when the card layout fills the entire wafer map, or when the end menu is selected, the process returns to S19 of FIG. 11, and the card layout position at that time is stored and filed.

When obtaining the contact region 22 in the probing method of this embodiment, any of the three modes may be used. If the number and arrangement of the multi-probe card 1 are determined, the minimum contact region 22 can be obtained in a short time by using the optimum setting mode. However, not all of the minimum contact regions 22 have the minimum number of blank chips. Therefore, in order to set the contact region 22 and the contact region 22 having the smallest number of blank shot chips, three modes are used, and the operator makes a judgment based on the respective results. Also, this determination can be performed by the computer 50. In that case, it is sufficient to incorporate the judgment software and input various conditions that are optimum conditions.

By using the computer 50 described above, it is possible to design the number and layout of multiple probe cards. To do this, various semiconductor wafers to be inspected are registered in advance in the file storage unit, various card information is input for each semiconductor wafer, and the most efficient multi-probe card is obtained based on the obtained results. If selected, an optimal multi-probe card can be obtained.

In each of the above-described embodiments, the present invention has been described in the case of simultaneously inspecting 8 × 2 chips T and 4 × 2 chips T. However, as a multi-probe card, an even number of chips are continuously connected vertically and horizontally. Also, a multi-probe card having a plurality of contacts corresponding to a plurality of four or more consecutive chips in at least one of the vertical and horizontal directions is used, and a plurality of chip areas to be inspected by the multi-probe card are used as one index area. Then, the index area is laid out vertically and horizontally and the minimum area formed when all the chips on the semiconductor wafer are covered is set as the contact area on the semiconductor wafer. Index the multi-probe card according to the shortest path from the index area to the last index area. If it is a method to send
All are included in the present invention. The present invention also includes a case where a computer is used to project a wafer and chips on a display unit such as a CRT or LCD and a contact region is designed on the wafer. Further, although the vertical probe card is used as the contactor of the multi-probe card in the above embodiment, a membrane card may be used when the present invention is carried out.

[0045]

As described above, according to the invention described in claim 1 of the present invention, a plurality of probe cards which are continuous in even numbers in the vertical and horizontal directions and are continuous in four or more in at least one of the vertical and horizontal directions. In addition to using a probe card having a plurality of contacts corresponding to the above chips, the area to be simultaneously inspected by the probe card is defined as one index area, and this index area is spread vertically and horizontally to cover all the chips on the semiconductor wafer. Since the contact target area having the smallest area is set on the semiconductor wafer, and the contacts are sequentially brought into contact with the index area in a predetermined index order in the contact target area,
It is possible to provide a semiconductor wafer probing method that reduces the number of index feeds and improves inspection efficiency.

According to the second aspect of the present invention, since the minimum contact area of the multi-probe card is set while observing the display section of the computer, the number of index feeds can be reduced and the number of blanks can be reduced. Set the minimum contact area to reduce the number of driven chips in a short time,
Moreover, it is possible to provide a semiconductor wafer probing method that reduces the number of index feeds and improves inspection efficiency.

[0047]

[Brief description of drawings]

FIG. 1 is a view showing a method of simultaneously inspecting 16 chips on a semiconductor wafer, wherein FIG. 1A shows an inspection order of chips on a semiconductor wafer according to an embodiment of a semiconductor wafer probing method of the present invention. A plan view and FIG. 1B are plan views showing an inspection order of chips of a semiconductor wafer by a conventional semiconductor wafer probing method.

FIG. 2 is a view showing a method of simultaneously inspecting eight chips on a semiconductor wafer, and FIG. 2A shows an inspection order of chips on a semiconductor wafer according to an embodiment of a semiconductor wafer probing method of the present invention. A plan view and FIG. 1B are plan views showing an inspection order of chips of a semiconductor wafer by a conventional semiconductor wafer probing method.

FIG. 3 is a perspective view showing a probe card of a probe device that is preferably used in the semiconductor wafer probing method of the present invention.

FIG. 4 is a cross-sectional view showing the probe card shown in FIG.

FIG. 5 is a flowchart showing an embodiment of a semiconductor wafer probing method according to the present invention.

FIG. 6 is a block diagram showing a main part of a computer used when implementing the semiconductor wafer probing method of the present invention.

7 is a block diagram showing an automatic allocation unit of the computer shown in FIG.

8 is a block diagram showing an optimum allocation unit of the computer shown in FIG.

9 is a block diagram showing an arbitrary allocation unit of the computer shown in FIG.

FIG. 10 is a flowchart showing a flow when allocating a multi-probe card.

FIG. 11 is a flowchart showing a flow when allocating a multi-probe card.

FIG. 12 is a flowchart showing a flow when allocating a multi-probe card.

FIG. 13 is a flowchart showing a flow when allocating a multi-probe card.

14 (a), (b), (c), (d), and (e) are all diagrams showing a graphic display of a display unit when a multi-probe card is allocated.

15 (a) and 15 (b) are schematic diagrams showing a part of a calculation process when allocating a multi-probe card.

FIG. 16 is a diagram showing an initial screen of a display unit.

FIG. 17 is a diagram showing a part of a probe needle of a conventional probe card and an arrangement of chips to be inspected by the probe card, FIG. 17 (a) is a perspective view showing a part of the probe needle in a normal state; 11B is a diagram corresponding to FIG. 19A showing the probe needle in a deformed state, and FIG. 19C is a plan view showing an array of chips to be inspected by the probe needle shown in FIG.

FIG. 18 is a diagram showing a part of a probe needle of another conventional probe card and an arrangement of chips to be inspected by the probe card. FIG. 18A is a perspective view showing a part of the probe needle in a normal state. The figure, the figure (b) is the figure corresponding to the figure (a) showing the probe needle in a deformed state, and the figure (c) is the figure (a).
FIG. 6 is a plan view showing an arrangement of chips to be inspected by the probe needle of FIG.

[Explanation of symbols]

 1 Probe Card 3 Vertical Probe Needle (Contact) 22 Index Area 23 Contact Area 50 Computer 51 Input Means 53A Display Section W Semiconductor Wafer T Chip GW Graphic Wafer GT Graphic Chip

Claims (2)

[Claims] 1. When inspecting electrical characteristics of chips arranged on a semiconductor wafer using a probe card, index feed is sequentially performed while simultaneously contacting probe needles with electrode pads of a plurality of chips. In a probing method of a semiconductor wafer in which contacts are brought into contact with all the chips, a plurality of contacts corresponding to a plurality of chips which are continuous in an even number in the vertical and horizontal directions and four or more continuous in at least one of the vertical and horizontal directions as the probe card. This is formed when a multi-probe card having a child is used and an area to be simultaneously inspected by this multi-probe card is set as one index area, and then this index area is spread vertically and horizontally to cover all the chips on the semiconductor wafer. The above-mentioned semiconductor window A method of probing a semiconductor wafer, which comprises indexing the semiconductor wafer according to the shortest path from the first index area to the last index area in the contact area after setting on the roof. 2. When inspecting the electrical characteristics of chips arranged on a semiconductor wafer using a probe card, index feed is sequentially performed while simultaneously contacting probe needles with electrode pads of a plurality of chips. In a probing method of a semiconductor wafer in which contacts are brought into contact with all the chips, a plurality of contacts corresponding to a plurality of chips which are continuous in an even number in the vertical and horizontal directions and four or more continuous in at least one of the vertical and horizontal directions as the probe card. When testing using a multi-probe card with a child,
After the semiconductor wafer and the chip are graphically displayed on the display unit of the computer, an area to be simultaneously tested by the multi-probe card is set as one index area on the display unit of the computer, and then this index area is graphically displayed on the wafer. After setting the area that is the smallest area formed when covering all the chips displayed graphically by laying it vertically and horizontally as the contact area in the above-mentioned display part, within this contact area from the first index area to the last A method for probing a semiconductor wafer, which comprises indexing the semiconductor wafer according to a shortest path to an index area.