JP3889879B2 - 仮想メモリ変換を制御する方法 - Google Patents

仮想メモリ変換を制御する方法 Download PDF

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Publication number
JP3889879B2
JP3889879B2 JP17440198A JP17440198A JP3889879B2 JP 3889879 B2 JP3889879 B2 JP 3889879B2 JP 17440198 A JP17440198 A JP 17440198A JP 17440198 A JP17440198 A JP 17440198A JP 3889879 B2 JP3889879 B2 JP 3889879B2
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Japan
Prior art keywords
message
memory
data
register
status
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English (en)
Japanese (ja)
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JPH1185618A (ja
JPH1185618A5 (enExample
Inventor
トニー・エム・ブルーアー
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP17440198A 1997-06-24 1998-06-22 仮想メモリ変換を制御する方法 Expired - Fee Related JP3889879B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/881,196 US6668314B1 (en) 1997-06-24 1997-06-24 Virtual memory translation control by TLB purge monitoring
US881,196 1997-06-24

Publications (3)

Publication Number Publication Date
JPH1185618A JPH1185618A (ja) 1999-03-30
JPH1185618A5 JPH1185618A5 (enExample) 2005-04-07
JP3889879B2 true JP3889879B2 (ja) 2007-03-07

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ID=25377975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17440198A Expired - Fee Related JP3889879B2 (ja) 1997-06-24 1998-06-22 仮想メモリ変換を制御する方法

Country Status (2)

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US (2) US6668314B1 (enExample)
JP (1) JP3889879B2 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668314B1 (en) * 1997-06-24 2003-12-23 Hewlett-Packard Development Company, L.P. Virtual memory translation control by TLB purge monitoring
US6766472B2 (en) * 2000-09-22 2004-07-20 Microsoft Corporation Systems and methods for replicating virtual memory on a host computer and debugging using the replicated memory
US20020087765A1 (en) * 2000-12-29 2002-07-04 Akhilesh Kumar Method and system for completing purge requests or the like in a multi-node multiprocessor system
US7430643B2 (en) * 2004-12-30 2008-09-30 Sun Microsystems, Inc. Multiple contexts for efficient use of translation lookaside buffer
US7506132B2 (en) * 2005-12-22 2009-03-17 International Business Machines Corporation Validity of address ranges used in semi-synchronous memory copy operations
US8032716B2 (en) * 2008-02-26 2011-10-04 International Business Machines Corporation System, method and computer program product for providing a new quiesce state
US8019922B2 (en) * 2008-10-21 2011-09-13 International Business Machines Corporation Interruption facility for adjunct processor queues
US20110219016A1 (en) * 2010-03-04 2011-09-08 Src, Inc. Stream Mining via State Machine and High Dimensionality Database
US10248573B2 (en) 2016-07-18 2019-04-02 International Business Machines Corporation Managing memory used to back address translation structures
US10168902B2 (en) 2016-07-18 2019-01-01 International Business Machines Corporation Reducing purging of structures associated with address translation
US10180909B2 (en) 2016-07-18 2019-01-15 International Business Machines Corporation Host-based resetting of active use of guest page table indicators
US10162764B2 (en) 2016-07-18 2018-12-25 International Business Machines Corporation Marking page table/page status table entries to indicate memory used to back address translation structures
US10176110B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Marking storage keys to indicate memory used to back address translation structures
US10282305B2 (en) 2016-07-18 2019-05-07 International Business Machines Corporation Selective purging of entries of structures associated with address translation in a virtualized environment
US10802986B2 (en) 2016-07-18 2020-10-13 International Business Machines Corporation Marking to indicate memory used to back address translation structures
US10176111B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Host page management using active guest page table indicators
US10176006B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Delaying purging of structures associated with address translation
US10241924B2 (en) 2016-07-18 2019-03-26 International Business Machines Corporation Reducing over-purging of structures associated with address translation using an array of tags
US10223281B2 (en) 2016-07-18 2019-03-05 International Business Machines Corporation Increasing the scope of local purges of structures associated with address translation
US10169243B2 (en) 2016-07-18 2019-01-01 International Business Machines Corporation Reducing over-purging of structures associated with address translation
US10169233B2 (en) * 2017-06-05 2019-01-01 International Business Machines Corporation Translation lookaside buffer purging with concurrent cache updates
US10353825B2 (en) 2017-06-16 2019-07-16 International Business Machines Corporation Suspending translation look-aside buffer purge execution in a multi-processor environment

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456954A (en) * 1981-06-15 1984-06-26 International Business Machines Corporation Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations
JPS59227098A (ja) * 1983-06-08 1984-12-20 Fujitsu Ltd Ｔｌｂパ−ジリカバリ方式
JPS60254346A (ja) * 1984-05-31 1985-12-16 Toshiba Corp マルチプロセツサシステム
US5574936A (en) * 1992-01-02 1996-11-12 Amdahl Corporation Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system
JPH0784883A (ja) * 1993-09-17 1995-03-31 Hitachi Ltd 仮想計算機システムのアドレス変換バッファパージ方法
JPH07248974A (ja) * 1994-03-10 1995-09-26 Hitachi Ltd 情報処理装置
US5906001A (en) * 1996-12-19 1999-05-18 Intel Corporation Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
US6668314B1 (en) * 1997-06-24 2003-12-23 Hewlett-Packard Development Company, L.P. Virtual memory translation control by TLB purge monitoring
US5966733A (en) * 1997-06-24 1999-10-12 Hewlett-Packard Company Optimizing data movement with hardware operations

Also Published As

Publication number Publication date
JPH1185618A (ja) 1999-03-30
US20040221131A1 (en) 2004-11-04
US6668314B1 (en) 2003-12-23
US7117338B2 (en) 2006-10-03

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