JP3887114B2 - LCD display driver circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LCD driving circuit for driving a liquid crystal display (hereinafter referred to as “LCD”) based on digital luminance data corresponding to the luminance of a display pixel.
[0002]
[Prior art]
FIG. 2 is a configuration diagram of a conventional LCD driving circuit.
The LCD drive circuit drives the LCD 10 to display a screen. The LCD 10 includes a plurality of X electrodes 11 in the vertical (column) direction._i(Where i = 1, 2,...), And a plurality of Y electrodes 12 in the horizontal (row) direction arranged orthogonally thereto._j(Where j = 1, 2,...). X electrode 11_iAnd Y electrode 12_jInsulated gate field effect transistor (hereinafter referred to as “MOS”) 13_{i, j}And liquid crystal display element 14_{i, j}Is arranged, and this MOS13_{i, j}The source of X electrode 11_iThe gate is the Y electrode 12_jIn addition, the drain is the liquid crystal display element 14._{i, j}Are respectively connected to the common electrode 15. Each Y electrode 12_jIs a scanning signal line 21 of the scanning circuit 20._j(Where j = 1, 2,...) And the scanning signal line 21₁, 21₂,... Are driven by scanning signals sequentially applied to.
[0003]
On the other hand, each X electrode 11 of the LCD 10_iThe driven Y electrode 12_jA driving voltage DVi corresponding to the luminance of each pixel in the row corresponding to is supplied from the LCD driving circuit. Adjacent X electrode 11_i, 11_{i + 1}In order to perform display without flicker, drive voltages DVi and DVi + 1 having different positive and negative polarities are applied to the common electrode 15. Further, the polarities of the drive voltages DVi and DVi + 1 are alternately switched every frame in order to extend the life of the LCD 10.
[0004]
The LCD driving circuit includes a shift register 30, a data register 40, a data latch 50, a level shifter (not shown), a digital / analog converter (hereinafter referred to as “DA converter”) 60, and an output buffer 70.
The shift register 30 is composed of cascade-connected flip-flops, and sequentially outputs the mark signals M1, M2,... To the data register 40 in synchronization with the clock signal CLK given subsequent to the start signal ST. .
The data register 40 includes a plurality of registers for storing the luminance data Di for each pixel for one row, and stores the luminance data D1, D2,... In each register in synchronization with the mark signals M1, M2,. Is.
The data latch 50 includes a plurality of latch circuits that store the luminance data Di for one row stored in the data register 40. Then, the luminance data Di for one row stored in the data register 40 is stored in a plurality of latch circuits collectively in synchronization with the strobe signal STB. The luminance data Di stored in the data latch 50 is converted to a logic level corresponding to the DA converter 60 in the subsequent stage by a level shifter (not shown) and is given.
[0005]
The DA converter 60 converts each luminance data Di into a luminance signal Bi having a positive or negative voltage corresponding to the value (for example, 0 to 63), and converts the positive and negative luminance signals applied to the LCD 10. It is designed to output.
The DA converter 60 includes reference voltage generation units 61 and 62 that generate positive and negative reference voltages, respectively. The reference voltage generation units 61 and 62 have the same configuration, and each has 63 resistors connected in series, and has a total of 64 nodes at both ends and connection points of the resistors. 64 positive reference voltages are output from 64 nodes by applying positive voltages V0 to V4 from the outside to both ends and some nodes in the middle of the reference voltage generation unit 61. Also, 64 negative reference voltages are output from 64 nodes by applying negative voltages V5 to V9 from the outside to both ends and some nodes in the middle of the reference voltage generating unit 62. Yes.
[0006]
The output side of the reference voltage generation unit 61 has each decoder (DEC) 63._iAre connected in common to the input side, and the output side of the reference voltage generator 62 is connected to each decoder 64._iCommonly connected to the input side. Each decoder 63_i, 64_iIn the selection terminal, luminance data D_iIs to be given. Further, each decoder 63_i, 64_iHas an enable terminal and an odd-numbered decoder 63._i, 64_iThe polarity control signal POL is given to the enable terminal of the even-numbered decoder 63._i, 64_iThe inverted polarity control signal / POL is applied to the enable terminal.
Each decoder 63_i, 64_iIs composed of a plurality of analog switches, and when the polarity control signals POL, / POL are at the level “H”, the luminance data D_iThe input side reference voltage is selected based on the luminance signal B_iIs output. Decoder 63_i, 64_iAre connected to the input side of the output buffer 70. The output buffer 70 is constituted by a voltage follower circuit using an operational amplifier, and each luminance signal B given from the DA converter 60 is provided._iAmplifying the power of each X electrode 11 of the LCD 10_iThe drive voltage DVi is output.
[0007]
Next, the operation will be described.
Here, it is assumed that the polarity control signal POL is alternately switched to “H” and “L” in units of one frame and is currently “H”.
The luminance data D1, D2,... Input in synchronization with the clock signal CLK are sequentially stored in the registers in the data register 40 by the mark signals M1, M2,. When the luminance data D1, D2,... For one row is stored in the data register 40, the luminance data D1, D2,... In the data register 40 are collectively stored in the data latch 50 by the strobe signal STB. Is done. The luminance data D1, D2,... In the data latch 50 is given to the DA converter 60 through a level shifter.
[0008]
Here, since the polarity signal POL is “H”, the odd-numbered decoder 63 of the DA converter 60.₁, 63₃,..., And even-numbered decoder 64₂, 64₄, ... can be operated. As a result, the odd-numbered decoder 63₁, 63₃,... Output positive polarity luminance signals B1, B3,... Corresponding to the luminance data D1, D3,.₂, 64₄,... Output luminance signals B2, B4,... Having negative polarity corresponding to the luminance data D2, D4,. These luminance signals D1, D2,... Are power amplified by the output buffer 70, and each X electrode 11 of the LCD 10 is used._iGiven to.
[0009]
On the other hand, the scanning circuit 20 generates a scanning signal for the row to be displayed, and the Y electrode 12 of the LCD 10._jGiven to. Thus, the Y electrode 12 of the LCD 10_jMOS13 connected to_{1, j}, 13_{2, j},... Are turned on, and the liquid crystal display element 14 connected to these drains_{1, j}, 14_{2, j},..., Each X electrode 11₁, 11₂,... Are applied with drive voltages DV1, DV2,. Odd-numbered X electrode 11₁, 11₃,... Are applied with positive drive voltages DV1, DV3,.₂, 11₄,... Are applied with negative drive voltages DV2, DV4,. And each liquid crystal display element 14_{i, j}Then, X electrode 11_iThe brightness is displayed in accordance with the difference between the drive voltage DVi of the current and the reference potential of the common electrode 15. When one frame is scanned from the first row to the last row, the polarity control signal POL is switched to “L” in the next frame.
[0010]
When the polarity control signal POL becomes “L”, the DA converter 60 uses an odd-numbered decoder 64.₁, 64₃,..., And even-numbered decoder 63₂, 63₄, ... can be operated. As a result, the odd-numbered decoder 64₁, 64₃,... Output luminance signals B1, B3,.₂, 63₄,... Output positive polarity luminance signals B2, B4,. Accordingly, each liquid crystal display element 14 of the LCD 10 is displayed._{i, j}The drive voltage DVi applied to is inverted to the opposite polarity to the previous frame.
Thus, the liquid crystal display element 14_{i, j}Thus, it is possible to extend the life of the LCD 10 and to improve display quality such as no flickering on the screen.
[0011]
[Problems to be solved by the invention]
However, the conventional LCD driving circuit has the following problems.
Each decoder 63 in the DA converter 60_i, 64_iAre each 6-bit luminance data D_iTo select one of the 64 reference voltages on the input side and select the luminance signal B_iIs output. Therefore, each decoder 63_i, 64_iFor example, analog switches need to be combined in a 64 × 6 matrix, and the circuit scale is larger than that of other data latches 50, output buffers 70, and the like. Moreover, the DA converter 60 includes two sets of reference voltage generators 61 and 62 having the same configuration and a decoder 63 in order to generate the positive and negative luminance signals Bi._i, 64_iThere is a problem that the circuit scale of the DA converter 60 becomes extremely large.
Furthermore, since it is necessary to apply the positive voltages V0 to V4 and the negative voltages V5 to V9 to the two reference voltage generation units 61 and 62 from the outside, there is a problem that the circuit scale of the outside increases.
The present invention solves the problems of the prior art and provides an LCD drive circuit capable of simplifying the circuit scale.
[0012]
[Means for Solving the Problems]
  In order to solve the above problems, a first invention of the present invention is:Data storage means for storing brightness data to be displayed on a plurality of display electrodes of a liquid crystal display, brightness signal generation means for generating a brightness signal according to the brightness data, and polarity of the brightness signal is inverted according to a polarity control signal The display driving means in the liquid crystal display driving circuit provided with the display driving means for applying to the display electrodes is configured as follows.
  That is, the display driving means is provided for every two adjacent display electrodes of the plurality of display electrodes, and the even-numbered and odd-numbered luminance signals generated by the luminance signal generating means are the first and second luminance signals, respectively. When the polarity control signal is applied to the input terminal and the polarity control signal is the first control value, the signals of the first and second input terminals are output to the first and second output terminals, respectively, and the polarity control signal is The first switch unit for outputting the signals of the first and second input terminals to the second and first output terminals, respectively, and the first output terminal of the first switch unit for the control value of A first amplifier that amplifies the output signal without inverting its polarity, and a second amplifier that amplifies the signal output from the second output terminal of the first switch unit by inverting its polarity. And the first and second amplifiers. First and second input terminals to which signals are respectively applied, and first and second output terminals connected to the adjacent even-numbered and odd-numbered display electrodes, respectively, and the polarity control signal is a first When the control value is the second control value, the signals applied to the first and second input terminals are output to the first and second output terminals, respectively. When the polarity control signal is the second control value, the first and second output terminals are output. The second switch unit outputs the signal given to the second input terminal to the second and first output terminals, respectively.
[0013]
  The second invention isData storage means for storing brightness data to be displayed on a plurality of display electrodes of a liquid crystal display, brightness signal generation means for generating a brightness signal according to the brightness data, and polarity of the brightness signal is inverted according to a polarity control signal The display driving means in the liquid crystal display driving circuit including the display driving means having a plurality of operational amplifiers applied to the display electrodes is configured as follows.
  That is, when the polarity control signal is the first control value, the odd-numbered operational amplifier of the display driving means inverts and outputs the polarity of the luminance signal, and when the polarity control signal is the second control value. The even-numbered operational amplifier outputs without inverting the polarity of the luminance signal when the polarity control signal is the first control value, and outputs the luminance signal without inverting the polarity of the luminance signal. When the polarity control signal is the second control value, the polarity of the luminance signal is inverted and output.
[0014]
  According to a third aspect of the present invention, a liquid crystal display driving circuit includes a luminance signal generation unit that generates first and second luminance signals according to a potential level selected based on luminance data, and the input first or second input A display driver having a switch unit that selectively outputs a luminance signal, and an amplifier unit that amplifies the first or second luminance signal selected by the switch unit to generate a first or second drive voltage It consists of and.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a configuration diagram of an LCD drive circuit showing a first embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.
This LCD driving circuit drives the LCD 10 and displays a screen, similarly to the conventional LCD driving circuit of FIG.
The LCD 10 is the same as that in FIG. 2, and a plurality of vertical display electrodes (for example, X electrodes) 11 arranged in parallel at equal intervals._i(Where i = 1, 2,...) And a plurality of lateral scanning electrodes (for example, Y electrodes) 12 arranged at equal intervals orthogonally to this._j(Where j = 1, 2,...). X electrode 11_iAnd Y electrode 12_jAt the intersection of, MOS13_{i, j}And liquid crystal display element 14_{i, j}Is arranged. And MOS13_{i, j}The source of X electrode 11_iThe gate is the Y electrode 12_jIn addition, the drain is the liquid crystal display element 14._{i, j}Are respectively connected to the common electrode 15. The common electrode 15 is connected to the reference potential Vop. Each Y electrode 12_jAre each scanning signal line 21 of the scanning circuit 20._jThese scanning signal lines 21 are connected to₁, 21₂,... Are repeatedly driven from top to bottom by scanning signals sequentially applied from.
[0020]
On the other hand, each X electrode 11 of the LCD 10_iThe driven Y electrode 12_jA driving voltage DVi corresponding to the luminance of each pixel in the row corresponding to is supplied from the LCD driving circuit. Adjacent X electrode 11 of LCD 10_i, 11_{i + 1}In order to perform display without flicker, drive voltages DVi and DVi + 1 having different positive and negative polarities with respect to the reference potential Vop of the common electrode 15 are applied. Furthermore, the X electrode 11_i, 11_{i + 1}The polarities of the drive voltages DVi and DVi + 1 applied to are alternately switched every frame (or one field) in order to extend the life of the LCD 10.
The LCD drive circuit includes data storage means (for example, shift register 30, data register 40, and data latch 50) similar to FIG. 2, level shifter not shown, and luminance signal generation means (for example, DA converter) different from FIG. 60A and display drive means (for example, output buffer) 70A.
[0021]
That is, the shift register 30 is composed of cascade-connected flip-flops having the number of stages corresponding to the number of pixels in the horizontal direction of the LCD 10 (that is, pixels for one row), and the clock register CLK applied following the start signal ST. Synchronously, the mark signals M1, M2,. The mark signals M1, M2,... Are output as timing signals for the data register 40.
The data register 40 is composed of a plurality of registers for storing, for example, 6-bit luminance data Di for each pixel of one row of the LCD 10, and is synchronized with the mark signals M1, M2,. The brightness data D1, D2,... Are sequentially stored in the respective registers. The luminance data D1, D2,... Are given to the data latch 50.
[0022]
The data latch 50 is composed of a plurality of latch circuits for storing luminance data D1, D2,... For one row stored in the data register 40. In addition, in synchronization with the strobe signal STB given when all the luminance data D1, D2,... For one row is stored in the data register 40, the luminance data D1, D2,. It is stored in the circuit. The luminance data D1, D2,... Stored in the data latch 50 is converted to a logic level on the input side of the subsequent DA converter 60A by a level shifter (not shown) and is given to the DA converter 60A.
The DA converter 60A converts the luminance signals D1, D2,... Given from the data latch 50 into the luminance signals B1, B2,.
The DA converter 60A includes a reference voltage generation unit 61 that generates 64 reference voltages, and each X electrode 11 of the LCD 10._iDecoder (DEC) 63 provided corresponding to_iIt consists of and.
[0023]
The reference voltage generation unit 61 is a liquid crystal display element 14 of the LCD 10._{i, j}In FIG. 4, 64 reference voltages subjected to γ correction are generated so that a luminance proportional to the value of the luminance data Di is obtained. The reference voltage generation unit 61 is configured by connecting 63 resistors in series, and has a total of 64 nodes at both ends and connection points of the resistors. By applying γ correction voltages V0 to V4 corresponding to a γ correction curve approximated by a broken line to both ends and an intermediate node of the reference voltage generator 61, 64 γ corrected reference voltages from 64 nodes are provided. Can be obtained.
The output side of the reference voltage generator 61 is connected to each decoder 63._iCommonly connected to the input side. Each decoder 63_iThe selection terminal is supplied with luminance data Di from the data latch 50 via a level shifter. Each decoder 63_iIs composed of a plurality of analog switches combined in, for example, a 64 × 6 matrix, and one of 64 reference voltages on the input side is selected based on 6-bit luminance data Di given to the selection terminal. Is selected and output as the luminance signal Bi. Decoder 63_iIs connected to the input side of the output buffer 70A.
[0024]
The output buffer 70A amplifies or inverts each luminance signal Bi given from the DA converter 60A in accordance with the polarity control signal POL, and each X electrode 11 of the LCD 10_iAre alternately driven by positive and negative drive signals.
The output buffer 70A has adjacent odd-numbered and even-numbered luminances given to the first and second input sides in accordance with the polarity control signal POL which is alternately switched between “H” and “L” in units of frames, for example. The switch unit 71 outputs the signals B2k-1 and B2k (for example, B1 and B2) to the first and second output sides while switching the signals B2k-1 and B2k (for example, B1 and B2) without change._k(For example, 71₁)have. Switch unit 71₁The first output side of the non-inverting amplifier 72₁However, an inverting amplifier 73 is provided on the second output side.₁Are connected to each other. Non-inverting amplifier 72₁And inverting amplifier 73₁The output side of the switch section 71₁Switch section 74 similar to₁Are connected to the first and second input sides. Switch part 74₁The first and second output sides of the LCD 10 are adjacent odd-numbered and even-numbered X electrodes 11 of the LCD 10.₁, 11₂It is connected to the.
[0025]
FIG. 3 is a block diagram showing details of the output buffer 70A in FIG. In FIG. 3, only the circuits for the luminance signals B1 and B2 given from the DA converter 60A are illustrated, but the same applies to the other adjacent odd-numbered and even-numbered luminance signals B2k-1 and B2k.
Switch unit 71₁Are constituted by analog switches (hereinafter referred to as “SW”) 71a, 71b, 71c, 71d. SWs 71 a and 71 d are switches that are turned on when the polarity control signal POL is “H”, and SWs 71 b and 71 c are switches that are turned on when the polarity control signal POL is “L”. A luminance signal B1 is given to the input side of SWs 71a and 71c, and a luminance signal B2 is given to the input side of SWs 71b and 71d.
The output side of the SWs 71a and 71b is a non-inverting amplifier (for example, operational amplifier) 72.₁Is connected to the + input terminal. Operational amplifier 72₁The output side of the operational amplifier 72₁A non-inverting amplifier having a voltage amplification factor of 1 by a voltage follower circuit is configured.
[0026]
The output side of the SWs 71c and 71d is the inverting amplifier 73.₁Is connected to the input side. Inverting amplifier 73₁Is an amplifier circuit having a voltage amplification factor of −1 and comprising capacitors 73a and 73b and an operational amplifier 73c, and a reference potential Vop is applied to the + input terminal of the operational amplifier 73c. Thus, the voltage applied from the output side of the SWs 71c and 71d is inverted with respect to the reference potential Vop to be amplified.
Switch part 74₁The switch unit 71₁In the same manner as above, SWs 74a, 74b, 74c, and 74d are configured. SW74a and 74d are switches that are turned on when the polarity control signal POL is “H”, and SW74b and 74c are switches that are turned on when the polarity control signal POL is “L”. The input side of SWs 74a and 74c is an operational amplifier 72.₁The output side of SW74b, 74d is the inverting amplifier 73.₁Are connected to the output side. Then, the X electrode 11 of the LCD 10 is output from the output side of the SWs 74a and 74b.₁Drive voltage DV1 to the X electrode 11 of the LCD 10 from the output side of SW74c, 74d.₂The drive voltage DV2 is output for each.
[0027]
Next, the operation will be described.
Here, it is assumed that the polarity control signal POL is switched to “H” and “L” alternately, for example, in units of one frame, and is currently “H”.
The luminance data D1, D2,... Input in synchronization with the clock signal CLK are sequentially stored in the registers in the data register 40 by the mark signals M1, M2,. When the luminance data D1, D2,... For one row is stored in the data register 40, the luminance data D1, D2,... In the data register 40 are collectively stored in the data latch 50 by the strobe signal STB. Is done. The luminance data D1, D2,... In the data latch 50 is given to the DA converter 60A through the level shifter.
In the DA converter 60A, 64 reference voltages γ-corrected by the reference voltage generation unit 61 are generated, and each decoder 63₁, 63₂, ... are given. Each decoder 63₁, 63₂,..., The reference voltage corresponding to the luminance signals D1, D2,... Is selected and the luminance signals B1, B2,... Are output and applied to the output buffer 70A.
[0028]
Here, since the polarity control signal POL is “H”, the odd-numbered luminance signals B1, B3,.₁, 71₂,... Through non-inverting amplifier 72₁, 72₂,... Are amplified and further switched by the switch unit 74.₁74₂,... As drive voltages DV1, DV3,...₁, 11₃Applied to. The even-numbered luminance signals B2, B4,.₁, 71₂,...₁, 73₂,... Are amplified and further switched by the switch unit 74.₁74₂,..., As drive voltages DV2, DV4,.₂, 11₄Applied to.
[0029]
On the other hand, the scanning circuit 20 generates a scanning signal for the row to be displayed, and the scanning signal line 21._iVia the Y electrode 12 of the LCD 10_jGiven to.
Thus, the Y electrode 12 of the LCD 10_jMOS13 connected to_{1, j}, 13_{2, j},... Are turned on, and each MOS 13_{1, j}, 13_{2, j},... Liquid crystal display element 14 connected to the drains_{1, j}, 14_{2, j},..., Each X electrode 11₁, 11₂,... Are applied with drive voltages DV1, DV2,... Corresponding to the luminance signals B1, B2,. Odd-numbered X electrode 11₁, 11₃,... Are applied with positive polarity drive voltages DV1, DV3,.₂, 11₄,... Are applied with negative polarity drive voltages DV2, DV4,. And each liquid crystal display element 14_{i, j}Then, X electrode 11_iThe brightness is displayed in accordance with the difference between this voltage and the reference potential Vop of the common electrode 15. When one frame is scanned from the first row to the last row in this way, the polarity control signal POL is switched to “L” in the next frame.
[0030]
When the polarity control signal POL becomes “L”, the switch unit 71 of the output buffer 70A._k74_kIs switched to a tucked connection. As a result, the odd-numbered luminance signals B1, B3,.₁, 71₂,...₁, 73₂,... Are amplified, and further, the switch unit 74.₁74₂,... Odd-numbered X electrodes 11 of the LCD 10₁, 11₃,... Are applied as drive voltages DV1, DV3,. The even-numbered luminance signals B2, B4,.₁, 71₂,... Through non-inverting amplifier 72₁, 72₂,... Are amplified, and further, the switch unit 74.₁74₂,... Through the even-numbered X electrodes 11₂, 11₄,... Are applied as drive voltages DV2, DV4,.
Accordingly, each liquid crystal display element 14 of the LCD 10 is displayed._{i, j}The drive voltage DVi applied to is inverted to a polarity opposite to that of the previous frame. Thus, the liquid crystal display element 14_{i, j}Thus, the life of the LCD 10 can be extended. Further, the liquid crystal display element 14 of the LCD 10._{i, j}The flicker caused by the difference in luminance due to the polarity of the voltage applied to can be suppressed, and the display quality can be maintained.
[0031]
As described above, the LCD drive circuit of the first embodiment has the output buffer 70A that outputs the drive voltage DVi by alternately inverting the polarity of the luminance signal Bi by the polarity control signal POL. The output buffer 70A converts the odd-numbered and even-numbered luminance signals B2k-1 and B2k into the non-inverting amplifier 72 according to the polarity control signal POL._kAnd inverting amplifier 73_kIt is configured to amplify by switching alternately. Therefore, the switch section 71 for switching_k74_kThe circuit scale of the output buffer 70A is only slightly increased.
On the other hand, since the DA converter 60A does not need to generate the negative luminance signal Bi, the circuit scale is halved compared to the conventional DA converter 60, and the circuit configuration can be greatly simplified. is there.
[0032]
Second embodiment
FIG. 4 is a configuration diagram of an output buffer showing a second embodiment of the present invention.
This output buffer 70B is used in place of the output buffer 70A in FIG. In FIG. 4, only circuits for the luminance signals B1 and B2 given from the DA converter 60A are illustrated, but the same applies to the other adjacent odd-numbered and even-numbered luminance signals B2k-1 and B2k.
This output buffer 70B is provided with, for example, a SW75 to which a luminance signal B1 is given.₁, 76₁have. SW75₁The output side of the capacitor 77₁Through an operational amplifier 78₁Connected to the negative input terminal. Operational amplifier 78₁Between the output terminal and the negative input terminal is a feedback capacitor 79.₁And SW80₁Is connected. SW76₁The output side of the operational amplifier 78₁Connected to the + input terminal of the operational amplifier 78 and further to the operational amplifier 78.₁The + input terminal of SW81₁The reference potential Vop is supplied via the.
These SW75₁, 81₁Is a switch that is turned on when the polarity control signal POL is “L”.₁, 80₁Is a switch that is turned on when the polarity control signal POL is "H". The operational amplifier 78₁The drive voltage DV1 is output from the output side.
[0033]
On the other hand, the luminance signal B2 is similarly SW75.₂, 76₂, 80₂, 81₂, Capacitor 77₂79₂And operational amplifier 78₂The drive voltage DV2 is output by the amplifier circuit configured as follows. However, SW75₂, 76₂, 80₂, 81₂The polarity control signal POL is inverted by the inverter 82, and the inverted polarity control signal / POL is given as a control signal.
In such an output buffer 70B, for example, when the polarity control signal POL is “H”, the SW75₁, 81₁Turns off and SW76₁, 80₁Is turned on. Thus, the operational amplifier 78₁Is formed, and the luminance signal B1 is output as the positive drive voltage DV1. On the other hand, SW75₂, 81₂Turns on and SW76₂, 80₂Is turned off. Thus, the operational amplifier 78₂The luminance signal B2 is output as a negative drive voltage DV2 with the polarity inverted.
[0034]
When the polarity control signal POL is switched to “L”, the operational amplifier 78₁Becomes an inverting amplifier circuit and an operational amplifier 78₂Becomes a non-inverting amplifier. As a result, the luminance signal B1 is inverted and output as a negative drive voltage DV1, and the luminance signal B2 is output as it is as a positive drive voltage DV2.
As described above, the output buffer 70B of the second embodiment has an operational amplifier 78 configured to be inverted / non-inverted by the polarity control signal POL._ihave. Thereby, in addition to the same advantages as those of the first embodiment, the amplifier circuit can be unified into one type, so that there is an advantage that the circuit can be further simplified.
[0035]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of this modification include the following (a) to (c).
(A) The number of bits of the luminance data Di is not limited to 6 bits, and can be similarly applied to any number of bits. In this case, the reference voltage in the DA converter 60A needs to be a number corresponding to this.
(B) Although the display color is not mentioned for simplification of description, when color display is performed, for example, three continuous luminance data D3i-2, D3i-1, and D3i are converted into red ( It is only necessary to correspond to the three primary colors R), green (G), and blue (B).
(C) In the output buffers 70A and 70B, the drive voltages DVi and DVi + 1 are generated by inverting the polarities of the adjacent luminance signals Bi and Bi + 1. For example, when used for color display, the output buffers 70A and 70B are continuous. The polarity may be inverted in units of three luminance signals B3i-2, B3i-1, and B3i.
[0036]
【The invention's effect】
  As explained in detail above, according to the first invention,The display driving means is composed of a non-inverting amplifier and an inverting amplifier for every two adjacent display electrodes, and first and second switch sections for switching the connection between the input side and the output side of these non-inverting amplifier and inverting amplifier. is doing. As a result, there is no need to generate positive and negative reference voltages, and the circuit scale can be simplified.
[0037]
  According to the second invention,Since the display driving means is composed of an operational amplifier that can be switched to a non-inverting amplifier or an inverting amplifier by a polarity control signal, the amplifier circuit can be unified into one type, and the circuit can be further simplified. effective.
  ThirdAccording to the eighth aspect of the present invention, the switch unit that selectively outputs the input first or second luminance signal, and the first or second luminance signal selected by the switch unit is amplified to be the first Alternatively, since the display drive unit having the amplification unit that generates the second drive voltage is provided, there is no need to provide an amplification unit for each luminance signal, and the circuit scale of the display drive unit can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an LCD drive circuit showing a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a conventional LCD driving circuit.
FIG. 3 is a configuration diagram showing details of an output buffer 70A in FIG. 1;
FIG. 4 is a configuration diagram of an output buffer showing a second embodiment of the present invention.
[Explanation of symbols]
10 LCD (Liquid Crystal Display)
11_i    X electrode
12_j    Y electrode
13_{i, j}    MOS (Insulated Gate Field Effect Transistor)
14_{i, j}    Liquid crystal display element
15 Reference electrode
20 Scanning circuit
30 Shift register
40 Data register
50 Data latch
60A DA converter
61 Reference voltage generator
63_i    decoder
70A, 70B output buffer
71_i74_i    Switch part
72_i    Non-inverting amplifier
73_i    Inverting amplifier

Claims (2)

A first display electrode; a second display electrode disposed adjacent to the first display electrode; a plurality of scan electrodes disposed orthogonal to the first and second display electrodes; A first or second driving voltage applied to the first and second display electrodes of a liquid crystal display including a liquid crystal display element provided at an intersection of the first and second display electrodes and the plurality of scanning electrodes. A liquid crystal display driving circuit for applying
A D / A converter for generating first and second luminance signals according to a potential level selected based on luminance data;
It said first and enter the second luminance signal, and a display driving unit which outputs the first and second drive voltages,
The display driver is
A first input terminal for inputting the first luminance signal; a second input terminal for inputting the second luminance signal; and a first output terminal and a second output terminal. A terminal and the first output terminal are electrically connected and the second input terminal and the second output terminal are electrically connected; or the first input terminal and the second output A first switch electrically connecting a terminal and electrically connecting the second input terminal and the first output terminal;
A first amplifying unit connected to the first output terminal of the first switch and amplifying and outputting an input signal;
A second amplifying unit connected to the second output terminal of the first switch and inverting and amplifying the input signal;
A third input terminal connected to the first amplifying unit; a fourth input terminal connected to the second amplifying unit; a third output terminal outputting the first drive voltage; And a fourth output terminal for outputting the second drive voltage, electrically connecting the third input terminal and the third output terminal, and the fourth input terminal and the fourth output. A terminal is electrically connected, or the third input terminal is electrically connected to the fourth output terminal, and the fourth input terminal is electrically connected to the third output terminal. A liquid crystal display driving circuit comprising a second switch that The D / A converter in accordance with the 6-bit luminance data, the liquid crystal display of claim 1, wherein generating the luminance signal by selecting from the level of the potential of 64 generated by the resistive element Unit drive circuit.

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