JP3876259B2 - Manufacturing method of ceramic substrate - Google Patents

Manufacturing method of ceramic substrate Download PDF

Info

Publication number
JP3876259B2
JP3876259B2 JP2004227995A JP2004227995A JP3876259B2 JP 3876259 B2 JP3876259 B2 JP 3876259B2 JP 2004227995 A JP2004227995 A JP 2004227995A JP 2004227995 A JP2004227995 A JP 2004227995A JP 3876259 B2 JP3876259 B2 JP 3876259B2
Authority
JP
Japan
Prior art keywords
substrate
cavity
break
open
separation line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004227995A
Other languages
Japanese (ja)
Other versions
JP2006049551A (en
Inventor
順一 鷲野
信治 前原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Spark Plug Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2004227995A priority Critical patent/JP3876259B2/en
Publication of JP2006049551A publication Critical patent/JP2006049551A/en
Application granted granted Critical
Publication of JP3876259B2 publication Critical patent/JP3876259B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/0919Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10068Non-printed resonator
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10106Light emitting diode [LED]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

本発明は、セラミック基板の製造方法に関する。   The present invention relates to a method for manufacturing a ceramic substrate.

従来から、SAWフィルタ、トランジスタ、LSI、水晶振動子、発光ダイオード等の電子部品を搭載するためのキャビティを備え、これらの電子部品を他の基板等と電気的に接続するためのセラミック基板が知られている。このようなセラミック基板の一例を、図11に示す。図11のセラミック基板100は、セラミックからなる基板本体が第一主表面CP1、第二主表面CP2、側面SFを有する四辺形板状をなし、第一主表面CP1にキャビティ101が形成され、キャビティの底面102には電子部品(図示しない)が実装される。そして側面SFには半円筒形の凹部104が設けられ、その内周面に形成されたメタライズ層103が、内部導体層(図示しない)を介してキャビティ底面CP2に実装された電子部品と電気的に接続している。   Conventionally, a ceramic substrate has been known which has a cavity for mounting electronic components such as SAW filters, transistors, LSIs, crystal resonators, and light emitting diodes and electrically connects these electronic components to other substrates. It has been. An example of such a ceramic substrate is shown in FIG. The ceramic substrate 100 of FIG. 11 has a quadrilateral plate shape in which a substrate body made of ceramic has a first main surface CP1, a second main surface CP2, and a side surface SF, and a cavity 101 is formed on the first main surface CP1. An electronic component (not shown) is mounted on the bottom surface 102 of. The side surface SF is provided with a semi-cylindrical recess 104, and the metallized layer 103 formed on the inner peripheral surface thereof is electrically connected to the electronic component mounted on the cavity bottom surface CP2 via an internal conductor layer (not shown). Connected to.

セラミック基板100の製造には、例えばグリーンシート積層法が用いられる。これにはまず、基板本体をなす数枚のセラミックグリーンシートを用意して、所定の場所にキャビティ101や凹部104となる貫通孔を、打ち抜き金具などを使って形成する。その後、グリーンシート表面や凹部104にMoやWなどの金属を含むメタライズペーストを印刷塗布して、グリーンシートを積層し、圧着する。そしてグリーンシートをメタライズペーストとともに高温焼成することで、積層されたグリーンシートが一体化した焼結体を得るとともに、メタライズ層103や内部導通層が形成される。   For manufacturing the ceramic substrate 100, for example, a green sheet lamination method is used. For this, first, several ceramic green sheets forming the substrate body are prepared, and through holes to be formed into the cavities 101 and the recesses 104 are formed at predetermined locations using a punched metal fitting or the like. Thereafter, a metallized paste containing a metal such as Mo or W is printed on the surface of the green sheet or the recess 104, and the green sheets are stacked and pressure bonded. Then, the green sheet is fired at a high temperature together with the metallized paste to obtain a sintered body in which the laminated green sheets are integrated, and the metallized layer 103 and the internal conductive layer are formed.

これらの工程は、セラミックグリーンシートに大判を用いて、一度に多数のセラミック基板100が取得できるようにされる。その一例を図12の(a)表面図及び(b)断面図に示す。図12においては、複数のセラミック基板100が面内方向に一体化した集合基板106が形成されている。焼成前に分離予定線lに沿ってブレーク溝b1,b2を入れて、焼成後に個々の基板単位を分離する(いわゆるチョコレートブレーク)ことによって、一度に多数のセラミック基板100が製造可能となる。図12(b)に示すようにブレーク溝を形成する工程では、第一主表面CP1側および第二主表面CP2側からブレーク刃105を入れることで、個々のセラミック基板100を分離するのに十分な深さとすることができる。なお、下記特許文献1及び特許文献2には、このようなブレーク溝の形成と、その応用について開示がされている。
特開2000−63414号公報 特開2000−252379号公報
In these steps, a large number of ceramic green sheets are used so that a large number of ceramic substrates 100 can be obtained at a time. An example thereof is shown in FIG. 12 (a) surface view and (b) sectional view. In FIG. 12, a collective substrate 106 in which a plurality of ceramic substrates 100 are integrated in the in-plane direction is formed. By placing break grooves b1 and b2 along the planned separation line l before firing and separating individual substrate units after firing (so-called chocolate break), a large number of ceramic substrates 100 can be manufactured at one time. In the step of forming the break groove as shown in FIG. 12B, the break blades 105 are inserted from the first main surface CP1 side and the second main surface CP2 side, which is sufficient to separate the individual ceramic substrates 100. Depth. The following Patent Document 1 and Patent Document 2 disclose the formation of such a break groove and its application.
JP 2000-63414 A JP 2000-252379 A

一方、図1のような形態のセラミック基板が望まれる場合もある。図1(a)では、壁部が一辺部において非形成とされることにより側方が開放した開放キャビティ2がセラミック基板1に形成されている。そして開放キャビティの底面4に電子部品の実装部や配線、接続端子(図示しない)を形成するのである。図1(b)のように側面に凹部22を設け、その内周面にメタライズ層5を形成して他の基板との接続端子とするセラミック基板もある。   On the other hand, a ceramic substrate having a form as shown in FIG. 1 may be desired. In FIG. 1A, an open cavity 2 that is open on the side is formed in the ceramic substrate 1 because the wall is not formed on one side. Then, a mounting portion of electronic parts, wiring, and connection terminals (not shown) are formed on the bottom surface 4 of the open cavity. As shown in FIG. 1B, there is a ceramic substrate in which a concave portion 22 is provided on a side surface and a metallized layer 5 is formed on an inner peripheral surface thereof to be a connection terminal with another substrate.

ところが上記形状のセラミック基板1を図12のように大判を用いて製造しようとすると、開放キャビティ2の底部にブレーク刃が届きにくいため十分な深さのブレーク溝を形成することができず(図13参照)、その結果、セラミック基板1を互いに分離したときにバリが生じる問題があった。   However, if the ceramic substrate 1 having the above shape is manufactured using a large size as shown in FIG. 12, a break groove having a sufficient depth cannot be formed because it is difficult for the break blade to reach the bottom of the open cavity 2 (see FIG. 12). 13), as a result, there is a problem that burrs are generated when the ceramic substrates 1 are separated from each other.

本発明は、上述のような事情を背景になされたものであって、特に、壁部が一辺部において非形成とされることにより側方が開放した開放キャビティを有するセラミック基板の製造方法で、一度に多数、製造でき、バリを生じにくいセラミック基板の製造方法を提供することを課題とする。   The present invention is made in the background as described above, and in particular, a method of manufacturing a ceramic substrate having an open cavity whose side is opened by the wall being not formed on one side, It is an object of the present invention to provide a method for manufacturing a ceramic substrate that can be manufactured in large numbers at a time and hardly generate burrs.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

上記課題を解決するために本発明のセラミック基板の製造方法は、四辺形板状の基板本体と、該基板本体を底部とするキャビティを形成するために、基板本体の第一主表面においてキャビティ底面となる領域を取り囲むように該第一主表面から突設される壁部とを有する基板単位を、当該基板単位を分離するための分離予定線により仕切られる形にて面内方向に複数一体化した集合基板を製造し、該集合基板を分離予定線に沿って切断することにより、個々の基板単位に分離する工程を有し、基板単位は、基板本体の一辺部において壁部が非形成となることにより、キャビティが、当該辺部にて側方に開放した開放キャビティとされてなり、集合基板において、分離予定線を挟んで隣接する2個の基板単位の開放キャビティが、開放側を該分離予定線側に一致させることにより、壁部とともに一体化して連結キャビティを形成するとともに、その連結位置において連結キャビティを挟んで対向する一対の壁部の第一主表面に、分離予定線に沿って第一のブレーク溝を形成し、基板本体の第二主表面側においては第一のブレーク溝に対応する位置に第二のブレーク溝を形成し、基板本体の連結キャビティの形成領域には、一対の壁部にそれぞれ形成された第一のブレーク溝をつなぐ位置に、分離予定線に沿ったブレーク貫通孔を形成し、それら第一のブレーク溝、第二のブレーク溝及びブレーク貫通孔にて基板単位を互いに分離することを主要な特徴とする。   In order to solve the above-described problems, a method for manufacturing a ceramic substrate according to the present invention includes a quadrilateral plate-like substrate body and a cavity bottom surface on a first main surface of the substrate body to form a cavity having the substrate body as a bottom. A plurality of substrate units having a wall portion protruding from the first main surface so as to surround the region to be formed are integrated in the in-plane direction so as to be partitioned by a predetermined separation line for separating the substrate units. Manufacturing the assembled substrate, and cutting the aggregate substrate along the planned separation line to separate each substrate unit, and the substrate unit has a wall portion not formed on one side of the substrate body. Thus, the cavity is formed as an open cavity opened laterally at the side, and in the collective substrate, the open cavities of two substrate units adjacent to each other with the planned separation line sandwich the open side. Min By aligning with the planned line side, it is integrated with the wall part to form a connection cavity, and at the connection position, on the first main surface of the pair of wall parts facing each other across the connection cavity, along the planned separation line A first break groove is formed, a second break groove is formed at a position corresponding to the first break groove on the second main surface side of the substrate body, and a pair of cavities are formed in a region where the connection cavity of the substrate body is formed. Break through-holes along the planned separation line are formed at positions where the first break grooves formed on the walls of the substrate are connected, and the first break groove, the second break groove, and the break through-hole form a substrate. The main feature is that the units are separated from each other.

本発明は、開放キャビティを有するセラミック基板の集合基板を製造し、2つの基板単位が、開放した側を分離予定線に一致させるように上記集合基板を形成しておく。この集合基板においては、開放キャビティの壁部は一体化して連結キャビティをなす。そして連結位置において、連結キャビティを挟んで対向する2つの壁部に、両方の主表面からブレーク溝を形成する。連結キャビティの底面には分離予定線に沿ってブレーク貫通孔を形成して、ブレーク溝及びブレーク貫通孔にてセラミック基板を互いに分離する。このようにすると、開放キャビティの壁部においては第一主表面及び第二主表面からブレーク刃を所望の深さまで入れることができるとともに、ブレーク刃を入れにくいキャビティ底部においてはブレーク貫通孔が形成されているので、セラミック基板を分離するときにバリが生じない。   In the present invention, a collective substrate of ceramic substrates having an open cavity is manufactured, and the collective substrate is formed so that two substrate units have the open side coincident with the planned separation line. In this collective substrate, the walls of the open cavities are integrated to form a connection cavity. And in a connection position, a break groove | channel is formed from both main surfaces in two wall parts which oppose on both sides of a connection cavity. Break through holes are formed along the planned separation line on the bottom surface of the connection cavity, and the ceramic substrates are separated from each other by the break grooves and the break through holes. In this way, the break blade can be inserted from the first main surface and the second main surface to a desired depth in the wall portion of the open cavity, and a break through hole is formed in the cavity bottom portion where it is difficult to insert the break blade. Therefore, no burrs are generated when the ceramic substrate is separated.

上述の開放キャビティを複数有する基板単位も製造可能である。例えば四辺形板状の基板本体の、対向する2つの辺に開放キャビティを別々に形成することができる。この場合、集合基板においては両隣のセラミック基板と開放キャビティを共有させるのである。   A substrate unit having a plurality of the above-described open cavities can also be manufactured. For example, open cavities can be separately formed on two opposing sides of a quadrilateral plate-like substrate body. In this case, the collective substrate shares the open cavity with the adjacent ceramic substrates.

さらに本発明は、上記の開放キャビティとは別の電子部品実装用キャビティを、基板本体の第一主表面においてキャビティ底面をなすように形成し、その電子部品実装用キャビティのキャビティ底面に電子部品の実装部を形成することもできる。   Further, according to the present invention, an electronic component mounting cavity different from the above open cavity is formed so as to form a cavity bottom surface on the first main surface of the substrate body, and the electronic component mounting cavity is formed on the cavity bottom surface of the electronic component mounting cavity. A mounting part can also be formed.

さらに本発明は、前記四辺形板状の基板本体の対向する2つの辺に前記開放キャビティをそれぞれ形成し、これら2つの開放キャビティとは別の発光素子実装用キャビティをさらに形成するとともに、前記発光素子実装用キャビティの前記キャビティ底面に発光素子の実装部を形成し、該発光素子を取り囲む経路に沿ってフィレット部を形成して、該フィレット部の表面において前記発光素子からの発光光束を所定の方向に反射させるようにする。   In the present invention, the open cavities are respectively formed on two opposing sides of the quadrilateral plate-like substrate body, a light emitting element mounting cavity different from the two open cavities is further formed, and the light emission A light emitting element mounting portion is formed on the cavity bottom surface of the element mounting cavity, a fillet portion is formed along a path surrounding the light emitting element, and a light beam emitted from the light emitting element is transmitted to the surface of the fillet portion by a predetermined amount. Reflect in the direction.

また、本発明は、上記の発光素子実装用キャビティの内周面と、キャビティ底面の外周縁部に金属層を形成して、これら2つの金属層にまたがるようにフィレット部を形成する。このフィレット部は、例えばAg系ロウ材を用いて形成することができる。   In the present invention, a metal layer is formed on the inner peripheral surface of the light emitting element mounting cavity and the outer peripheral edge of the bottom surface of the cavity, and the fillet portion is formed so as to straddle these two metal layers. This fillet portion can be formed using, for example, an Ag-based brazing material.

以下、本発明の実施の形態を、図面を用いて説明する。
図2に集合基板の(a)表面図、(b)断面図、そして図3に斜視図を示す。これらの図に示すように、セラミック基板の基板単位を複数一体化した集合基板6を先ず形成し、分離予定線l,l’に沿って切断して、個々の基板単位を得る。基板単位は四辺形状で、キャビティ底面4を取り囲むように壁部Wが突設される。本発明の集合基板においては2個の基板単位を連結して、開放キャビティ2の開放側を分離予定線に一致させており、開放キャビティ2が壁部Wとともに一体化して連結キャビティ9を形成している。集合基板6にブレーク溝を形成するには、図2(b)に示すように、分離予定線l,l’に沿って第一主表面CP1からブレーク刃8を入れて第一ブレーク溝b1を形成するとともに、第二主表面CP2からもブレーク刃8を入れて第二ブレーク溝b2を形成する。また、連結キャビティ9の形成領域には、分離予定線l’に沿ってブレーク貫通孔7を形成しておく。このようにすると、ブレーク貫通孔7において2個の基板単位が容易に分離できるので、分割工程でバリが生じにくくなる。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
2A is a front view, FIG. 2B is a cross-sectional view, and FIG. 3 is a perspective view. As shown in these drawings, an aggregate substrate 6 in which a plurality of substrate units of ceramic substrates are integrated is first formed and cut along the predetermined separation lines l and l ′ to obtain individual substrate units. The substrate unit is a quadrilateral shape, and a wall portion W is provided so as to surround the cavity bottom surface 4. In the collective substrate of the present invention, two substrate units are connected so that the open side of the open cavity 2 coincides with the planned separation line, and the open cavity 2 is integrated with the wall portion W to form a connecting cavity 9. ing. In order to form a break groove in the collective substrate 6, as shown in FIG. 2B, the break blade 8 is inserted from the first main surface CP1 along the planned separation lines l and l ′ to form the first break groove b1. At the same time, the break blade 8 is inserted from the second main surface CP2 to form the second break groove b2. Further, a break through hole 7 is formed in the formation region of the connection cavity 9 along the planned separation line l ′. In this way, since two substrate units can be easily separated in the break through hole 7, burrs are hardly generated in the dividing step.

壁部Wの高さをh1、キャビティ底部の厚さをh2とすると、第一ブレーク溝の深さd1はh1の50〜60%とし、第二ブレーク溝の深さd2はh2の50〜60%とすることが望ましい。50%未満になるとブレークしにくくなり、60%を超えるとブレーク刃が内部導通層(図示しない)を損傷する場合がある。   When the height of the wall W is h1 and the thickness of the cavity bottom is h2, the first break groove depth d1 is 50-60% of h1, and the second break groove depth d2 is 50-60 of h2. % Is desirable. If it is less than 50%, it becomes difficult to break, and if it exceeds 60%, the break blade may damage the internal conductive layer (not shown).

上述したように集合基板6を製造した後、セラミックグリーンシートを焼結し、分離予定線l,l’に沿って個々の基板単位を分離すると、図4に示すセラミック基板1が多数、製造できる。図4のセラミック基板1は開放キャビティ2を有する。開放キャビティ2は集合基板6における連結キャビティ9を分割して形成するものである。   After the assembly substrate 6 is manufactured as described above, the ceramic green sheets are sintered and the individual substrate units are separated along the planned separation lines l and l ′, so that many ceramic substrates 1 shown in FIG. 4 can be manufactured. . The ceramic substrate 1 of FIG. 4 has an open cavity 2. The open cavity 2 is formed by dividing the connecting cavity 9 in the collective substrate 6.

以上説明したように本発明では集合基板6において、分離予定線l’に沿ったブレーク貫通孔7を形成するので、個々の基板単位を分離する工程でバリが生じにくい。ここで仮に図13に示すように、ブレーク貫通孔7を形成しておかなかったら、連結キャビティの底部4には第一主表面CP1からのブレーク刃8が届かないので、必ずしも十分な深さのブレーク溝b2’を形成することができない。その結果、基板単位を分割する工程で、ブレーク溝b2’においてバリが発生する場合がある。また、ブレーク溝b2’の深さd3を十分に深くしようとすると、第二主表面CP2側から入れるブレーク刃8の圧力が高くなり、その結果、壁部Wにおけるブレーク溝b2の深さが必要以上に深くなってしまう問題が生じる。   As described above, in the present invention, the break through hole 7 is formed in the collective substrate 6 along the planned separation line l ', so that burrs are hardly generated in the process of separating individual substrate units. Here, as shown in FIG. 13, if the break through hole 7 is not formed, the break blade 8 from the first main surface CP1 does not reach the bottom 4 of the connection cavity, so that the depth is not necessarily sufficient. Break groove b2 'cannot be formed. As a result, burrs may occur in the break groove b2 'in the process of dividing the substrate unit. Further, if the depth d3 of the break groove b2 ′ is made sufficiently deep, the pressure of the break blade 8 inserted from the second main surface CP2 side increases, and as a result, the depth of the break groove b2 in the wall W is necessary. The problem which becomes deeper than that arises.

一方、図5(a)に示すように、開放キャビティ2以外に電子部品実装用キャビティ10を形成することも可能である。この電子部品実装用キャビティ10にはSAWフィルタ、トランジスタ、LSI、水晶振動子、発光ダイオード等の電子部品の実装部(図示しない)を形成するとともに、実装部と接続する導通層を開放キャビティ2へ引出して、他の基板との接続部分を形成するのである。また、図5(b)に示すように、側面に凹部22を形成し、その内周面に内部導通層と電気的に接続したメタライズ層5を形成して、このメタライズ層5を他の基板との接続部分としてもよい。   On the other hand, as shown in FIG. 5A, it is possible to form an electronic component mounting cavity 10 in addition to the open cavity 2. A mounting part (not shown) for electronic parts such as SAW filters, transistors, LSIs, crystal resonators, and light emitting diodes is formed in the electronic part mounting cavity 10, and a conductive layer connected to the mounting part is connected to the open cavity 2. It is pulled out to form a connection portion with another substrate. Further, as shown in FIG. 5B, a recess 22 is formed on the side surface, a metallized layer 5 electrically connected to the internal conductive layer is formed on the inner peripheral surface thereof, and this metallized layer 5 is attached to another substrate. It is good also as a connection part.

さらに、図6の(a)断面図(b)斜視図に示すように、四辺形状のセラミック基板1の対向する2つの辺にそれぞれ開放キャビティ2を形成するとともに、これら開放キャビティ2とは別の電子部品実装用キャビティ10を形成することも可能である。図6の実施形態では電子部品実装用キャビティ10に、発光ダイオードなどの発光素子13を実装している。具体的には、電子部品実装キャビティ10の底面19に実装部14が形成され、ここに発光素子13が実装される。図6では赤、青、緑の3種類の発光素子を搭載して、白色光を取り出す形態としている。一方、キャビティの内周面20と底面19にそれぞれ金属層12a,12bを形成し、これら2つの金属層12a,12bにまたがるようにAg系ロウ材のフィレット部15が形成されている。フィレット部15の表面は、発光素子13からの発光光束を外部へ反射するための光反射面16とされている。このようなフィレット部15は後述するように、Ag系ロウ材の粒子を金属層12b上に載置して、高温処理を施してリフローさせることにより形成する。リフローによってフィレット部15の表面は滑らかになるので、光反射面16は光反射率が高いものとなる。また、金属層12a,12bはともにメタライズペーストを印刷塗布することにより形成でき、加工精度が高ので、この2つの金属層12a,12bにまたがって形成されるフィレット部15の加工精度も高いものとなり、光の反射角度などのバラツキを低く抑えることが可能となる。   Further, as shown in the perspective view of FIG. 6A, the open cavities 2 are formed on the two opposing sides of the quadrilateral ceramic substrate 1, and different from these open cavities 2. It is also possible to form the electronic component mounting cavity 10. In the embodiment of FIG. 6, a light emitting element 13 such as a light emitting diode is mounted in the electronic component mounting cavity 10. Specifically, the mounting portion 14 is formed on the bottom surface 19 of the electronic component mounting cavity 10, and the light emitting element 13 is mounted thereon. In FIG. 6, three types of light emitting elements of red, blue, and green are mounted to extract white light. On the other hand, metal layers 12a and 12b are formed on the inner peripheral surface 20 and the bottom surface 19 of the cavity, respectively, and an Ag-based filler material 15 is formed so as to straddle the two metal layers 12a and 12b. The surface of the fillet portion 15 is a light reflecting surface 16 for reflecting the emitted light beam from the light emitting element 13 to the outside. As will be described later, the fillet portion 15 is formed by placing Ag-based brazing particles on the metal layer 12b, performing high temperature treatment, and reflowing. Since the surface of the fillet portion 15 is smoothed by the reflow, the light reflecting surface 16 has a high light reflectance. Further, both the metal layers 12a and 12b can be formed by printing and applying metallized paste, and the processing accuracy is high. Therefore, the processing accuracy of the fillet portion 15 formed over the two metal layers 12a and 12b is also high. Thus, it is possible to suppress variations such as the light reflection angle.

図6の基板本体は3枚のセラミック層11a,11b,11cを積層して形成される。セラミック層11aの表面には金属層12aが形成され、セラミック層11bにはパッド17および金属層12aが形成されている。そしてパッド17と発光素子13とはワイヤ18によって電気的接続がなされている。さらにパッド17はセラミック基板11bを貫通する導通層21を介して金属層12bと電気的に接続されている。また、金属層12bは一部が開放キャビティ2から露出しており、この露出した部分は他の基板との接続部CNとして使用される。   The substrate body of FIG. 6 is formed by laminating three ceramic layers 11a, 11b, and 11c. A metal layer 12a is formed on the surface of the ceramic layer 11a, and a pad 17 and a metal layer 12a are formed on the ceramic layer 11b. The pad 17 and the light emitting element 13 are electrically connected by a wire 18. Further, the pad 17 is electrically connected to the metal layer 12b through a conductive layer 21 penetrating the ceramic substrate 11b. A part of the metal layer 12b is exposed from the open cavity 2, and this exposed part is used as a connection part CN with another substrate.

次に、図6に示したセラミック基板1の製造方法を、図7〜図10の工程図を用いて説明する。まず、セラミックグリーンシート11a’〜11c’を用意する(工程1)。その後、工程2に示すように、所定の位置に連結キャビティ9、発光素子実装用キャビティ10、ブレーク貫通孔7、導通層21となるべき貫通穴を、打ち抜き形成する。次に、メタライズペースト14’、12a’、12b’、17’、21’を、所定の位置に印刷塗布する(工程3)。メタライズペーストの印刷には、例えばスクリーン印刷法が採用される。その後、セラミックグリーンシート11a’〜11c’を積層、圧着し、メタライズペーストとともに高温で焼成することによって、セラミックグリーンシートが一体化した集合基板6を得る(工程4)。焼成した結果、メタライズペースト14’、12a’、12b’、17’、21’は実装部14、金属層12a,12b、導通層21、パッド17となる。このようにした後で、発光素子実装用キャビティ10の内周面20に形成された金属層12aと、底面19の外周縁部に形成された金属層12bとにまたがるようにフィレット部を形成する。そのためにまず工程5に示すように、Ag系ロウ材の粒子15’を金属層12b上に載置する。そしてこの粒子15’を集合基板6ごと高温加熱して、Agロウ材をリフローさせ、フィレット部15を形成する。このように形成されたフィレット部15の表面は滑らかで光反射率が高く、光反射面として好適に用いられる。   Next, a method for manufacturing the ceramic substrate 1 shown in FIG. 6 will be described with reference to the process diagrams of FIGS. First, ceramic green sheets 11a 'to 11c' are prepared (step 1). Thereafter, as shown in Step 2, the connecting cavity 9, the light emitting element mounting cavity 10, the break through hole 7, and the through hole to be the conductive layer 21 are punched and formed at predetermined positions. Next, the metallized pastes 14 ′, 12 a ′, 12 b ′, 17 ′, and 21 ′ are printed and applied to predetermined positions (Step 3). For printing the metallized paste, for example, a screen printing method is employed. Thereafter, the ceramic green sheets 11a 'to 11c' are laminated and pressure-bonded, and fired at a high temperature together with the metallized paste to obtain an aggregate substrate 6 in which the ceramic green sheets are integrated (step 4). As a result of baking, the metallized pastes 14 ′, 12 a ′, 12 b ′, 17 ′, and 21 ′ become the mounting portion 14, the metal layers 12 a and 12 b, the conductive layer 21, and the pad 17. After this, a fillet portion is formed so as to straddle the metal layer 12 a formed on the inner peripheral surface 20 of the light emitting element mounting cavity 10 and the metal layer 12 b formed on the outer peripheral edge portion of the bottom surface 19. . For this purpose, first, as shown in step 5, Ag-based brazing filler metal particles 15 'are placed on the metal layer 12b. Then, the particles 15 ′ are heated together with the aggregate substrate 6 at a high temperature to reflow the Ag brazing material, thereby forming the fillet portion 15. The surface of the fillet portion 15 formed in this way is smooth and has a high light reflectance, and is suitably used as a light reflecting surface.

次に、以上のように製造した集合基板6を個々の基板単位に分離するために、図10に示すブレーク溝b1,b2を形成する。まず、分離予定線l’に沿って、連結キャビティ9を挟む一対の壁部Wに、第一主表面CP1から第一のブレーク溝b1を形成する(図10では縦方向のブレーク溝b1)。また、横方向にも第一のブレーク溝b1を形成する。さらに、第一のブレーク溝b1に対応する位置に、第二主表面CP2から第二のブレーク溝b2を入れる。一方、連結キャビティの形成領域には、壁部Wに形成された第一のブレーク溝b1をつなぐ位置に、ブレーク貫通孔7が予め形成されている。これら第一のブレーク溝b1、第二のブレーク溝b2、ブレーク貫通孔7を使って各基板単位を分離することが可能となる。   Next, in order to separate the collective substrate 6 manufactured as described above into individual substrate units, break grooves b1 and b2 shown in FIG. 10 are formed. First, the first break groove b1 is formed from the first main surface CP1 along the planned separation line l 'in the pair of wall portions W sandwiching the connecting cavity 9 (the vertical break groove b1 in FIG. 10). The first break groove b1 is also formed in the lateral direction. Further, the second break groove b2 is inserted from the second main surface CP2 at a position corresponding to the first break groove b1. On the other hand, a break through hole 7 is formed in advance at a position where the first break groove b <b> 1 formed in the wall portion W is connected to the connection cavity forming region. Each of the substrate units can be separated by using the first break groove b1, the second break groove b2, and the break through hole 7.

以上説明したように本発明ではブレーク貫通孔7を打ち抜き形成しておくので、焼成後に各基板単位を分離する工程において、キャビティ底面にバリを生じることなく分離することができる。   As described above, in the present invention, since the break through hole 7 is formed by punching, in the step of separating each substrate unit after firing, it can be separated without causing burrs on the bottom surface of the cavity.

セラミック基板の一例Example of ceramic substrate セラミック基板の製造方法の一実施形態を示す(a)表面図および(b)断面図。The (a) surface view and (b) sectional drawing which show one Embodiment of the manufacturing method of a ceramic substrate. 同じく斜視図。Similarly perspective view. 本発明に係るセラミック基板の基板単位を示す一実施形態。An embodiment which shows a substrate unit of a ceramic substrate concerning the present invention. 図4とは別の実施形態。Embodiment different from FIG. 発光素子を搭載したセラミック基板の一実施形態。One embodiment of the ceramic substrate carrying a light emitting element. 図6のセラミック基板を製造する方法の一例。An example of the method of manufacturing the ceramic substrate of FIG. 図7に続く図。The figure following FIG. 図8に続く図。The figure following FIG. 図9に続く図。The figure following FIG. 従来のセラミック基板。Conventional ceramic substrate. 従来の集合基板の(a)表面図および(b)断面図。(A) Surface view and (b) Cross-sectional view of a conventional aggregate substrate. 仮にキャビティ底部にブレーク溝を形成しなかった場合の(a)表面図および(b)断面図。(A) surface view and (b) cross-sectional view when a break groove is not formed at the bottom of the cavity.

符号の説明Explanation of symbols

1 セラミック基板
2 開放キャビティ
3 開放辺部
4 キャビティ底面
6 集合基板
7 ブレーク貫通孔
8 ブレーク刃
9 連結キャビティ
10 電子部品実装用キャビティ
13 発光素子
15 フィレット部
16 光反射面
22 凹部
CP1 第一主表面
W 壁部
l 分離予定線
l’2個の基板単位の開放側が一致した分離予定線
b1 第一のブレーク溝
DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Open cavity 3 Open side part 4 Cavity bottom face 6 Collective board 7 Break through-hole 8 Break blade 9 Connection cavity 10 Electronic component mounting cavity 13 Light emitting element 15 Fillet part 16 Light reflecting surface 22 Recessed part CP1 First main surface W Wall 1 l Planned separation line l ′ Planned separation line b1 in which the open sides of the two substrate units coincide with each other First break groove

Claims (4)

四辺形板状の基板本体と、該基板本体を底部とするキャビティを形成するために、前記基板本体の第一主表面においてキャビティ底面となる領域を取り囲むように該第一主表面から突設される壁部とを有する基板単位を、当該基板単位を分離するための分離予定線により仕切られる形にて面内方向に複数一体化した集合基板を製造し、該集合基板を前記分離予定線に沿って切断することにより、個々の基板単位に分離する工程を有し、
前記基板単位は、前記基板本体の一辺部において前記壁部が非形成となることにより、前記キャビティが、当該辺部にて側方に開放した開放キャビティとされてなり、前記集合基板において、前記分離予定線を挟んで隣接する2個の基板単位の前記開放キャビティが、開放側を該分離予定線側に一致させることにより、前記壁部とともに一体化して連結キャビティを形成するとともに、その連結位置において前記連結キャビティを挟んで対向する一対の前記壁部の第一主表面に、前記分離予定線に沿って第一のブレーク溝を形成し、前記基板本体の第二主表面側においては前記第一のブレーク溝に対応する位置に第二のブレーク溝を形成し、前記基板本体の前記連結キャビティの形成領域には、前記一対の壁部にそれぞれ形成された前記第一のブレーク溝をつなぐ位置に、前記分離予定線に沿ったブレーク貫通孔を形成し、それら第一のブレーク溝、第二のブレーク溝及びブレーク貫通孔にて前記基板単位を互いに分離することを特徴とするセラミック基板の製造方法。
In order to form a quadrilateral plate-like substrate main body and a cavity having the substrate main body as a bottom, the substrate main body protrudes from the first main surface so as to surround a region serving as a cavity bottom surface on the first main surface. Manufacturing a collective substrate in which a plurality of substrate units having a wall portion are integrated in an in-plane direction in a form partitioned by a planned separation line for separating the substrate unit, and the aggregate substrate is used as the planned separation line A step of separating the substrate into individual substrate units by cutting along
In the substrate unit, the wall portion is not formed on one side portion of the substrate body, whereby the cavity is an open cavity opened laterally at the side portion. The open cavities of the two substrate units adjacent to each other with the planned separation line are integrated with the wall portion so that the open side coincides with the planned separation line side, thereby forming a coupling cavity, and its coupling position. In the first main surface of the pair of wall portions opposed to each other with the connection cavity interposed therebetween, a first break groove is formed along the planned separation line, and the second main surface side of the substrate body is the first main surface. A second break groove is formed at a position corresponding to the one break groove, and the first cavity formed in the pair of wall portions is formed in the connection cavity forming region of the substrate body. A break through hole is formed along the predetermined separation line at a position connecting the break grooves, and the substrate units are separated from each other by the first break groove, the second break groove, and the break through hole. A method for manufacturing a ceramic substrate.
前記開放キャビティの底面に、電子部品の実装部を形成する請求項1記載のセラミック基板の製造方法。 The method for manufacturing a ceramic substrate according to claim 1, wherein a mounting portion for an electronic component is formed on a bottom surface of the open cavity. 前記開放キャビティとは別の電子部品実装用キャビティを、前記基板本体の前記第一主表面においてキャビティ底面をなすように形成し、前記電子部品実装用キャビティの前記キャビティ底面に電子部品の実装部を形成する請求項1または請求項2記載のセラミック基板の製造方法。 An electronic component mounting cavity different from the open cavity is formed so as to form a cavity bottom surface on the first main surface of the substrate body, and an electronic component mounting portion is formed on the cavity bottom surface of the electronic component mounting cavity. The method for producing a ceramic substrate according to claim 1 or 2, wherein the ceramic substrate is formed. 前記四辺形板状の基板本体の対向する2つの辺に前記開放キャビティをそれぞれ形成し、これら2つの開放キャビティとは別の発光素子実装用キャビティをさらに形成するとともに、前記発光素子実装用キャビティの前記キャビティ底面に発光素子の実装部を形成し、該発光素子を取り囲む経路に沿ってフィレット部を形成して、該フィレット部の表面において前記発光素子からの発光光束を所定の方向に反射させるようにした請求項1ないし請求項3のいずれか1項に記載のセラミック基板の製造方法。 The open cavities are respectively formed on two opposing sides of the quadrilateral plate-like substrate body, and a light emitting element mounting cavity different from the two open cavities is further formed, and the light emitting element mounting cavity A mounting part of the light emitting element is formed on the bottom surface of the cavity, a fillet part is formed along a path surrounding the light emitting element, and the emitted light beam from the light emitting element is reflected in a predetermined direction on the surface of the fillet part. The method for manufacturing a ceramic substrate according to any one of claims 1 to 3.
JP2004227995A 2004-08-04 2004-08-04 Manufacturing method of ceramic substrate Expired - Fee Related JP3876259B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004227995A JP3876259B2 (en) 2004-08-04 2004-08-04 Manufacturing method of ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004227995A JP3876259B2 (en) 2004-08-04 2004-08-04 Manufacturing method of ceramic substrate

Publications (2)

Publication Number Publication Date
JP2006049551A JP2006049551A (en) 2006-02-16
JP3876259B2 true JP3876259B2 (en) 2007-01-31

Family

ID=36027771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004227995A Expired - Fee Related JP3876259B2 (en) 2004-08-04 2004-08-04 Manufacturing method of ceramic substrate

Country Status (1)

Country Link
JP (1) JP3876259B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2514576A1 (en) 2011-04-19 2012-10-24 NGK Insulators, Ltd. A method of producing ceramic substrates

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4012936B2 (en) 2004-08-06 2007-11-28 株式会社アライドマテリアル Assembly board
JP4936743B2 (en) * 2006-02-27 2012-05-23 京セラ株式会社 Manufacturing method of ceramic generation form for multiple-taken wiring board, manufacturing method of multiple-taken wiring board, electronic component storage package, and electronic device
KR101469972B1 (en) 2007-10-17 2014-12-05 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
KR101064049B1 (en) 2010-02-18 2011-09-08 엘지이노텍 주식회사 Semiconductor light emitting device and manufacturing method thereof, light emitting device package
JP5511603B2 (en) * 2010-09-16 2014-06-04 京セラ株式会社 Multiple wiring board
US9526167B2 (en) * 2010-11-02 2016-12-20 Kyocera Corporation Many-up wiring substrate, wiring board, and electronic device
JP6767204B2 (en) 2016-08-25 2020-10-14 京セラ株式会社 Boards for mounting electronic components, electronic devices and electronic modules
CN108511431A (en) * 2018-05-21 2018-09-07 佛山市国星光电股份有限公司 A kind of LED display unit group and display panel
CN112235960B (en) * 2020-10-28 2022-05-17 惠州市特创电子科技股份有限公司 Gold immersion circuit board and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2514576A1 (en) 2011-04-19 2012-10-24 NGK Insulators, Ltd. A method of producing ceramic substrates

Also Published As

Publication number Publication date
JP2006049551A (en) 2006-02-16

Similar Documents

Publication Publication Date Title
TWI488548B (en) Ceramic wiring substrate, multi-piece ceramic wiring substrate and method for manufacturing the same
JP3876259B2 (en) Manufacturing method of ceramic substrate
JP2006261308A (en) Package for mounting electronic component, and package assembly substrate
CN114204405A (en) Package for mounting optical element, electronic device, and electronic module
JPWO2012165530A1 (en) Multilayer substrate manufacturing method and multilayer substrate
JPWO2018216801A1 (en) Electronic component mounting board, electronic device and electronic module
JP2004179602A (en) Ceramic multilayered board and manufacturing method therefor
JP6317115B2 (en) Multi-cavity wiring board, wiring board, and manufacturing method of multi-cavity wiring board
JP2016219677A (en) Ceramic package manufacturing method and ceramic package
JP2007251017A (en) Wiring substrate, multipartite wiring substrate, and manufacturing method thereof
JP4817781B2 (en) Manufacturing method of electronic component package
JP2017076698A (en) Wiring board and manufacturing method of the same
JP3855798B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
JP5247415B2 (en) Multi-cavity wiring board, wiring board and electronic device
JP4712065B2 (en) Multi-cavity wiring board, wiring board, and multi-cavity wiring board and method of manufacturing wiring board
JP2006190983A (en) Wiring board for mounting light emitting device
JP2018046266A (en) Multi-piece wiring board and manufacturing method for multi-piece wiring board
JP6838961B2 (en) Wiring board and its manufacturing method
JP3181887B2 (en) Connected ceramic wiring board, method of manufacturing the same, and method of manufacturing ceramic wiring board
JP6140831B2 (en) Light emitting element mounting package and light emitting device
US10448505B2 (en) Wiring board, method for manufacturing wiring board, and method for manufacturing multi-pattern wiring board
JP2007042768A (en) Circuit board assembly
JP2004228100A (en) Members for light emitting device and light emitting device
JP4677383B2 (en) Manufacturing method of ceramic substrate
JP6321477B2 (en) Electronic component storage package, package assembly, and method of manufacturing electronic component storage package

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061016

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061019

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061030

R150 Certificate of patent or registration of utility model

Ref document number: 3876259

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101102

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101102

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111102

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111102

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121102

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121102

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131102

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees