JP3834856B2 - Electronic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the circuit configuration of an electronic circuit, the electronic circuit according to the present invention can suppress an increase in level at a portion where a high impedance state is temporarily or periodically at the stage of its electrical operation. On the road Related.
[0002]
[Prior art]
In general, in an electronic circuit having a transistor circuit formed on a silicon substrate, for example, by planar technology, there may be a part that temporarily or periodically becomes a high impedance state in the process of electrical operation.
[0003]
For example, in a circuit that detects and holds only the peak from the input signal, for example, a portion having high impedance is generated during a period in which a level other than the peak is input.
[0004]
Specifically, the mechanism for generating the high impedance will be described with reference to the output circuit shown in FIG. First, the output circuit amplifies a voltage signal Vin obtained by converting a signal charge accumulated in a linear sensor of the imaging device, for example, a charge-electric signal by a floating diffusion in an imaging device such as a video camera. The main line L1 that is output as the imaging signal Vs from the first output terminal φ1 and the control that is branched from the main line L1 and obtains an appropriate signal output level as the imaging signal Vs can be controlled like so-called auto gain control. And a branch line L2 to which a peak hold circuit 101 is connected.
[0005]
The peak hold circuit 101 performs a signal processing operation of holding and outputting the peak value of the imaging signal Vs read out at a certain time point or a predetermined period, and the peak value held by this circuit is connected to the outside. An electric signal is supplied to the electronic iris control circuit, and the electronic iris control circuit controls the charge accumulation period (exposure period) at the time of the next imaging based on the peak value, so that an appropriate signal output level can be obtained. Is.
[0006]
The output circuit includes a first-stage source follower circuit 102 that amplifies the voltage signal Vin from the linear sensor with a predetermined gain (≈1) and a signal Va output from the first source follower 102. The peak hold circuit 101 that detects and holds the peak level Vm and the source follower circuit 103 that amplifies the minimum peak level signal Vm held by the peak hold circuit 101 with a predetermined gain (≈1) are connected. Has been configured.
[0007]
The first-stage source follower circuit 102 is configured by connecting a driving transistor Tr1 and a load transistor Tr2 made of an N-MOS transistor in series between a power supply line Lp (power supply voltage Vdd) and the ground, and a gate electrode of the driving transistor Tr1. Are connected so as to be supplied with the voltage signal Vin from the linear sensor. The output Va of the source follower circuit 102 is taken out from a common contact point a of both transistors Tr1 and Tr2.
[0008]
The peak hold circuit 101 is connected to the output line of the source follower circuit 102 in the first stage, a diode D by a P-MOS transistor connected in the reverse direction to the signal output direction, and the anode of the diode D and the ground. And a capacitor C.
[0009]
The source follower circuit 103 in the latter stage is configured by connecting a driving transistor Tr3 and a load transistor Tr4 made of an N-MOS transistor in series between a power supply line Lp (power supply voltage Vdd) and the ground, and the gate electrode of the driving transistor Tr3 The wiring is connected so that the anode potential of the diode D is supplied. The output Vout of the source follower circuit 103 is extracted from the common contact b of both transistors Tr3 and Tr4.
[0010]
The gate electrodes of the load transistors Tr2 and Tr4 in the first-stage source follower circuit 102 and the subsequent-stage source follower circuit 103 are connected so as to be supplied with a gate potential Vgg.
[0011]
Here, the signal processing operation of the peak hold circuit 101 will be briefly described. When the output potential Va of the first source follower circuit 102, that is, the cathode potential Va of the diode D is lower than the anode potential Vm of the diode D, The diode D is turned on, and as a result, charges corresponding to the cathode potential Va are accumulated in the capacitor C.
[0012]
On the other hand, when the cathode potential Va of the diode D is higher than the anode potential Vm of the diode D, the diode D is turned off, so that the charge corresponding to the anode potential Vm is still accumulated in the capacitor C. That is, the charge accumulated by the low-level cathode potential that has been accumulated before remains accumulated, and the minimum level of the voltage signal input until the present stage is maintained.
[0013]
By repeating the above series of operations temporarily or periodically, the change in the voltage across the capacitor C (change in the peak level Vm held in the capacitor C) is amplified and output by the source follower circuit 103 in the subsequent stage. It is output from the terminal φout.
[0014]
In the period in which the cathode potential Va of the diode D is higher than the anode potential Vm, the gate electrode of the MOS transistor which is a high input impedance portion is connected to the subsequent stage of the anode of the diode D, and the capacitor C Thus, the outflow (transport) path of the electric charge accumulated in the output line is substantially eliminated, and the capacitor connection point c of the output line exists as a high impedance part.
[0015]
[Problems to be solved by the invention]
By the way, in the imaging device, there is a period in which a high level signal is output for a long period of time as an imaging signal, such as a charge accumulation period and a black level detection period.
[0016]
When such a high level signal is output for a long period of time, there is a phenomenon that the potential Vm at the high impedance generation site (capacitor connection point c of the output line) in the output circuit becomes higher depending on the use condition of the linear sensor. Arise.
[0017]
That is, due to the influence of light leaking into the high impedance portion c due to the dark current in the diffusion layer of the transistor in the high impedance portion c, the use condition of the linear sensor, etc., as shown in FIG. The potential of the high impedance portion c will rise.
[0018]
If the potential rise in the high impedance portion is left for a long time, the potential Vout appearing at the output terminal φout of the output circuit becomes equal to or higher than the potential Vdd1 designed as a rating, resulting in inconvenience in circuit operation. There is a possibility that it is not preferable in terms of ensuring reliability.
[0019]
Further, when the potential rise at the high impedance portion c is left for a long time, the potential rise is saturated at a certain potential, but the reference potential designed with the potential Vout appearing at the output terminal φout of the output circuit as a rating. If it is not desired to increase the voltage to Vdd1 or more, it is processed as a defective product, which may be disadvantageous in terms of improving the yield of the imaging device.
[0020]
In the above example, the potential increase at the high impedance portion c is taken as an example. However, depending on the circuit configuration, the potential at the high impedance portion drops due to the influence of the dark current, photoelectric conversion, etc. Thus, there is a possibility that a desired circuit operation is not performed.
[0021]
The above example shows an example of a peak hold circuit incorporated in an output circuit of an imaging device. In addition, in an electronic circuit incorporated in a mobile phone or various electronic devices, the potential of the high impedance generation portion is, for example, Changes due to temperature changes or the like, and as a result, the potential extracted from the output terminal may become an unrated potential.
[0022]
The present invention has been made in view of the above-described problems. The object of the present invention is to suppress the potential change level at a high impedance generation site to a predetermined potential and to regulate the output potential within the rating. , And An object of the present invention is to provide an electronic circuit capable of achieving reliable circuit operation.
[0027]
[Means for Solving the Problems]
The electronic circuit according to the present invention is configured by connecting a potential limiting circuit for limiting the potential at the high impedance generating portion to a predetermined potential. Thereby, for example, the level of the potential change in the high impedance generation portion due to temperature change, light leakage, or the like is limited to a predetermined potential by the potential limiting circuit. As a result, the output potential of the electronic circuit can be regulated within the rating, and a reliable circuit operation can be realized.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the electronic circuit according to the present invention On the road Embodiments of the present invention will be sequentially described with reference to FIGS.
[0046]
[Electronic circuit]
First, some embodiments in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage will be described with reference to FIGS.
[0047]
As shown in FIG. 1, the basic configuration of the signal output circuit according to the first embodiment is a first-stage source follower circuit 1 that amplifies the input signal Vin supplied to the input terminal φin with a predetermined gain (≈1). A peak hold circuit 2 for detecting and holding the minimum peak level Vm from the signal Va output from the source follower circuit 1 of the first stage, and a minimum peak level signal Vm held by the peak hold circuit 2 Is connected to a source follower circuit 3 that amplifies the signal with a predetermined gain (≈1).
[0048]
The source follower circuit 1 in the first stage is configured by connecting a drive transistor Tr1 and a load transistor Tr2 made of an N-MOS transistor in series between a power supply line Lp (power supply voltage Vdd) and the ground, and a gate electrode of the drive transistor Tr1. Are connected so as to be supplied with the input signal Vin. The output Va of the source follower circuit 1 is taken out from the common contact point a of both transistors Tr1 and Tr2.
[0049]
The peak hold circuit 2 includes a diode D1 composed of an enhancement type P-channel MOS transistor (hereinafter simply referred to as a P-MOS transistor) connected in the reverse direction to the output line in the source follower circuit 1 in the first stage, and an anode of the diode D1. The capacitor Ca is connected between the grounds.
[0050]
In the source follower circuit 3, a drive transistor Tr3 and a load transistor Tr4, which are enhancement-type N-channel MOS transistors (hereinafter simply referred to as N-MOS transistors), are connected in series between a power supply line Lp (power supply voltage Vdd) and the ground. Thus, the gate electrode of the drive transistor Tr3 is connected so that the anode potential of the diode D1 is supplied. The output Vout of the source follower circuit 3 is extracted from the output terminal φout through the common contact b of both transistors Tr3 and Tr4.
[0051]
The gate electrodes of the load transistors Tr2 and Tr4 in the first-stage source follower circuit 1 and the subsequent-stage source follower circuit 3 are connected to each other so as to be supplied with a gate potential Vgg.
[0052]
The signal output circuit according to the present embodiment has a potential limiting circuit (between the peak hold circuit 2 and the source follower circuit 3 in the subsequent stage) that limits the output potential Vm of the peak hold circuit 2 to a predetermined potential Vdd1. (Limiter circuit) 4 is connected.
[0053]
In the limiter circuit 4, a diode D2 is connected between the supply line of the predetermined potential Vdd1 and the output line of the peak hold circuit 4 by a P-MOS transistor connected in the forward direction to the supply line of the predetermined potential Vdd1. Has been configured. The predetermined potential Vdd1 is determined at the time of design, and indicates a potential at which the potential of the high impedance portion is not desired to be increased further. Therefore, in the following description, the predetermined potential Vdd1 is described as the reference potential Vdd1.
[0054]
Here, the signal processing operation of the signal output circuit according to the above embodiment will be described with reference to the signal waveform diagram of FIG.
[0055]
First, when the voltage level of the signal Vin input to the input terminal φin is lowered and the output potential Va of the first-stage source follower circuit 1, that is, the cathode potential Va of the diode D1, becomes lower than the anode potential Vm of the diode D1. More precisely, when the anode potential Vm-p is lower than the threshold value (Vm-Vth) of the p-channel MOS transistor, the diode D1 is turned on. As a result, the capacitor Ca has the cathode potential Va. The corresponding charge is accumulated. In this case, the anode potential Vm of the diode D1 is higher than the cathode potential Va of the diode D1 by the threshold value Vth.
[0056]
On the other hand, when the level of the signal Vin input to the input terminal φin becomes high and the cathode potential Va of the diode D1 becomes higher than the anode potential Vm of the diode D1, the diode D1 is turned off. The charge corresponding to the anode potential Vm is still accumulated in Ca. That is, the charges accumulated by the low-level cathode potential Vm accumulated before remain accumulated, and the minimum level of the voltage signal input until the present stage is maintained.
[0057]
By repeating the above series of operations temporarily or periodically, the change in the voltage across the capacitor Ca (change in the peak level Vm held in the capacitor Ca) is amplified by the source follower circuit 3 in the subsequent stage. It is output from the output terminal φout.
[0058]
During the period when the cathode potential Va of the diode D1 is higher than the anode potential, the gate electrode of the MOS transistor, which is a high input impedance portion, is connected to the subsequent stage of the anode of the diode D1, and the capacitor Ca is connected to the capacitor Ca. The outflow (transport) path of the accumulated charge is substantially eliminated, and the capacitor connection point c of the output line exists as a high impedance part.
[0059]
When the high impedance state at the capacitor connection point c is left for a long period of time, usually, the time elapses as shown in FIG. 2 due to a change in temperature or dark current in the diffusion layer of the transistor in the high impedance generation portion. At the same time, the potential of the high impedance generation portion c rises and eventually becomes saturated at a certain potential (see the broken line in FIG. 2).
[0060]
However, in the present embodiment, since the limiter circuit 4 having the above-described configuration is connected between the peak hold circuit 2 and the source follower circuit 3 at the subsequent stage, the potential of the high impedance portion c is the reference potential Vdd1. When the potential becomes slightly higher (Vdd1 + Vth), the diode D2 by the P-MOS transistor constituting the limiter circuit 4 is turned on, whereby the potential increase in the high impedance portion c is slightly higher than the reference potential Vdd1. It is limited at a high potential. The potential Vth indicates the threshold value of the P-MOS transistor.
[0061]
Since the output line of the peak hold circuit 4 is connected to the source follower circuit 3 by an N-MOS transistor in the subsequent stage, even if the potential of the high impedance portion c becomes the reference potential Vdd1 + threshold value Vth, From the output terminal φout of the follower circuit 3, a potential that is lower than the potential of the high impedance portion c by the threshold value of the N-MOS transistor appears. In other words, the source follower circuit 3 at the subsequent stage functions as a correction circuit that suppresses the potential increase by the threshold value Vth of the diode D2 constituting the limiter circuit 4.
[0062]
Therefore, the threshold values of the two transistors are adjusted by adjusting parameters such as the diffusion concentration and the channel width / channel length of the P-MOS transistor constituting the limiter circuit 4 and the N-MOS transistor constituting the source follower circuit 3. By making substantially the same, even if the potential of the high impedance portion c can be limited only to the reference potential Vdd1 + threshold value Vth by the limiter circuit 4, the potential appearing from the output terminal φout of the subsequent source follower circuit 3 is rated. Therefore, it is possible to improve the reliability without causing any inconvenience in circuit operation.
[0063]
Next, a signal output circuit according to a second embodiment will be described with reference to FIGS. In addition, the same code | symbol is described about the thing corresponding to FIG. 1, and the duplication description is abbreviate | omitted.
[0064]
The signal output circuit according to the second embodiment shows an example in which a voltage follower circuit 11 is connected to the subsequent stage of the output line of the peak hold circuit 3 as shown in FIG. Normally, as shown in the block diagram of FIG. 5A, the voltage follower circuit includes, for example, a differential amplifier circuit 12 using a current mirror circuit, and an output terminal Vc that amplifies the output Vc of the differential amplifier circuit 12 with a predetermined gain. The circuit is composed of a buffer circuit 13 that outputs from φout, has a feedback system 14, has substantially the same input and output DC levels, and has a gain of approximately 1. FIG. 5B shows a general circuit example in which the voltage follower circuit is configured by MOS transistors.
[0065]
In the signal output circuit according to the second embodiment, the limiter circuit 4 is constructed by inserting and connecting the source follower circuit 14 using a P-MOS transistor to the feedback system of the voltage follower circuit 11. The threshold value Vth of the diode D2 is increased.
[0066]
More specifically, the voltage follower circuit 11 of the signal output circuit according to the second embodiment has a differential amplifier circuit 12 using a current mirror circuit 15 and an output Vc of the differential amplifier circuit 12 as a predetermined value. Of the first source follower circuit 13 that is amplified with a gain (≈1) and output from the output terminal φout, and the output Vout of the first source follower circuit 13 is amplified with a predetermined gain (≈1) to obtain a voltage signal A second source follower circuit 14 that feeds back to the differential amplifier circuit 12 as Vd is connected.
[0067]
The differential amplifier circuit 12 in the voltage follower circuit 11 includes a current mirror circuit 15 configured by commonly connecting the drains of two P-MOS transistors Tr11 and Tr12 to a power supply line Lp, An input-side N-MOS transistor Tr13 connected in series to the source of one P-MOS transistor Tr11 and having the gate electrode supplied with the output Vm of the peak hold circuit 2, and the other P-MOS transistor 15 in the current mirror circuit 15. An output side NMOS transistor Tr14 connected in series to the source of the MOS transistor Tr12 and having the gate electrode supplied with the output Vd of the second source follower circuit 14, and a common contact d of the emitters of these NMOS transistors Tr13 and Tr14 N-MOS transistor Tr15 between Is constructed and a that the constant current source 16. The output Vc of the differential amplifier circuit 12 is taken out from a connection point e between the other P-MOS transistor Tr12 of the current mirror circuit 15 and the N-MOS transistor Tr14 on the output side.
[0068]
The first source follower circuit 13 is configured by connecting a drive transistor Tr21 and a load transistor Tr22 made of an N-MOS transistor in series between a power supply line Lp and the ground, and the differential amplification circuit is connected to the gate electrode of the drive transistor Tr21. The wiring is connected so that 12 outputs Vc are supplied. The output of the first source follower circuit 13 is extracted from the common contact f of both transistors Tr21 and Tr22 through the output terminal φout.
[0069]
The second source follower circuit 14 is configured by connecting a driving transistor Tr31 and a load transistor Tr32 made of a P-MOS transistor in series between the ground and the power supply line Lp, and the first source is connected to the gate electrode of the driving transistor Tr31. The wiring is connected so that the output Vout of the follower circuit 13 is supplied. The output Vd of the second source follower circuit 14 is taken out from the common contact g of the transistors Tr31 and Tr32 and is supplied to the gate electrode of the output side N-MOS transistor Tr14 in the differential amplifier circuit 12. It is connected.
[0070]
Note that the N-MOS transistor Tr15 constituting the constant current source 16 of the differential amplifier circuit 12 and each gate electrode of the load transistor Tr22 in the first source follower circuit 13 are connected to the load transistor Tr2 in the source follower circuit 1 in the first stage. The same gate potential (first gate potential) Vgg1 as the applied gate potential is supplied, and the second gate potential Vgg2 is supplied to the gate electrode of the load transistor Tr32 in the second source follower circuit 14. Wired connection.
[0071]
Here, the signal processing operation of the signal output circuit according to the second embodiment, particularly the voltage follower circuit 11, will be described. The high impedance state at the capacitor connection point c is left for a long time, and the high impedance portion c When the potential Vm rises in the form of a ramp signal, first, the limiter circuit 4 limits the potential rise of the high impedance portion c to the reference potential Vdd1 + threshold value Vth. At this time, since the second source follower circuit 14 is composed of a P-MOS transistor, the feedback potential Vout output from the first source follower 13 is changed to P by the second source follower circuit 14. -Increased by the threshold value of the MOS transistor.
[0072]
In this case, the parameters such as the diffusion concentration and the channel width / channel length of the P-MOS transistor constituting the limiter circuit 4 and the P-MOS transistor constituting the second source follower circuit 14 are adjusted to adjust the If the threshold values are substantially the same, the potentials corresponding to the threshold values of the signals Vm and Vd supplied to both input sides of the differential amplifier circuit 12 are canceled, and the potential appearing at the output terminal φout is set to the reference potential. It can be lowered to Vdd1.
[0073]
That is, by connecting the voltage follower circuit 11 according to this embodiment, as shown in FIG. 4, the potential Vout appearing at the output terminal φout can be limited to the reference potential Vdd1 or less designed at the rating, and the circuit operation The reliability can be improved without causing any inconvenience.
[0074]
Next, a signal output circuit according to a third embodiment will be described with reference to FIG. In addition, the same code | symbol is described about the thing corresponding to FIG. 1, and the duplication description is abbreviate | omitted.
[0075]
As shown in FIG. 6, the signal output circuit according to the third embodiment has a configuration in which a clamp circuit 5 is connected instead of the peak hold circuit 2 in the signal output circuit according to the first embodiment. Have.
[0076]
Specifically, the clamp circuit 5 is connected between the coupling capacitor Cb connected to the output line of the first source follower circuit 1, the output line derived from the coupling capacitor Cb, and the supply line of the reference potential Vdd1. Switching circuit SW. The switching circuit SW can be configured by, for example, an N-MOS transistor. In this case, the supply line of the reference potential Vdd1 is connected to the drain, the output line derived from the coupling capacitor Cb is connected to the source, and the gate electrode Are connected so as to be supplied with the switching control signal Sc.
[0077]
The signal processing operation of this signal output circuit will be described. The signal component DC of the signal Va output from the first-stage source follower circuit 1 is removed by the coupling capacitor Cb of the clamp circuit 5, and the signal swings positive / negative around the 0 level. It will be taken out as Vb. Then, during a certain reference period of the signal Vb, the switching control signal Sc becomes high level, for example, and the switching circuit SW is turned on, so that the output level of the reference period becomes the reference potential Vdd1. Therefore, the clamp circuit 5 extracts a signal Vc that swings to the positive side and the negative side around the reference potential Vdd1.
[0078]
When the switching circuit SW is in an off state, the connection point h with the output line of the switching circuit SW is in a high impedance state. If this state is left for a long period of time, as in the case of the first embodiment, The potential Vc of the impedance portion h will increase.
[0079]
However, in the third embodiment, since the limiter circuit 4 is connected to the subsequent stage of the clamp circuit 5, the potential rise at the high impedance portion h is limited to the reference potential Vdd1 + threshold value Vth. The potential Vout appearing from the output terminal φout of the source follower circuit 3 is equal to or less than the reference potential Vdd1 designed by rating.
[0080]
In the signal output circuit according to the third embodiment, an example in which the source follower circuit 3 using an N-MOS transistor is connected to the subsequent stage of the limiter circuit 4 is shown in FIG. 3 instead of the source follower circuit 3. The voltage follower circuit 11 according to the second embodiment shown may be connected. Also in this case, the potential Vout appearing from the output terminal φout of the first source follower circuit 13 is equal to or lower than the reference potential Vdd1 designed by rating.
[0081]
Next, a signal output circuit according to a fourth embodiment will be described with reference to FIG. Note that components corresponding to those in FIG. 6 are denoted by the same reference numerals, and redundant description thereof is omitted.
[0082]
As shown in FIG. 7, the signal output circuit according to the fourth embodiment has substantially the same configuration as the signal output circuit according to the third embodiment shown in FIG. 6, but includes a clamp circuit 5 and a limiter. The difference is that a correction circuit 6 that suppresses the potential Vc of the high impedance portion h to the reference potential Vdd1 or less is inserted and connected between the circuits 4.
[0083]
The correction circuit 6 is configured by connecting a driving transistor Tr5 and a load transistor Tr6 made of a P-MOS transistor in series between a ground and a power supply line (power supply voltage Vdd). A coupling capacitor Cb is connected to the gate electrode of the driving transistor Tr5. The output line derived from is connected. The output Vd of the correction circuit 6 is extracted from the common contact i of both transistors Tr5 and Tr6. In this case, the threshold value of the P-MOS transistor constituting the correction circuit 6 is adjusted to be substantially the same as the threshold value Vth of the P-MOS transistor constituting the limiter circuit 4. Note that the gate electrode of the load transistor Tr6 in the correction circuit 6 is wired to be supplied with the second gate potential Vgg2.
[0084]
The signal processing operation of the correction circuit 6 will be described. Since the correction circuit 6 is composed of a source follower circuit using P-MOS transistors, the output potential Vd is higher than the input potential Vb by the threshold value Vth. Become. Therefore, when the potential of the high impedance portion h rises to become the reference potential Vdd1, the output potential Vd of the correction circuit 6 becomes the reference potential Vdd1 + threshold value Vth. Thus, the subsequent limiter circuit 4 is turned on. Then, the output potential Vd of the correction circuit 6 is not increased any further. That is, the potential increase in the high impedance portion h is limited by the reference potential Vdd1.
[0085]
As described above, in the signal output circuit according to the fourth embodiment, both the potential increase of the high impedance portion h and the potential increase appearing at the output terminal φout can be limited to the reference potential Vdd1.
[0086]
In the example of FIG. 7, an example in which the source follower circuit 3 using an N-MOS transistor is connected to the subsequent stage of the limiter circuit 4 is shown, but according to the second embodiment shown in FIG. 3 instead of the source follower circuit 3. The voltage follower circuit 11 may be connected.
[0087]
[Solid-state imaging device]
Next, an embodiment in which the solid-state imaging device according to the present invention is applied to a linear sensor having a CCD structure transfer stage (hereinafter simply referred to as a linear sensor according to the embodiment) will be described with reference to FIGS. While explaining.
[0088]
As shown in FIG. 8, the linear sensor according to this embodiment has a large number of light receiving units 21 that convert incident light from a subject into signal charges having a charge amount corresponding to the amount of light (for example, 2000 pixels). And a transfer register 24 having a CCD structure for transferring a signal charge read from each light receiving portion 21 of the sensor array 22 via the read gate 23 in one direction. It is configured.
[0089]
Reading of signal charges by the read gate 23 is performed by applying a gate pulse φROG. In addition, by applying two-phase transfer pulses φH1 and φH2 having different phases to the transfer electrode formed of, for example, two polycrystalline silicon layers formed on the transfer register 24, the signal charge on the transfer register 24 is unidirectionally changed. Will be transferred.
[0090]
An output unit 25 is connected to the final stage of the transfer register 24. The output unit 15 converts a signal charge transferred from the final stage of the transfer register 24 into an electric signal (for example, a voltage signal Vi), for example, a charge-electric signal conversion unit configured by a floating diffusion or a floating gate. 26 and a reset gate RG that sweeps the signal charge after being converted into the voltage signal Vi by the charge-electric signal converter 26 into the drain region D according to the input of the reset pulse φRG. Has been. A power supply voltage Vdd is applied to the drain region D through a power supply line Lp.
[0091]
Further, a buffer circuit 27 composed of, for example, a source follower circuit for amplifying the voltage signal Vi from the charge-electric signal converter 26 is formed at the subsequent stage of the charge-electric signal converter 26.
[0092]
The linear sensor according to the present embodiment is configured by connecting a signal output circuit 28 to the subsequent stage of the buffer circuit 27. The signal output circuit 28 is formed on the same substrate (on-chip formation) together with the sensor array 22, the readout gate 23, the transfer register 24, and the output unit 25.
[0093]
Here, the processing operation of the linear sensor will be briefly described. First, in the charge accumulation period, signal charges corresponding to incident light from the subject are accumulated in each light receiving unit 21 of the sensor array 22. In the subsequent charge reading, the signal charges accumulated in the sensor array 22 are read out to the transfer register 24 by applying a gate pulse φROG to the reading gate 23. In the next scanning period, the supply of the two-phase transfer pulses φH1 and φH2 to the transfer register 24 sequentially changes the potential distribution below each transfer electrode in the transfer register 24, whereby the signal charge is transferred to the transfer register 24. Are sequentially transferred to the charge-electrical signal conversion unit 26 of the output unit 25, converted into a voltage signal Vi by the charge-electrical signal conversion unit 26, and supplied to the signal output circuit 28 via the buffer circuit 27 in the subsequent stage. Will be.
[0094]
Here, several configuration examples of the signal output circuit 28 will be described. First, as shown in FIG. 9, the signal output circuit according to the first configuration example is the first embodiment shown in FIG. The signal output circuit has substantially the same configuration, but differs in that the output line of the first source follower circuit 1 is branched into two. Accordingly, components corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description thereof is omitted.
[0095]
Of the two output lines L1 and L2 derived from the source follower circuit 1 in the first stage, one output line (main line) L1 is connected to the first output terminal φ1 derived to the outside and connected to the input terminal. The voltage signal Vi input to φin is taken out as the imaging signal Vs through the first output terminal φ1, and the other output line (branch line) L2 is connected to the above-described output in the same manner as in the first embodiment. A peak hold circuit 2 that detects and holds the minimum peak level Vm of the voltage signal Vi is connected, and a source follower circuit 3 using an N-MOS transistor is connected to the subsequent stage. The output line of the source follower circuit 3 is connected to a second output terminal φ2 led to the outside.
[0096]
Therefore, the imaging signal Vs obtained by amplifying the voltage signal Vi from the linear sensor with a predetermined gain is output from the first output terminal φ1, and the voltage signal from the linear sensor is output from the second output terminal φ2. A signal indicating the minimum peak level of Vi (hereinafter referred to as a peak detection signal Vp) is output.
[0097]
Usually, in the linear sensor, there is a period during which a high level signal is output as the voltage signal Vi for a long period of time, such as during standby for operation, a charge accumulation period, and a black level detection period. In this case, a phenomenon occurs in which the capacitor connection point c of the peak hold circuit 2 connected to the branch line L2 is in a high impedance state, and the potential Vm of the high impedance portion c increases depending on the use conditions of the linear sensor and the like. That is, light leaks into the high impedance portion c depending on the use condition of the linear sensor, and as a result, the potential of the high impedance portion c rises due to photoelectric conversion in the diffusion layer of the transistor in the high impedance portion c. Become.
[0098]
If the potential rise at the high impedance portion c is left for a long time, the output level of the peak detection signal Vp output from the second output terminal φ2 becomes equal to or higher than the reference potential Vdd1 designed as a rating, which is inconvenient in circuit operation. May occur, which is not preferable in terms of ensuring reliability.
[0099]
However, in the first configuration example of the signal output circuit 28 in the linear sensor according to the present embodiment, a limiter circuit that limits the potential Vm at the high impedance portion c to approximately the reference potential Vdd1 after the peak hold circuit 2. 4, even if the potential rises due to light leakage or the like in the high impedance portion c, the potential rise is limited to the reference potential Vdd 1 + threshold value Vth by the limiter circuit 4. In addition, since the source follower circuit 3 including the N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, the potential Vp appearing at the second output terminal φ2 can be suppressed to the reference potential Vdd1 or lower. Effectively improve the reliability of linear sensor circuit operation and the yield of linear sensors Door can be.
[0100]
Next, a second configuration example of the signal output circuit 28 will be described with reference to FIG. 10. The signal output circuit 28 according to the second configuration example is the same as that of the second embodiment shown in FIG. The signal output circuit has substantially the same configuration as that of the first signal output circuit, except that the output line of the first-stage source follower circuit 1 is branched into two (main line L1 and branch line L2) as in the first configuration example.
[0101]
Specifically, of the two output lines L1 and L2 derived from the first-stage source follower circuit 1, the first output terminal φ1 led to the outside is connected to one output line (main line) L1. Thus, the voltage signal Vi input to the input terminal φin is taken out as the imaging signal Vs through the first output terminal φ1, and the other output line (branch line) L2 is the same as in the first embodiment. Further, a peak hold circuit 2 that detects and holds the minimum peak level of the voltage signal Vi is connected, and a voltage follower circuit 11 according to the second embodiment is connected to the subsequent stage. The output line of the first source follower circuit 13 in the voltage follower circuit 11 is connected to the second output terminal φ2 led to the outside.
[0102]
Also in the second configuration example, similarly to the first configuration example, the limiter circuit 4 that limits the potential Vm at the high impedance portion c to the reference potential Vdd1 is connected to the subsequent stage of the peak hold circuit 2. Therefore, even if the potential rises due to light leakage or the like in the high impedance portion c, the potential rise is limited to the reference potential Vdd1 + threshold value Vth by the limiter circuit 4, and Since the voltage follower circuit 11 is connected to the subsequent stage of the limiter circuit 4, the potential Vp appearing at the second output terminal φ2 can be suppressed below the reference potential Vdd1, and the reliability of the circuit operation of the linear sensor can be reduced. It is possible to effectively improve the yield of the linear sensor.
[0103]
Next, a third configuration example of the signal output circuit 28 will be described with reference to FIG. 11. The signal output circuit according to the third configuration example is related to the first embodiment shown in FIG. Although it has substantially the same configuration as the signal output circuit, it differs from the first configuration example in that the output line of the first source follower circuit 1 is branched into two (main line L1 and branch line L2).
[0104]
A difference from the first configuration example is that the clamp circuit 5, the limiter circuit 4, and the source follower circuit 3 according to the third embodiment shown in FIG. 6 are connected to the main line L1.
[0105]
As shown in FIG. 12, the waveform of the voltage signal Vi input to the input terminal φin is a reset pulse φRG (potential) applied to the reset gate RG to the signal component Vsig from the charge-electrical signal converter 26 in the output unit 25. Vrg) has a waveform added by coupling. A period between the output period Ts of the signal component Vsig and the output period Tc of the coupling component Vrg is a feedthrough period Tf.
[0106]
Therefore, in the main line L1 in the third configuration example, the DC component (in this case, the feed-through component Vf) of the signal output from the first source follower circuit 1 is removed by the coupling capacitor Cb of the clamp circuit 5, The feedthrough component is set to a signal output Vb in which the level is zero. Then, in the signal Vb output from the coupling capacitor Cb, the switching control signal Sc becomes high level, for example, in synchronization with the feedthrough period Tf, and the switching circuit SW is turned on, so that the output of the feedthrough period Tf is output. The level becomes the reference potential Vdd1. Therefore, the signal Va (≈Vi) output from the first-stage source follower circuit 1 is level-shifted from the clamp circuit 5, and the signal Vc having the feedthrough component Vf as the reference potential Vdd1 is extracted. .
[0107]
In this case, the output level of the coupling period Tc becomes very high, but the level is limited by the limiter circuit 4 to the reference potential Vdd1 + threshold value Vth, and further, the source follower circuit 3 in the subsequent stage receives the coupling period. A signal Vp in which the output level of Tc is the same as the reference potential Vdd1 as that of the feedthrough component is extracted. That is, from the first output terminal φ1, an unnecessary coupling component Vrg is removed and a signal including only the necessary signal component Vsig is extracted as the imaging signal Vs, so that the dynamic range of the imaging signal Vs is increased. Therefore, it is possible to effectively improve the sensitivity.
[0108]
In the third configuration example, as described in the signal output circuit according to the sixth embodiment, when the switching circuit SW is in the OFF state, the connection point h with the output line of the switching circuit SW. Becomes a high impedance state, and if this state is left for a long period of time, the potential Vc of the high impedance portion h rises.
[0109]
However, in this third configuration example, since the limiter circuit 4 is connected to the subsequent stage of the clamp circuit 5, the potential rise at the high impedance portion h is limited to the reference potential Vdd1 + threshold value Vth, The potential Vs appearing from the output terminal (first output terminal φ1) of the source follower circuit 3 is equal to or lower than the reference potential Vdd1 designed by rating.
[0110]
Next, a fourth configuration example of the signal output circuit will be described with reference to FIG. 13. The signal output circuit according to the fourth configuration example is the same as the output circuit according to the third configuration example shown in FIG. The correction circuit 6 is inserted and connected between the clamp circuit 5 and the limiter circuit 4 in the same manner as the signal output circuit according to the fourth embodiment shown in FIG. Different.
[0111]
In this case, when the potential of the high impedance portion h rises to become the reference potential Vdd1, the output potential of the correction circuit 6 becomes the reference potential Vdd1 + threshold value Vth. Thus, the subsequent limiter circuit 4 is turned on. Then, the output potential Vd of the correction circuit 6 is not increased any further. That is, the potential increase in the high impedance portion h is limited by the reference potential Vdd1.
[0112]
Therefore, in the output circuit according to the fourth configuration example, it is possible to limit both the potential rise of the high impedance portion h and the potential Vs appearing at the output terminal φ1 to the reference potential Vdd1.
[0113]
In the third configuration example shown in FIG. 12 and the fourth configuration example shown in FIG. 13, the source follower circuit 3 using an N-MOS transistor is connected to the subsequent stage of the limiter circuit 4. Instead of the circuit 3, the voltage follower circuit 11 according to the second embodiment may be connected. Also in this case, the potentials Vp and Vs appearing from the output terminals φ1 and φ2 of the first source follower circuit 13 are equal to or lower than the reference potential Vdd1 designed by rating.
[0114]
[Imaging device]
Next, an embodiment in which the imaging device according to the present invention is applied to a camera device using a linear sensor having a CCD-structure transfer stage for focus control (hereinafter simply referred to as a camera device according to the embodiment) will be described. This will be described with reference to FIG.
[0115]
In the camera device according to this embodiment, as shown in the figure, a linear sensor 32 for focus control is incorporated in a camera body 31 that captures an object, and the signal output level of the linear sensor 32 is set to an appropriate level. It has a gain control means 33 for controlling.
[0116]
The camera body 31 includes a zoom lens unit 41 configured to incorporate a focus lens, a variator, a compensator, an erector, a relay lens, and the like, and light from a subject that has an electronic shutter function and is incident through the zoom lens unit 41. Of the linear sensor 32 that converts the signal charge into an amount corresponding to the amount of light and outputs it as an electrical signal, and timing generation for generating various timing signals such as a read gate pulse and a transfer clock for driving the linear sensor 32 The circuit 42 and the gain control means 33 for performing control for obtaining an appropriate signal output level based on the output from the linear sensor 32 are configured.
[0117]
The linear sensor 32 has the same configuration as that of the linear sensor according to the present embodiment shown in FIG. 8, and the output circuit has the same configuration as that shown in FIGS. Therefore, detailed description of the linear sensor 32 and its output circuit is omitted.
[0118]
The gain control means 33 controls the timing of the timing generation circuit 42 based on the level (minimum peak level) of the peak detection signal Vp output from the second output terminal φ2 of the output circuit in the linear sensor 32, thereby linearly An exposure adjustment circuit 43 that adjusts the exposure time of the sensor 32, and a calculation that calculates a focus shift based on the level of the imaging signal Vs output from the first output terminal φ1 of the output circuit and outputs the focus error signal Sf. A circuit 44, and an autofocus control circuit 46 that performs focus adjustment by moving the focus lens 45 in the optical axis direction in accordance with the current focus shift based on the focus error signal Sf from the arithmetic circuit 44. Configured.
[0119]
Here, the operation of the camera device according to the present embodiment when the first configuration example shown in FIG. 9 is used as the output circuit of the linear sensor 32 will be described. First, in the linear sensor 32, incidence from a subject is performed. An imaging signal Vs having a signal component of a level corresponding to the amount of light is converted to a signal charge corresponding to the amount of light, and is output through the main line L1 of the output circuit, and the imaging signal Vs is output through the branch line L2. The peak level is detected and output as the peak detection signal Vp.
[0120]
The imaging signal Vs and the peak detection signal Vp are supplied to the gain control means 33 at the subsequent stage, and control for obtaining an appropriate signal output level is performed. That is, the length of exposure time in the linear sensor 32 is adjusted according to the level of the peak detection signal Vp, and focus adjustment is performed according to the level of the imaging signal Vs.
[0121]
In the exposure time control by the exposure adjustment circuit 43, if the level of the peak detection signal Vp output from the output circuit is larger than the reference level, the timing generation circuit is configured so that the exposure time at the linear sensor 32 is shortened. 42 is controlled, and if the level of the peak detection signal Vp is smaller than the reference level, the timing of the timing generation circuit 42 is controlled so that the exposure time in the linear sensor 32 becomes longer.
[0122]
In this case, the output circuit according to the first configuration example, as shown in FIG. 9, limits the potential Vm at the high impedance portion (capacitor connection point c) to the reference potential Vdd1 at the subsequent stage of the peak hold circuit 2. Since the limiter circuit 4 is connected, even if the potential Vm is increased due to light leakage or the like in the high impedance portion c, the potential increase is caused by the limiter circuit 4 by the reference potential Vdd1 + threshold value Vth. In addition, since the source follower circuit 3 including the N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, the potential Vp appearing at the second output terminal φ2 is suppressed to be equal to or lower than the reference potential Vdd1. can do.
[0123]
That is, the level of potential change at the high impedance portion c of the output circuit in the linear sensor 32 can be suppressed to substantially the reference potential Vdd1, thereby the peak detection signal Vp output from the output circuit of the linear sensor 32. The output level can be regulated within the rating, and control for obtaining an appropriate signal output level in the gain control means 33 can be performed satisfactorily. This leads to an improvement in imaging characteristics of the camera device.
[0124]
Next, when the second configuration example shown in FIG. 10 is used as the output circuit of the linear sensor 32, the peak hold circuit 2 of the peak hold circuit 2 is similar to the case where the output circuit according to the first configuration example is used. Since the limiter circuit 4 that restricts the potential Vm at the high impedance portion c to substantially the reference potential is connected to the subsequent stage, even if the potential Vm increases due to light leakage or the like in the high impedance portion c, The rise in the potential is limited to the reference potential Vdd1 + threshold value Vth by the limiter circuit 4, and the voltage follower circuit 11 is connected to the subsequent stage of the limiter circuit 4, so that the second output terminal φ2 Can be suppressed to the reference potential Vdd1 or less, and thereby the output level from the output circuit of the linear sensor 32 can be reduced. Le a can be restricted within the rated, the control for obtaining a proper signal output level of the gain control means 33 can be satisfactorily performed.
[0125]
Next, when the third configuration example shown in FIG. 11 and the fourth configuration example shown in FIG. 13 are used as the output circuit of the linear sensor 32, an unnecessary coupling component Vrg is generated from the second output terminal φ2. Since the signal including only the necessary signal component Vsig after being removed is extracted as the imaging signal Vs, the dynamic range of the imaging signal Vs can be increased, and the sensitivity can be effectively improved.
[0126]
In addition, since the limiter circuit 4 is connected to the subsequent stage of the clamp circuit 5, the potential rise at the high impedance portion (the connection point h with the output line of the switching circuit) is the reference potential Vdd1 + in the third configuration example. The threshold value Vth is limited. In the case of the fourth configuration example, the potential is limited to the reference potential Vdd1. Become. In particular, in the fourth configuration example, it is possible to limit both the increase in potential of the high impedance portions c and h and the increase in potentials Vs and Vp appearing at the output terminals φ1 and φ2 to the reference potential Vdd1.
[0127]
As a result, the output level from the output circuit of the linear sensor 32 can be regulated within the rating, and control for obtaining an appropriate signal output level in the gain control means 33 can be performed satisfactorily. In the output circuits according to the third configuration example and the fourth configuration example, the source follower circuit 3 using an N-MOS transistor is connected to the subsequent stage of the limiter circuit 4. However, instead of the source follower circuit 3, The voltage follower circuit 11 according to the second embodiment shown in FIG. Also in this case, the potentials Vs and Vp appearing from the output terminals φ1 and φ2 of the first source follower circuit 13 are equal to or lower than the reference potential Vdd1 designed by rating.
[0128]
In the above embodiment, the example applied to the output circuit of the linear sensor 32 has been shown. However, in addition, a large number of light receiving units are connected to the final stage of the horizontal transfer register of the image sensor arranged in a matrix. It can also be applied to an output circuit.
[0129]
[Light receiving device]
Next, an embodiment in which the light receiving device according to the present invention is applied to, for example, a remote sensor on the receiving side used for optical communication (hereinafter referred to as a remote sensor according to the embodiment) will be described with reference to FIGS. While explaining.
[0130]
As shown in FIG. 15, the remote sensor according to this embodiment includes, for example, a sensor unit 51 having a photodiode FD, and an output circuit that amplifies an output signal Vin from the sensor unit 51 and supplies the amplified signal to a subsequent decoder 52. 53.
[0131]
The sensor unit 51 includes a bias power supply 54 (power supply voltage −V) whose + pole is grounded, the photodiode FD connected in the reverse direction with respect to the flow of current i, and the cathode of the photodiode FD and the ground. And a load resistor R connected therebetween. In the sensor unit 51, when light is incident from the outside, a light detection signal Vin having a negative voltage level corresponding to the amount of incident light is output.
[0132]
The transmission system that outputs an optical signal to the remote sensor according to the present embodiment is configured to optically modulate code data to be transmitted and output it as an infrared optical signal. An example of the optical signal for the code data is shown in FIG. 16A. This optical signal has a signal form in which the output level of infrared rays is made variable in accordance with logical values “0” and “1”.
[0133]
Then, when the optical signal from the transmission system is incident on the remote sensor, for example, as shown in FIG. 16B, a light detection signal Vin corresponding to the light output level of the light signal is taken out. For example, when the optical signal in FIG. 16A is incident, for a logical value “1” with a high optical output level, a light detection signal with a sharp voltage level drop is output, and a logical value with a low optical output level is output. For “0”, a light detection signal with a gradual drop in voltage level is output.
[0134]
Since the output circuit 53 has the same configuration as that of the signal output circuit according to the third embodiment shown in FIG. 6, the detailed description thereof is omitted, but the switching control signal Sc supplied to the switching circuit SW is In the period in which the logical value is determined in the input signal (photodetection signal) Vin, the signal form is high in, for example, a quarter period at each head. This ¼ period is a period during which the optical output is always 0, and therefore the signal Va output from the first source follower circuit 1 is always at a high level in the ¼ period. Therefore, when the switching circuit SW is turned on in the ¼ period, the high level in the ¼ period is clamped to the reference potential Vdd1.
[0135]
Therefore, the signal Vout output from the output terminal φout of the output circuit 53 has the ¼ period set as the reference potential Vdd1 when the optical signal indicates the logical value “1”, and the ¼ period has passed. When the signal waveform sharply drops to a low level from the point in time and the optical signal shows a logical value “0”, the ¼ period is set to the reference potential Vdd1, and the level is gradually lowered from the lapse of the ¼ period. The signal waveform falls into
[0136]
The decoder 52 detects the potential in the predetermined period τ from the ¼ period of the signal Vout output from the output circuit 53, and the potential difference (detection voltage) between the detected potential and the reference potential Vdd1 is higher than the reference voltage Vr. If it is higher, that is, the detected voltage is V _H Is recognized as a logical value “1”, and if it is lower than the reference voltage Vr, that is, the detected voltage is V _L In this case, it has a circuit configuration that recognizes it as logic “0” and outputs it as digital code information Dc. The code information Dc from the decoder 52 is supplied to a system controller (not shown), for example, and control according to the code information Dc is performed.
[0137]
In this case, as shown in FIG. 6, the output circuit 53 is configured to connect the limiter circuit 4 to the subsequent stage of the clamp circuit 5, so that the high impedance portion (the connection point h with the output line of the switching circuit SW). ), Even if the potential Vc rises due to light leakage or the like, the potential rise is limited to the reference potential Vdd1 + threshold value Vth by the limiter circuit 4, and N− Since the source follower circuit 3 by the MOS transistor is connected, the potential Vout appearing at the output terminal φout can be suppressed to the reference potential Vdd1 or lower.
[0138]
As a result, the output level from the output circuit 53 can be regulated within the rating, and the conversion to the code information Dc in the subsequent decoder 52 can be performed satisfactorily.
[0139]
The output circuit 53 is connected to the source follower circuit 3 formed of an N-MOS transistor at the subsequent stage of the limiter circuit 4, but instead of the source follower circuit 3, the voltage according to the second embodiment shown in FIG. The follower circuit 11 may be connected. Also in this case, the potential Vout appearing from the output terminal φout of the first source follower circuit 13 is equal to or lower than the reference potential Vdd1 designed by rating.
[0140]
As another configuration, the circuit configuration shown in FIG. 6 is adopted as the output circuit 53, but the circuit configuration according to the fourth embodiment shown in FIG. 7 may be used. In this case, it is possible to limit both the increase in potential of the high impedance portion h and the increase in potential Vout appearing at the output terminal φout to the reference potential Vdd1.
[0141]
【The invention's effect】
As described above, according to the electronic circuit of the present invention, the potential limiting circuit for limiting the potential at the high impedance generation portion to the predetermined potential is connected to the high impedance generation portion. The level of change can be suppressed to a predetermined potential, the output potential can be regulated within the rating, and a reliable circuit operation can be achieved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.
FIG. 2 is a waveform diagram showing potential changes at a high impedance portion and an output terminal in the signal output circuit according to the first embodiment.
FIG. 3 is a circuit diagram showing a second embodiment in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.
FIG. 4 is a waveform diagram showing potential changes at a high impedance portion and an output terminal in a signal output circuit according to a second embodiment.
5A and 5B are diagrams showing a general configuration of a voltage follower circuit, where FIG. 5A is a block diagram and FIG. 5B is a circuit diagram.
FIG. 6 is a circuit diagram showing a third embodiment in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.
FIG. 7 is a circuit diagram showing a fourth embodiment in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.
[Fig. 8] Solid 1 is a configuration diagram illustrating an embodiment in which a body imaging device is applied to a linear sensor having a CCD-structure transfer stage (hereinafter simply referred to as a linear sensor according to an embodiment).
FIG. 9 is a circuit diagram illustrating a first configuration example of the signal output circuit of the linear sensor according to the present embodiment.
FIG. 10 is a circuit diagram showing a second configuration example of the signal output circuit of the linear sensor according to the present embodiment.
FIG. 11 is a circuit diagram showing a third configuration example of the signal output circuit of the linear sensor according to the present embodiment.
FIG. 12 is a timing chart showing signal processing on the main line of the third configuration example in the signal output circuit of the linear sensor according to the present embodiment;
FIG. 13 is a circuit diagram showing a fourth configuration example of the signal output circuit of the linear sensor according to the present embodiment.
FIG. 14 Shoot It is a block diagram which shows the embodiment which applied the imaging device to the camera apparatus which used the linear sensor which has the transfer stage of CCD structure for focus control.
FIG. 15 Receiving It is a block diagram which shows the embodiment (it is hereafter described as the remote sensor which concerns on embodiment) which applied the optical apparatus to the remote sensor of the receiving side used for optical communication, for example.
FIG. 16 is a timing chart showing signal processing in the output circuit of the remote sensor according to the present embodiment.
FIG. 17 is a circuit diagram showing a configuration of a conventional signal output circuit in a linear sensor.
FIG. 18 is a waveform diagram showing potential changes at a high impedance portion and an output terminal of a signal output circuit according to a conventional example.
[Explanation of symbols]
1 Source follower circuit of the first stage, 2 Peak hold circuit, 3 Source follower circuit of the subsequent stage, 4 Limit circuit, 5 Clamp circuit, D1, D2, D diode, 11 Voltage follower circuit, 22 Sensor array, 24 Transfer register, 26 Charge − Electrical signal conversion unit, 28 signal output circuit, L1 main line, L2 branch line, Lp power supply line, 31 camera body, 32 linear sensor, 33 gain control means, 42 timing generation circuit, 43 exposure adjustment circuit, 44 arithmetic circuit, 45 focus lens 46 Autofocus control circuit 51 Sensor unit 52 Decoder 53 Output circuit

Claims (10)

In an electronic circuit as an output circuit that outputs an electrical signal,
A potential limiting circuit that limits the potential at the high impedance generation portion of the output circuit to a predetermined potential is connected to the output circuit ,
The potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential generating source and the high impedance generating portion,
An electronic circuit, wherein a correction circuit for suppressing a potential increase corresponding to a threshold value of a diode constituting the potential limiting circuit in the high impedance generating portion is connected . The high impedance generator portion, an electronic circuit according to claim 1, characterized in that the capacitor connection point in the connected peak-hold circuit in front of the high input impedance section. 3. The electronic circuit according to claim 2 , wherein the peak hold circuit includes a diode connected in the reverse direction with respect to a signal input direction and a capacitor connected between an anode of the diode and the ground. . 3. A correction circuit that suppresses a potential increase corresponding to a threshold value of a diode that constitutes the potential limiting circuit in the high impedance generation portion is connected to the subsequent stage of the capacitor connection point. 3. The electronic circuit according to 3 . 5. The electronic circuit according to claim 4 , wherein the correction circuit is a source follower circuit using an n-channel MOSFET. 5. The electronic circuit according to claim 4 , wherein the correction circuit is a source follower circuit using a p-channel MOSFET connected to a feedback system in a voltage follower circuit. The high impedance generator portion, an electronic circuit according to claim 1, wherein the at connected clamping circuit in front of the high input impedance unit is a selective supply point of the clamp voltage. The clamp circuit according to claim 7, characterized in that it is constituted by a connected switching circuits between coupling capacitance connected to the input signal line and the output-side electrode and the clamp voltage generating source of the binding capacity Electronic circuit. A correction circuit is connected between the selective supply point of the clamp voltage and the diode constituting the potential limiting circuit to suppress the potential increase of the threshold voltage of the diode constituting the potential limiting circuit at the high impedance generation portion. 9. The electronic circuit according to claim 7 , wherein the electronic circuit is provided. 10. The electronic circuit according to claim 9 , wherein the correction circuit is a source follower circuit using a p-channel MOSFET.

Images