JPH09247544A - Electronic circuit, solid-state image pickup element, output circuit for solid-state image pickup element, image pickup device and light receiving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain reliable circuit operation by regulating output potential within rating by suppressing the level of potential change at a high impedance generating part to a prescribed potential. SOLUTION: A source follower circuit 1 of a first stage to current-amplify an input signal Vin supplied to an input terminal ϕin , a peak hold circuit 2 to detect the minimum peak level Vm of a signal Va outputted from the circuit 1 from the same signal Va , and hold it, and the source follower circuit 3 to current-amplify the peak level Vm held by the peak hold circuit 2 are connected, and further, a limiter circuit 4 to limit the output potential Vm of the peak hold circuit 2 to a prescribed potential Vdd1 is connected between the peak hold circuit 2 and the source follower circuit 3. The peak hold circuit 2 is composed of a diode D1 by a P-MOS transistor and a capacitor Ca connected between the anode of the diode D1 and the ground, and the limiter circuit 4 is composed of the diode D2 by the P-MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit having an electronic circuit structure capable of suppressing a level increase at a constant level at a portion which is temporarily or periodically in a high impedance state during the electrical operation stage thereof. A circuit, a solid-state image sensor in which the configuration of the electronic circuit is formed on the same substrate together with the image capturing section of the solid-state image sensor, and the output circuit when the configuration of the electronic circuit is applied to the output circuit of the solid-state image sensor, The present invention relates to an imaging device equipped with the solid-state imaging device and a light-receiving device incorporating the electronic circuit.

[0002]

2. Description of the Related Art Generally, in an electronic circuit having a transistor circuit formed on a silicon substrate by a planar technique, for example, there is a portion which temporarily or periodically becomes a high impedance state in the process of its electrical operation. There are cases.

As an example thereof, for example, in a circuit that detects and holds only the peak of an input signal and the like, a portion having a high impedance is generated during a period when a level other than the peak is input.

The mechanism for generating the high impedance will be described in detail with reference to the output circuit shown in FIG. First, the output circuit amplifies a voltage signal Vin obtained by converting a signal charge accumulated in a linear sensor of the image pickup device into a charge-electric signal by, for example, a floating diffusion in an image pickup device such as a video camera. A main line L1 that outputs as an image pickup signal Vs from the first output terminal φ1 and a control that is branched from the main line L1 and obtains a proper signal output level as the image pickup signal Vs, that is, so-called auto gain control, are possible. And a branch line L2 to which the peak hold circuit 101 for connecting is connected.

The peak hold circuit 101 performs a signal processing operation of holding and outputting the peak value of the image pickup signal Vs read at a certain time or a predetermined period, and the peak value held by this circuit is output to the outside. The signal is supplied to the connected electronic iris control circuit, and the electronic iris control circuit controls the charge accumulation period (exposure period) at the time of the next image pickup based on the peak value to obtain an appropriate signal output level. Is something that can be done.

The output circuit uses the source follower circuit 102 at the first stage for amplifying the voltage signal Vin from the linear sensor with a predetermined gain (≈1), and the signal Va output from the first source follower 102. The peak hold circuit 101 that detects and holds the minimum peak level Vm, and the minimum peak level signal Vm that is held by the peak hold circuit 101 have a predetermined gain (≈).
The source follower circuit 103 which amplifies in 1) is connected and configured.

The source follower circuit 102 at the first stage is
Between the power supply line Lp (power supply voltage Vdd) and ground, NM
The driving transistor Tr1 and the load transistor Tr2, which are OS transistors, are connected in series and are connected by wiring so that the voltage signal Vin from the linear sensor is supplied to the gate electrode of the driving transistor Tr1. The output Va of the source follower circuit 102 is adapted to be taken out from the common contact a of both transistors Tr1 and Tr2.

The peak hold circuit 101 includes a diode D, which is a P-MOS transistor connected in the opposite direction to the signal output direction, to the output line of the source follower circuit 102 at the first stage, and between the anode of the diode D and ground. It is composed of a connected capacitor C.

The source follower circuit 103 at the subsequent stage is an N-MOS between the power supply line Lp (power supply voltage Vdd) and the ground.
A drive transistor Tr3 and a load transistor Tr4, which are transistors, are connected in series and are connected by wiring so that the gate potential of the drive transistor Tr3 is supplied with the anode potential of the diode D. The output Vout of the source follower circuit 103 is adapted to be taken out from the common contact b of both transistors Tr3 and Tr4.

The gate electrodes of the load transistors Tr2 and Tr4 in the source follower circuit 102 in the first stage and the source follower circuit 103 in the latter stage are connected by wiring so that the gate potential Vgg is supplied to them.

The signal processing operation of the peak hold circuit 101 will be briefly described below. The output potential Va of the source follower circuit 102 at the first stage, that is, the cathode potential Va of the diode D is lower than the anode potential Vm of the diode D. In this case, the diode D is turned on, and as a result,
The electric charge corresponding to the cathode potential Va is accumulated in the capacitor C.

On the other hand, when the cathode potential Va of the diode D is higher than the anode potential Vm of the diode D,
Since the diode D is turned off, the electric charge according to the anode potential Vm is still accumulated in the capacitor C. That is, the previously accumulated charge due to the low level cathode potential remains accumulated, and the minimum level of the voltage signal input up to the present stage is maintained.

By repeating the above series of operations temporarily or periodically, a change in the voltage across the capacitor C (a change in the peak level Vm held in the capacitor C) is amplified by the source follower circuit 103 in the subsequent stage. And output from the output terminal φout.

Then, the cathode potential Va of the diode D
During a period when is higher than the anode potential Vm, the gate electrode of the MOS transistor, which is a high input impedance part, is connected to the subsequent stage of the anode of the diode D, so that the charge stored in the capacitor C flows out ( The (transportation) route is substantially eliminated, and the capacitor connection point c of the output line exists as a high impedance portion.

[0015]

In the image pickup device, there is a period in which a high level signal is output as an image pickup signal for a long time, such as a charge accumulation period or a black level detection period.

When a high level signal is output for a long time, the potential Vm at the high impedance generating portion (capacitor connection point c of the output line) in the above output circuit.
However, there is a phenomenon in which it becomes higher depending on the usage conditions of the linear sensor.

That is, due to the influence of light leaking into the high impedance portion c due to the dark current in the diffusion layer of the transistor in the high impedance portion c, the use condition of the linear sensor, etc., as shown in FIG. The potential of the high impedance portion c increases with the passage of time.

When the potential rise in the high impedance portion is left for a long time, the potential Vout appearing at the output terminal φout of the output circuit is the potential Vdd designed as the rating.
If it is 1 or more, or less, there will be inconvenience in circuit operation, which may be unfavorable for ensuring reliability.

If the potential rise in the high impedance portion c is left for a long time, the potential rise will be saturated at a certain potential, but the output terminal φou of this output circuit.
If it is not desired to raise the potential Vout appearing at t to the reference potential Vdd1 designed as a rating or higher, it is treated as a defective product, which may be disadvantageous in terms of improving the yield of the imaging device.

In the above example, the potential rise in the high impedance portion c is taken as an example. However, depending on the circuit configuration, the potential of the high impedance portion drops in reverse due to the influence of the dark current or photoelectric conversion and the like. There is a possibility that a desired circuit operation may not be performed because the voltage becomes lower than the reference potential.

In the above example, the peak hold circuit incorporated in the output circuit of the image pickup device is shown. However, in other electronic circuits incorporated in mobile phones and various electronic devices, the potential of the high impedance generating portion is also increased. But,
For example, it may change due to temperature change and the like, and as a result, the potential taken out from the output terminal may be out of the rated potential.

The present invention has been made in view of the above problems, and an object thereof is to suppress the level of potential change at a high impedance generating portion to a predetermined potential and regulate the output potential within the rating. And an electronic circuit capable of achieving reliable circuit operation.

Another object of the present invention is to suppress the level of potential change at a high impedance generating portion in an image pickup signal output circuit formed on the same substrate to a predetermined potential, and to output the output of the output circuit. An object of the present invention is to provide a solid-state image sensor capable of regulating the level within the rating.

Another object of the present invention is to suppress the level of potential change at a high impedance generating portion in an output circuit formed on the same substrate together with an image pickup section and a transfer register to a predetermined potential, and to output the output. An object of the present invention is to provide an output circuit of a solid-state image pickup device that can regulate the output level from the circuit within the rating.

Another object of the present invention is, in an image pickup apparatus having a solid-state image pickup device mounted thereon, a potential at a high impedance generating portion of an output circuit formed on the same substrate together with an image pickup section and a transfer register of the solid-state image pickup device. (EN) An image pickup device capable of suppressing a change level to a predetermined potential, thereby restricting an output level from an output circuit of a solid-state image pickup device within a rating, and improving image pickup characteristics. It is in.

Another object of the present invention is to suppress the level of potential change at a high impedance generating portion of the output circuit formed on the same substrate together with the photoelectric conversion portion to a predetermined potential, whereby An object of the present invention is to provide a light receiving device capable of regulating the output level from the output circuit within the rating and improving the light receiving characteristics.

[0027]

An electronic circuit according to the present invention comprises a high impedance generating portion and a potential limiting circuit for limiting the potential at the portion to a predetermined potential. As a result, for example, the level of potential change in the high impedance generation part due to temperature change, light leakage, etc.
The potential limiting circuit limits the potential to a predetermined potential. As a result, the output potential of the electronic circuit can be regulated within the rating, and reliable circuit operation can be realized.

Next, the solid-state image pickup device according to the present invention has an image pickup section in which a large number of photoelectric conversion sections for converting incident light from a subject into signal charges of an amount corresponding to the quantity of light are arranged, and accumulated in the image pickup section. The transfer register for transferring the signal charge thus transferred to the output side and the output circuit for converting the signal charge transferred through the transfer register into an electric signal of a level corresponding to the amount of the electric charge and outputting it as an image pickup signal are the same. In the solid-state imaging device formed on the substrate, a potential limiting circuit for limiting the potential at the high impedance generating portion of the output circuit to a predetermined potential is connected to the high impedance generating portion.

As a result, first, the light from the subject is incident on the image pickup section, and is converted into a signal charge of an amount corresponding to the amount of incident light in each photoelectric conversion section arranged in the image pickup section. The signal charges accumulated in the image pickup unit are sequentially transferred to the output circuit side by the transfer operation of the transfer register.
The output circuit converts the signal charge transferred through the transfer register into an electric signal having a level corresponding to the amount of the charge and outputs the electric signal.

Normally, in a solid-state image pickup device, there are periods in which a high-level signal is output as an image pickup signal for a long time, such as a vertical blanking period, a horizontal blanking period, and a black level detection period.

As a circuit configuration of the output circuit, for example, when a high-level signal is output for a long period of time and a high impedance is generated in the output circuit, the potential at the high-impedance generating portion is the use condition of the solid-state image sensor. The phenomenon that it becomes higher due to such factors as above. That is, light leaks into the high impedance portion depending on the usage conditions of the solid-state imaging device, and as a result, the potential of the high impedance portion rises or falls due to photoelectric conversion in the diffusion layer of the transistor in the high impedance portion. Become.

If the potential rise or fall in the high impedance portion is left for a long time, the output level of the output circuit becomes higher or lower than the potential designed as the rating, which causes inconvenience in the circuit operation. There is a possibility that it is not preferable in terms of securing the property.

However, in the solid-state image pickup device according to the present invention, since the potential limiting circuit for limiting the potential in the high impedance generating portion of the output circuit to a predetermined potential is provided, the high impedance generating portion is Even if the potential rises or falls due to light leakage or the like, the level change is suppressed to a predetermined potential by the potential limiting circuit, and the output level of the output circuit can be regulated within the rating.

Next, the output circuit of the solid-state image pickup device according to the present invention comprises an image pickup section in which a large number of photoelectric conversion sections for converting incident light from a subject into signal charges of an amount corresponding to the light quantity are arranged.
It is formed on the same substrate together with a solid-state image pickup device having a transfer register for transferring the signal charge accumulated in the image pickup section to an output side, and the signal charge transferred through the transfer register is set to the charge amount. In an output circuit of a solid-state image sensor that converts an electric signal of a corresponding level and outputs the image signal as an image signal, in addition to the main line that is the output line of the image signal, a branch line that detects the peak level of the image signal is provided. A potential limiting circuit that limits the potential of the branch to a predetermined potential is connected to the high impedance generating portion of the branch line.

In this output circuit, as described above, since the potential limiting circuit for limiting the potential in the high impedance generating portion to the predetermined potential is provided, light leakage or the like occurs in the high impedance generating portion. Even if the potential rises or falls due to, the level change is suppressed to a predetermined potential by the potential limiting circuit, and the output level of the output circuit can be regulated within the rating.

Next, in the image pickup apparatus according to the present invention,
In an imaging device having a solid-state image sensor for focus control and a gain control means for performing control for obtaining an appropriate signal output level based on an output from the solid-state image sensor, the output of the solid-state image sensor for focus control As a circuit, a main line that outputs a signal containing a signal component corresponding to the amount of accumulated signal charge and a branch line that detects the peak level of the signal component are provided, and at least the high impedance generation part of the branch line has the part. It is configured by connecting a potential limiting circuit that limits the potential at 1 to a predetermined potential.

As a result, in the above-mentioned solid-state image pickup device for focus control, an output signal which is converted into a signal charge having an electric charge amount corresponding to the light amount of the incident light from the subject and which has a signal component of a level corresponding to the electric charge amount is output. The signal is output through the main line of the output circuit, and the peak level of the signal component is detected and output through the branch line.

These signal components and peak levels are supplied to the gain control means, and control is performed to obtain an appropriate signal output level. For example, the length of the charge accumulation period (exposure period) in the focus control solid-state imaging device is adjusted according to the peak level, and focus adjustment is performed according to the level of the signal component.

In this case, since the output circuit is provided with a potential limiting circuit for limiting the potential at the high impedance generating portion to a predetermined potential, the potential at the high impedance generating portion is caused by light leakage or the like. Even if rises or falls, the level change is suppressed to a predetermined potential by the potential limiting circuit.

That is, the level of potential change at the high impedance occurrence portion of the output circuit of the focus control solid-state image pickup device can be suppressed to a predetermined potential, whereby the output from the output circuit of the focus control solid-state image pickup device. The level can be regulated within the rating, and the control for obtaining an appropriate signal output level in the gain control means can be favorably performed. This leads to improvement of the imaging characteristics of the imaging device.

Next, the light receiving device according to the present invention includes a photoelectric conversion unit for converting incident light from a subject into a signal charge of an amount corresponding to the amount of the light, and an electrical conversion unit for converting the signal charge to a level corresponding to the amount of the charge. In a light-receiving device in which an output circuit for converting into a signal and outputting as a light-receiving signal is formed on the same substrate, a potential limiting circuit for limiting the potential at the high-impedance generating portion of the output circuit to a predetermined potential is provided. Connect and configure.

As a result, first, the light from the subject is incident on the photoelectric conversion unit, and is converted into signal charges in the photoelectric conversion unit in an amount according to the incident light amount. The signal charge obtained by the photoelectric conversion unit is converted into an electric signal having a level corresponding to the amount of the electric charge by the output circuit and is output.

In this case, if the potential rise or fall in the high impedance generation portion of the output circuit is left for a long time, the output level of the output circuit becomes higher or lower than the rated design potential, which is inconvenient for the circuit operation. May occur, which is not preferable for ensuring reliability.

However, since the light receiving device according to the present invention is provided with the potential limiting circuit for limiting the potential in the high impedance generating portion of the output circuit to a predetermined potential, the light receiving device in the high impedance generating portion is Even if the potential rises or falls due to the leakage of the voltage, the level change is suppressed to a predetermined potential by the potential limiting circuit, and the output level of the output circuit can be regulated within the rated value.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an electronic circuit according to the present invention, a solid-state image sensor according to the present invention (output circuit thereof), an image pickup apparatus according to the present invention, and a light receiving apparatus according to the present invention will be described below with reference to FIG. ~ It demonstrates one by one with reference to FIG.

[Electronic Circuit] First, some embodiments of the electronic circuit according to the present invention applied to a signal output circuit having an amplification stage will be described with reference to FIGS.

The basic configuration of the signal output circuit according to the first embodiment is, as shown in FIG. 1, a first stage source for amplifying the input signal Vin supplied to the input terminal φin with a predetermined gain (≈1). A follower circuit 1 and a peak hold circuit 2 for detecting and holding a minimum peak level Vm of a signal Va output from the source follower circuit 1 at the first stage.
And a source follower circuit 3 for amplifying the minimum peak level signal Vm held by the peak hold circuit 2 with a predetermined gain (≈1).

The source follower circuit 1 at the first stage has an N-MOS between the power supply line Lp (power supply voltage Vdd) and the ground.
The drive transistor Tr1 and the load transistor Tr2, which are transistors, are configured by being connected in series, and are connected by wiring so that the input signal Vin is supplied to the gate electrode of the drive transistor Tr1. The output Va of the source follower circuit 1 is adapted to be taken out from the common contact a of both transistors Tr1 and Tr2.

The peak hold circuit 2 includes a diode D1 formed of an enhancement type P-channel MOS transistor (hereinafter simply referred to as a P-MOS transistor) reversely connected to the output line of the source follower circuit 1 in the first stage, and the diode D1. And a capacitor Ca connected between the anode and the ground.

The source follower circuit 3 has a power supply line Lp.
An enhancement-type N-channel MOS transistor (hereinafter simply referred to as N-MOS) between (power supply voltage Vdd) and ground.
A drive transistor Tr3 (referred to as a transistor) and a load transistor Tr4 are connected in series, and are connected by wiring so that the gate potential of the drive transistor Tr3 is supplied with the anode potential of the diode D1. The output Vout of the source follower circuit 3 is taken out from the output terminal φout through the common contact b of both transistors Tr3 and Tr4.

Each load transistor T in the source follower circuit 1 in the first stage and the source follower circuit 3 in the latter stage.
The gate electrodes of r2 and Tr4 are connected by wiring so as to be supplied with the gate potential Vgg.

In the signal output circuit according to this embodiment, the output potential Vm of the peak hold circuit 2 is placed between the peak hold circuit 2 and the source follower circuit 3 in the subsequent stage.
Is connected to a potential limiting circuit (limiter circuit) 4 for limiting the voltage to a predetermined potential Vdd1.

The limiter circuit 4 has the predetermined potential V
Between the supply line of dd1 and the output line of the peak hold circuit 4, a diode D2 of a P-MOS transistor connected in the forward direction to the supply line of the predetermined potential Vdd1 is connected. The predetermined potential Vdd1 is determined at the time of designing, and refers to a potential at which the potential of the high impedance portion is not desired to be raised further.
Therefore, in the following description, the predetermined potential Vdd1 is described as the reference potential Vdd1.

Here, the signal processing operation of the signal output circuit according to the above embodiment will be described with reference to the signal waveform diagram of FIG.

First, the signal V input to the input terminal φin
When the voltage level of in becomes low and the output potential Va of the source follower circuit 1 at the first stage, that is, the cathode potential Va of the diode D1 becomes lower than the anode potential Vm of the diode D1, more accurately, the anode potential Vm-p. Channel type MOS transistor threshold (Vm-Vth)
When it becomes lower than the above, the diode D1 is turned on, and as a result, the cathode potential V is applied to the capacitor Ca.
The charge corresponding to a is accumulated. In this case, the anode potential Vm of the diode D1 is higher than the cathode potential Va of the diode D1 by the threshold value Vth.

On the other hand, the signal V input to the input terminal φin
When the level of in becomes high and the cathode potential Va of the diode D1 becomes higher than the anode potential Vm of the diode D1, the diode D1 is turned off, so that the capacitor Ca still responds to the anode potential Vm. The charge remains stored. That is, the previously stored charge due to the low level cathode potential Vm remains stored, and the minimum level of the input voltage signal is held until the present stage.

The above series of operations is repeated temporarily or periodically to change the voltage across the capacitor Ca (peak level V held by the capacitor Ca.
(change in m) is current-amplified by the source follower circuit 3 in the subsequent stage and output from the output terminal φout.

Then, the cathode potential V of the diode D1
During a period in which a is higher than the anode potential, the gate electrode of the MOS transistor, which is a high input impedance part, is connected to the subsequent stage of the anode of the diode D1, so that the charge stored in the capacitor Ca flows out ( The (transportation) route is substantially eliminated, and the capacitor connection point c of the output line exists as a high impedance portion.

When the high impedance state at the capacitor connection point c is left for a long period of time, normally, as shown in FIG. 2, due to a temperature change or a dark current in the diffusion layer of the transistor in the high impedance generation portion, as shown in FIG. The potential of the high impedance generating portion c rises with the lapse of time and eventually becomes saturated at a certain potential (see the broken line in FIG. 2).

However, in the present embodiment, since the limiter circuit 4 having the above configuration is connected between the peak hold circuit 2 and the source follower circuit 3 in the subsequent stage, the potential of the high impedance portion c is Reference potential V
When the potential becomes a little higher than dd1 (Vdd1 + Vth), the diode D2 formed by the P-MOS transistor that constitutes the limiter circuit 4 is turned on, whereby
The increase in the potential of the high impedance portion c is limited to a potential slightly higher than the reference potential Vdd1. The potential Vth indicates the threshold value of the P-MOS transistor.

Since the output line of the peak hold circuit 4 is connected to the source follower circuit 3 of N-MOS transistor at the subsequent stage, even if the potential of the high impedance portion c becomes the reference potential Vdd1 + the threshold value Vth. , The output terminal φout of the source follower circuit 3
From the potential of the high impedance part c to N-MO
A potential lowered by the threshold value of the S transistor appears. That is, the source follower circuit 3 in the subsequent stage has the threshold value Vth of the diode D2 that constitutes the limiter circuit 4.
It functions as a correction circuit that suppresses the increase in potential.

Therefore, P-M which constitutes the limiter circuit 4
N constituting the OS transistor and the source follower circuit 3
-By adjusting parameters such as the diffusion concentration of each MOS transistor and each channel width / channel length so that the threshold values of both transistors become substantially the same, the limiter circuit 4 causes the potential of the high impedance portion c to become the reference potential. Even if it can be limited only to Vdd1 + threshold value Vth, the output terminal φ of the source follower circuit 3 in the subsequent stage
The potential appearing from out is the reference potential Vdd designed by the rating.
Since it is 1 or less, there is no inconvenience in circuit operation, and reliability can be improved.

Next, a signal output circuit according to the second embodiment will be described with reference to FIGS. In addition,
Components corresponding to those in FIG. 1 are designated by the same reference numerals, and duplicate description thereof will be omitted.

As shown in FIG. 3, the signal output circuit according to the second embodiment shows an example in which a voltage follower circuit 11 is connected to the output line of the peak hold circuit 3 at the subsequent stage. Normally, the voltage follower circuit is
As shown in the block diagram of FIG. 5A, for example, a differential amplifier circuit 12 using a current mirror circuit, and the differential amplifier circuit 1
The output Vc of 2 is amplified by a predetermined gain and output terminal φou
This circuit is composed of a buffer circuit 13 for outputting from t, has a feedback system 14, and has a DC level of input and output of approximately the same and a gain of approximately 1. FIG. 5B shows a general circuit example in which the voltage follower circuit is composed of MOS transistors.

In the signal output circuit according to the second embodiment, the source follower circuit 14 of the P-MOS transistor is inserted and connected to the feedback system of the voltage follower circuit 11 to limit the feedback potential. Diode D that composes 4
The threshold value Vth of 2 is increased.

More specifically, the voltage follower circuit 11 of the signal output circuit according to the second embodiment.
Is a differential amplifier circuit 12 using the current mirror circuit 15.
And the output Vc of the differential amplifier circuit 12 is set to a predetermined gain (≈
The first source follower circuit 13 which is amplified in 1) and is output from the output terminal φout, and the output Vout of the first source follower circuit 13 is amplified by a predetermined gain (≈1) and the difference is obtained as the voltage signal Vd. A second source follower circuit 14 that feeds back to the dynamic amplifier circuit 12 is connected and configured.

The differential amplifier circuit 12 in the voltage follower circuit 11 has two P-MOs on the power supply line Lp.
A current mirror circuit 15 configured by connecting the drains of the S transistors Tr11 and Tr12 in common, and the current mirror circuit 15 is connected in series to the source of one P-MOS transistor Tr11 of the current mirror circuit 15 and has the above-mentioned peak at the gate electrode. A second source follower circuit is connected in series to the input side N-MOS transistor Tr13 to which the output Vm of the hold circuit 2 is supplied and the source of the other P-MOS transistor Tr12 of the current mirror circuit 15 and to the gate electrode. NMOS on the output side to which the output Vd of 14 is supplied
The transistor Tr14 and these NMOS transistors T
A constant current source 16 formed by an N-MOS transistor Tr15 between a common contact d of each emitter in r13 and Tr14 and ground.
And is configured. The output Vc of the differential amplifier circuit 12 is the other P-MOS of the current mirror circuit 15.
It is taken out from the connection point e between the transistor Tr12 and the output side N-MOS transistor Tr14.

The first source follower circuit 13 is constructed by connecting a drive transistor Tr21 and a load transistor Tr22, which are N-MOS transistors, in series between a power supply line Lp and ground, and the gate electrode of the drive transistor Tr21 has the above-mentioned difference. The wires are connected so that the output Vc of the dynamic amplifier circuit 12 is supplied. The output of the first source follower circuit 13 is taken out from the common contact f of both transistors Tr21 and Tr22 through the output terminal φout.

The second source follower circuit 14 is constructed by connecting a driving transistor Tr31 and a load transistor Tr32, which are P-MOS transistors, in series between the ground and the power supply line Lp, and the gate electrode of the driving transistor Tr31 is connected to the gate electrode of the first transistor. Output Vo of the source follower circuit 13 of No. 1
It is wired so that ut is supplied. This second
The output Vd of the source follower circuit 14 is wired from the common contact point g of the transistors Tr31 and Tr32 and is supplied to the gate electrode of the output side N-MOS transistor Tr14 in the differential amplifier circuit 12. There is.

The gate electrodes of the N-MOS transistor Tr15 forming the constant current source 16 of the differential amplifier circuit 12 and the load transistor Tr22 of the first source follower circuit 13 are connected to the load of the source follower circuit 1 of the first stage. The same gate potential (first gate potential) Vgg1 as the gate potential applied to the transistor Tr2 is supplied, and the gate electrode of the load transistor Tr32 in the second source follower circuit 14 has the second gate potential Vg.
Wiring is connected so that g2 is supplied.

Here, the signal processing operation of the signal output circuit according to the second embodiment, particularly the voltage follower circuit 11, will be explained. The high impedance state at the capacitor connection point c is left for a long time, and the high impedance state is left. When the potential Vm of the impedance portion c rises like a ramp signal, first,
The limiter circuit 4 limits the potential rise of the high impedance portion c to the reference potential Vdd1 + the threshold value Vth. At this time, the second source follower circuit 14 becomes P-
Since it is composed of MOS transistors,
The feedback potential Vout output from the source follower 13 is increased by the threshold value of the P-MOS transistor by the second source follower circuit 14.

In this case, P- which constitutes the limiter circuit 4
If the threshold values of the MOS transistor and the P-MOS transistor forming the second source follower circuit 14 are adjusted to be approximately the same by adjusting parameters such as diffusion concentration and channel width / channel length of each transistor, the difference is obtained. The potentials corresponding to the respective threshold values of the signals Vm and Vd supplied to both input sides of the dynamic amplifier circuit 12 are canceled, and the potential appearing at the output terminal φout can be lowered to the reference potential Vdd1.

That is, by connecting the voltage follower circuit 11 according to this embodiment, the potential Vout appearing at the output terminal φout can be limited to the rated reference potential Vdd1 or less, as shown in FIG. ,
The reliability can be improved without causing any inconvenience in circuit operation.

Next, a signal output circuit according to the third embodiment will be described with reference to FIG. The components corresponding to those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated.

In the signal output circuit according to the third embodiment, as shown in FIG. 6, the clamp circuit 5 is connected instead of the peak hold circuit 2 in the signal output circuit according to the first embodiment. It has a configuration.

Specifically, the clamp circuit 5 includes a coupling capacitor Cb connected to the output line of the source follower circuit 1 in the first stage, an output line derived from the coupling capacitor Cb, and a supply line of the reference potential Vdd1. And a switching circuit SW connected to. The switching circuit SW can be composed of, for example, an N-MOS transistor. In this case, the drain is connected to the supply line of the reference potential Vdd1, the source is connected to the output line derived from the coupling capacitor Cb, and the gate electrode is connected. The wiring is connected so that the switching control signal Sc is supplied to the.

To explain the signal processing operation of this signal output circuit, the DC component of the signal Va output from the source follower circuit 1 at the first stage is the coupling capacitor Cb of the clamp circuit 5.
And is extracted as a signal Vb that swings positively and negatively around the 0 level. Then, during a certain reference period of the signal Vb, the switching control signal Sc becomes high level, for example, and the switching circuit SW is turned on, so that the output level of the reference period becomes the reference potential Vdd1. Therefore, from the clamp circuit 5, the signal Vc swinging to the positive and negative sides with the reference potential Vdd1 as the center is taken out.

Then, when the switching circuit SW is in the off state, the connection point h with the output line of the switching circuit SW is in a high impedance state, and if this state is left for a long time, as in the case of the first embodiment. , The potential Vc of the high impedance portion h increases.

However, in the third embodiment, since the limiter circuit 4 is connected to the latter stage of the clamp circuit 5, the potential rise in the high impedance portion h is limited to the reference potential Vdd1 + threshold Vth. Then, the potential Vout that appears from the output terminal φout of the source follower circuit 3 in the subsequent stage becomes equal to or lower than the reference potential Vdd1 designed by the rating.

In the signal output circuit according to the third embodiment, an example in which the source follower circuit 3 by the N-MOS transistor is connected to the latter stage of the limiter circuit 4 is shown. However, instead of the source follower circuit 3, The voltage follower circuit 11 according to the second embodiment shown in FIG. 3 may be connected. Also in this case, the potential Vo appearing from the output terminal φout of the first source follower circuit 13
ut becomes the reference potential Vdd1 or less designed by the rating.

Next, a signal output circuit according to the fourth embodiment will be described with reference to FIG. It should be noted that the same reference numerals are given to those corresponding to those in FIG. 6, and the duplicate description thereof will be omitted.

As shown in FIG. 7, the signal output circuit according to the fourth embodiment has substantially the same structure as the signal output circuit according to the third embodiment shown in FIG. 5 is different from the limiter circuit 4 in that a correction circuit 6 for suppressing the potential Vc of the high impedance portion h to a reference potential Vdd1 or less is inserted and connected.

The correction circuit 6 is constructed by connecting a drive transistor Tr5 and a load transistor Tr6, which are P-MOS transistors, in series between the ground and the power supply line (power supply voltage Vdd), and is connected to the gate electrode of the drive transistor Tr5. The output line derived from the coupling capacitor Cb is connected. The output Vd of the correction circuit 6 is taken out from the common contact i of both transistors Tr5 and Tr6. In this case, the P-MOS transistor that constitutes the correction circuit 6 is adjusted so that its threshold value becomes substantially the same as the threshold value Vth of the P-MOS transistor that constitutes the limiter circuit 4. The gate electrode of the load transistor Tr6 in the correction circuit 6 is wired so that the second gate potential Vgg2 is supplied.

The signal processing operation of the correction circuit 6 will be described. Since the correction circuit 6 is composed of a source follower circuit composed of P-MOS transistors, its output potential Vd is higher than its input potential Vb by its threshold value. It increases by Vth. Therefore, when the potential of the high-impedance portion h rises to the reference potential Vdd1, the output potential Vd of the correction circuit 6 becomes the reference potential Vdd1 + the threshold value Vth, so that the limiter circuit 4 in the subsequent stage is turned on. Then
The output potential Vd of the correction circuit 6 will not be further increased. That is, the potential rise of the high impedance portion h is limited by the reference potential Vdd1.

As described above, in the signal output circuit according to the fourth embodiment, both the increase in the potential of the high impedance portion h and the increase in the potential appearing at the output terminal φout can be limited to the reference potential Vdd1.

In the example shown in FIG. 7, N is provided after the limiter circuit 4.
Although the example in which the source follower circuit 3 is connected by the -MOS transistor is shown, the voltage follower circuit 11 according to the second embodiment shown in FIG. 3 may be connected instead of the source follower circuit 3.

[Solid-State Image Sensor] Next, an example of an embodiment in which the solid-state image sensor according to the present invention is applied to a linear sensor having a transfer stage having a CCD structure (hereinafter, simply referred to as a linear sensor according to the embodiment) will be described. This will be described with reference to FIGS.

In the linear sensor according to this embodiment, as shown in FIG. 8, a large number of light receiving portions 21 for converting incident light from a subject into signal charges having a charge amount corresponding to the light amount and accumulating the signal charges are arranged in a line ( For example, a sensor row 22 arranged for 2000 pixels) and a transfer register 24 having a CCD structure for unidirectionally transferring the signal charge read from each light receiving portion 21 of the sensor row 22 through the read gate 23. It is configured to have.

The reading of the signal charge by the read gate 23 is performed by applying the gate pulse φROG. In addition, by applying transfer pulses φH1 and φH2 of two phases having different phases to the transfer electrodes formed of, for example, two layers of polycrystalline silicon formed on the transfer register 24, the signal charges on the transfer register 24 are unidirectionally applied. Will be transferred.

The output section 25 is provided at the final stage of the transfer register 24.
Is connected. The output unit 15 is a transfer register 2
The signal charge transferred from the final stage of 4 is converted into an electric signal (for example, voltage signal Vi), for example, floating.
The charge-electrical signal conversion unit 26 including a diffusion or a floating gate, and the signal charge after being converted into the voltage signal Vi by the charge-electrical signal conversion unit 26 are input to the reset pulse φRG. And a reset gate RG which is swept to the drain region D according to the above. A power supply voltage Vdd is applied to the drain region D through a power supply line Lp.

In the subsequent stage of the electric charge-electrical signal converter 26, the voltage signal V from the electric charge-electrical signal converter 26 is provided.
A buffer circuit 27 including a source follower circuit that amplifies the current i is formed.

The linear sensor according to this embodiment is constructed by connecting the signal output circuit 28 to the subsequent stage of the buffer circuit 27. The signal output circuit 28 is formed (on-chip) on the same substrate together with the sensor array 22, the read gate 23, the transfer register 24, and the output section 25.

Here, the processing operation of the linear sensor will be briefly described. First, during the charge accumulation period, signal charges corresponding to the incident light from the subject are accumulated in each light receiving portion 21 of the sensor array 22. At the time of charge reading after that,
By applying the gate pulse φROG to the read gate 23, the signal charge accumulated in the sensor array 22 is read out to the transfer register 24. Then, in the next scanning period, the transfer register 24 is supplied with the two-phase transfer pulses φH1 and φH2.
, The potential distribution under each transfer electrode sequentially changes, whereby the signal charges are sequentially transferred to the charge-electrical signal conversion unit 26 of the output unit 25 along the transfer register 24, and in this charge-electrical signal conversion unit 26. Voltage signal V
It is converted to i and supplied to the signal output circuit 28 via the buffer circuit 27 in the subsequent stage.

Here, some configuration examples of the signal output circuit 28 will be described. First, as shown in FIG. 9, the signal output circuit according to the first configuration example has the first configuration shown in FIG. Although it has almost the same configuration as the signal output circuit according to the embodiment, the output line of the source follower circuit 1 at the first stage is 2
It differs in that it is branched into books. Therefore, components corresponding to those in FIG. 1 are designated by the same reference numerals, and duplicate description thereof will be omitted.

Of the two output lines L1 and L2 derived from the first-stage source follower circuit 1, one output line (main line) L1 is connected to a first output terminal φ1 derived to the outside. , The voltage signal Vi input to the input terminal φin is the imaging signal Vs through the first output terminal φ1.
As in the first embodiment, the peak hold circuit 2 for detecting and holding the minimum peak level Vm of the voltage signal Vi is provided on the other output line (branch line) L2. Connected, and NM in the subsequent stage
A source follower circuit 3 including an OS transistor is connected. The output line of this source follower circuit 3 is
The second output terminal φ2 led to the outside is connected.

Therefore, the image signal Vs obtained by amplifying the voltage signal Vi from the linear sensor with a predetermined gain is output from the first output terminal φ1, and the linear sensor outputs from the second output terminal φ2. A signal indicating the minimum peak level of the voltage signal Vi (hereinafter, referred to as peak detection signal Vp) is output.

Normally, in the linear sensor, there is a period in which a high level signal is output as the voltage signal Vi for a long period of time such as an operation standby state, a charge accumulation period and a black level detection period. In this case, a phenomenon occurs in which the capacitor connection point c of the peak hold circuit 2 connected to the branch line L2 is in a high impedance state, and the potential Vm of the high impedance portion c becomes high due to the usage conditions of the linear sensor. That is, light leaks into the high impedance portion c depending on the usage conditions of the linear sensor, and as a result, the potential of the high impedance portion c increases due to photoelectric conversion in the diffusion layer of the transistor in the high impedance portion c. Become.

If the potential rise in the high impedance portion c is left for a long time, the output level of the peak detection signal Vp output from the second output terminal φ2 becomes equal to or higher than the reference potential Vdd1 designed as the rating, and the circuit This may cause inconvenience in operation and may be unfavorable for ensuring reliability.

However, in the first configuration example of the signal output circuit 28 in the linear sensor according to the present embodiment,
Since the limiter circuit 4 for limiting the potential Vm in the high impedance portion c to approximately the reference potential Vdd1 is connected to the subsequent stage of the peak hold circuit 2, the potential in the high impedance portion c is reduced due to light leakage or the like. , The potential rise is limited by the limiter circuit 4 to the reference potential Vdd1 + threshold value Vth, and the source follower circuit 3 by the N-MOS transistor is connected in the subsequent stage of the limiter circuit 4. Therefore, the potential Vp appearing at the second output terminal φ2 can be suppressed to the reference potential Vdd1 or less, and the reliability of the circuit operation of the linear sensor and the improvement of the yield of the linear sensor can be effectively achieved.

Next, a second configuration example of the signal output circuit 28 will be described with reference to FIG.
The signal output circuit 28 according to the configuration example has substantially the same configuration as the signal output circuit according to the second embodiment shown in FIG. 3 above, but like the first configuration example, the source follower circuit at the first stage is used. Two output lines of 1 (main line L1 and branch line L2)
It is different in that it is branched into.

Specifically, of the two output lines L1 and L2 derived from the source-follower circuit 1 in the first stage, one output line (main line) L1 has a first output terminal φ1 externally derived. Is connected so that the voltage signal Vi input to the input terminal φin is taken out as the image pickup signal Vs through the first output terminal φ1, and the other output line (branch line) L2 is connected to the first embodiment. Similar to the embodiment, the peak hold circuit 2 for detecting and holding the minimum peak level of the voltage signal Vi is connected, and the voltage follower circuit 11 according to the second embodiment is provided at the subsequent stage.
Is connected. The output line of the first source follower circuit 13 in the voltage follower circuit 11 is
The second output terminal φ2 led to the outside is connected.

In this second configuration example as well, similar to the first configuration example, the potential Vm in the high impedance portion c is provided substantially at the reference potential Vd in the subsequent stage of the peak hold circuit 2.
Since the limiter circuit 4 limiting to d1 is connected, even if the potential rises in the high impedance portion c due to light leakage or the like, the potential rise is caused by the limiter circuit 4 to be the reference potential Vdd1 + threshold. Since the limiter circuit 4 is connected to the voltage follower circuit 11 after the limiter circuit 4, the potential Vp appearing at the second output terminal φ2 can be suppressed to the reference potential Vdd1 or lower. You can
It is possible to effectively improve the reliability of the circuit operation of the linear sensor and improve the yield of the linear sensor.

Next, a third configuration example of the signal output circuit 28 will be described with reference to FIG.
The signal output circuit according to the configuration example has substantially the same configuration as that of the signal output circuit according to the first embodiment shown in FIG. 1, but similarly to the first configuration example, the source-follower circuit 1 of the first stage is used. The output line is divided into two lines (main line L1 and branch line L2).

The difference from the first configuration example is that
The clamp circuit 5, the limiter circuit 4, and the source follower circuit 3 according to the third embodiment shown in FIG. 6 are provided on the main line L1.
Are connected.

Voltage signal Vi input to input terminal φin
12, the waveform is a waveform in which the reset pulse φRG (potential Vrg) applied to the reset gate RG is added to the signal component Vsig from the charge-electrical signal conversion unit 26 in the output unit 25 by coupling. Have. The period between the output period Ts of the signal component Vsig and the output period Tc of the coupling component Vrg is the feedthrough period Tf.

Therefore, the main line L in the third configuration example is
1, the DC component of the signal output from the source follower circuit 1 at the first stage (in this case, the feedthrough component V
The signal f) is removed by the coupling capacitor Cb of the clamp circuit 5 and becomes the signal output Vb in which the feedthrough component is 0 level. Then, in the signal Vb output from the coupling capacitor Cb, the switching control signal Sc becomes, for example, at a high level in synchronization with the feedthrough period Tf, and the switching circuit SW is turned on, so that the output of the feedthrough period Tf is output. Level is reference potential V
It becomes dd1. Therefore, from this clamp circuit 5, the signal Va (≈) output from the source follower circuit 1 at the first stage is output.
Vi) is level-shifted, and the feedthrough component Vf
The signal Vc whose reference potential is Vdd1 is extracted.

In this case, the output level in the coupling period Tc becomes extremely high, but the level is limited by the limiter circuit 4 to the reference potential Vdd1 + threshold value Vth, and further, from the source follower circuit 3 in the subsequent stage, A signal Vp whose output level in the coupling period Tc is the reference potential Vdd1 which is the same as that of the feedthrough component is extracted. That is, since the unnecessary coupling component Vrg is removed from the first output terminal φ1 and a signal including only the necessary signal component Vsig is taken out as the image pickup signal Vs, the dynamic range of the image pickup signal Vs is increased. Therefore, the sensitivity can be effectively improved.

In the third configuration example, as described in the signal output circuit according to the sixth embodiment, when the switching circuit SW is in the off state, the output line of the switching circuit SW is The connection point h is in a high impedance state, and if this state is left for a long time, the potential Vc of the high impedance portion h will rise.

However, in the third configuration example, since the limiter circuit 4 is connected to the stage subsequent to the clamp circuit 5, the potential rise in the high impedance portion h is limited to the reference potential Vdd1 + the threshold value Vth. The potential Vs that appears from the output terminal (first output terminal φ1) of the source follower circuit 3 in the subsequent stage is equal to or lower than the reference potential Vdd1 designed by the rating.

Next, the fourth configuration example of the signal output circuit will be described with reference to FIG. 13. The signal output circuit according to the fourth configuration example is the same as the third configuration example shown in FIG. Although it has almost the same configuration as that of the output circuit according to the fourth embodiment, like the signal output circuit according to the fourth embodiment shown in FIG. 7, the correction circuit 6 is inserted and connected between the clamp circuit 5 and the limiter circuit 4. The difference is that

In this case, when the potential of the high impedance portion h rises to the reference potential Vdd1, the correction circuit 6
Since the output potential of is equal to the reference potential Vdd1 + the threshold value Vth, the limiter circuit 4 in the subsequent stage is turned on, and the output potential Vd of the correction circuit 6 is not further increased. That is, the potential rise of the high impedance portion h is limited by the reference potential Vdd1.

Therefore, in the output circuit according to the fourth configuration example, the increase in the potential of the high impedance portion h and the increase in the potential Vs appearing at the output terminal φ1 are both increased by the reference potential Vd.
It can be limited to d1.

The third configuration example shown in FIG. 12 and FIG.
In the fourth configuration example shown by 3, the source follower circuit 3 composed of the N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, but the source follower circuit 3 is replaced by the second embodiment. The voltage follower circuit 11 may be connected. Also in this case, the first
The potentials Vp and Vs appearing from the output terminals φ1 and φ2 of the source follower circuit 13 are the reference potential Vd designed by the rating
d1 or less.

[Imaging Device] Next, an example of an embodiment in which the imaging device according to the present invention is applied to a camera device using a linear sensor having a transfer stage of CCD structure for focus control (hereinafter, simply referred to as an embodiment) Such a camera device will be described with reference to FIG.

In the camera device according to this embodiment, as shown in the drawing, a linear sensor 32 for focus control is incorporated in a camera body 31 for picking up an image of a subject.
The linear sensor 32 has a gain control means 33 for controlling the signal output level of the linear sensor 32 to an appropriate level.

The camera body 31 has a zoom lens section 41 having a focus lens, a variator, a compensator, an erector, a relay lens and the like incorporated therein, and an object having an electronic shutter function and incident through the zoom lens section 41. The linear sensor 32 which converts the light from the light into a signal charge of an amount corresponding to the amount of light and outputs it as an electric signal, and various timing signals such as a read gate pulse and a transfer clock for driving the linear sensor 32 are generated. And a gain control means 33 for performing control for obtaining an appropriate signal output level based on the output from the linear sensor 32.

The linear sensor 32 has the same structure as that of the linear sensor according to the present embodiment shown in FIG. 8, and the output circuit thereof has the same structure as that shown in FIGS. 9 to 13. There is. Therefore, detailed description of these linear sensors 32 and their output circuits will be omitted.

The gain control means 33 is a linear sensor 32.
Exposure for adjusting the exposure time of the linear sensor 32 by controlling the timing of the timing generation circuit 42 based on the level (minimum peak level) of the peak detection signal Vp output from the second output terminal φ2 of the output circuit in FIG. The adjusting circuit 43 and the first output terminal φ of the output circuit
According to the focus shift this time, based on the focus error signal Sf from the arithmetic circuit 44, which calculates the focus shift based on the level of the image pickup signal Vs output from No. 1 and outputs it as the focus error signal Sf. And an automatic focus control circuit 46 for performing focus adjustment by moving the focus lens 45 in the optical axis direction.

The operation of the camera device according to the present embodiment when the first configuration example shown in FIG. 9 is used as the output circuit of the linear sensor 32 will now be described. Is converted into a signal charge having an electric charge amount corresponding to the amount of incident light from, and an imaging signal Vs having a signal component of a level corresponding to the electric charge amount is output through the main line L1 of the output circuit, and the imaging is performed through the branch line L2. The peak level of the signal Vs is detected and output as the peak detection signal Vp.

These image pickup signal Vs and peak detection signal Vp
Is supplied to the gain control means 33 in the subsequent stage, and control for obtaining an appropriate signal output level is performed. That is, the length of the exposure time in the linear sensor 32 is adjusted according to the level of the peak detection signal Vp, and the focus adjustment is performed according to the level of the image pickup signal Vs.

In the control of the exposure time in the exposure adjusting circuit 43, the peak detection signal V output from the output circuit is output.
If the level of p is higher than the reference level, the timing of the timing generation circuit 42 is controlled so that the exposure time in the linear sensor 32 is shortened, and the peak detection signal Vp is set.
If the level of is smaller than the reference level, the timing of the timing generation circuit 42 is controlled so that the exposure time of the linear sensor 32 becomes longer.

In this case, in the output circuit according to the first configuration example, as shown in FIG. 9, the potential Vm at the high impedance portion (capacitor connection point c) is substantially the reference potential after the peak hold circuit 2. Since the limiter circuit 4 for limiting the voltage to Vdd1 is connected, even if the potential Vm rises in the high impedance portion c due to light leakage or the like, the potential rise is caused by the limiter circuit 4 to be the reference potential Vdd1 +. Threshold value Vth
In addition, since the source follower circuit 3 including the N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, the second output terminal φ2
It is possible to suppress the potential Vp appearing at 1 below the reference potential Vdd1.

That is, the level of potential change in the high impedance portion c of the output circuit of the linear sensor 32 can be suppressed to substantially the reference potential Vdd1, and thus the peak output from the output circuit of the linear sensor 32. The output level of the detection signal Vp can be regulated within the rating, and the gain control means 33 can satisfactorily perform control for obtaining an appropriate signal output level.
This leads to improvement in the image pickup characteristics of the camera device.

Next, when the second configuration example shown in FIG. 10 is used as the output circuit of the linear sensor 32, the peak hold is the same as when the output circuit according to the first configuration example is used. High impedance part c in the latter stage of circuit 2
Limiter circuit 4 for limiting the potential Vm at the reference to almost the reference potential
Therefore, even if the potential Vm rises in the high impedance portion c due to light leakage or the like, the potential rise is limited by the limiter circuit 4 to the reference potential Vdd1 + the threshold value Vth. In addition, since the voltage follower circuit 11 is connected to the subsequent stage of the limiter circuit 4, the potential Vp appearing at the second output terminal φ2 is changed to the reference potential Vdd1.
The output level from the output circuit of the linear sensor 32 can be regulated within the rating by the following, and the control for obtaining an appropriate signal output level in the gain control means 33 can be favorably performed. Can be done.

Next, when the third configuration example shown in FIG. 11 and the fourth configuration example shown in FIG. 13 are used as the output circuit of the linear sensor 32, an unnecessary coupling from the second output terminal φ2. The component Vrg is removed and the required signal component V is obtained.
Since the signal including only sig is extracted as the image pickup signal Vs, the dynamic range of the image pickup signal Vs can be widened, and the sensitivity can be effectively improved.

Further, since the limiter circuit 4 is connected to the stage subsequent to the clamp circuit 5, the potential rise in the high impedance portion (connection point h with the output line of the switching circuit) is higher than that in the third configuration example. Limit to reference potential Vdd1 + threshold Vth, reference potential Vdd in the case of the fourth configuration example
The potentials Vs and Vp appearing at the output terminals φ1 and φ2 of the source follower circuit 3 in the subsequent stage are limited to 1 or less than the reference potential Vdd1 designed by the rating. In particular, in the fourth configuration example, it is possible to limit both the increase in the potentials of the high impedance portions c and h and the increase in the potentials Vs and Vp appearing at the output terminals φ1 and φ2 to the reference potential Vdd1.

As a result, the output level from the output circuit of the linear sensor 32 can be regulated within the rating, and the gain control means 33 can perform good control for obtaining an appropriate signal output level. . In addition, in the output circuits according to the third configuration example and the fourth configuration example, the source follower circuit 3 including the N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, but instead of the source follower circuit 3, Alternatively, the voltage follower circuit 11 according to the second embodiment shown in FIG. 3 may be connected. Also in this case, the potentials Vs and Vp appearing from the output terminals φ1 and φ2 of the first source follower circuit 13 are equal to or lower than the reference potential Vdd1 designed by the rating.

In the above embodiment, an example in which it is applied to the output circuit of the linear sensor 32 is shown, but in addition to this, in the final stage of the horizontal transfer register of the image sensor in which a large number of light receiving parts are arranged in a matrix. It can also be applied to a connected output circuit.

[Light-Receiving Device] Next, an embodiment example (hereinafter referred to as a remote sensor according to the embodiment) in which the light-receiving device according to the present invention is applied to a remote sensor on the receiving side used for optical communication, for example, is illustrated. This will be described with reference to FIGS. 15 and 16.

The remote sensor according to this embodiment is
As shown in FIG. 15, for example, a sensor unit 51 having a photodiode FD and an output signal V from the sensor unit 51
It has an output circuit 53 for amplifying in and supplying it to the decoder 52 at the subsequent stage.

The sensor section 51 includes a bias power source 54 (power source voltage −V) whose + pole is grounded, and the above-mentioned photodiode FD connected in the reverse direction with respect to the flow of the current i.
The photodiode FD has a load resistance R connected between the cathode and the ground. In this sensor unit 51, when light is incident from the outside,
The light detection signal Vin having a negative voltage level according to the amount of incident light is output.

The transmission system for outputting an optical signal to the remote sensor according to the present embodiment is adapted to optically modulate the code data to be sent and output it as an infrared optical signal. Example of optical signal for code data
6A. This optical signal has a signal form in which the output level of infrared rays is variable according to the logical values "0" and "1".

When the optical signal from the transmission system is incident on the remote sensor, the optical detection signal Vin corresponding to the optical output level of the optical signal is extracted as shown in FIG. 16B, for example. For example, when the optical signal of FIG. 16A is incident, for a logical value "1" having a high optical output level, an optical detection signal with a sharp drop in voltage level is output, and a logical value having a low optical output level is output. "0"
In response, a photodetection signal whose voltage level has been gradually reduced is output.

The output circuit 53 has the same structure as that of the signal output circuit according to the third embodiment shown in FIG. 6, and therefore the detailed description thereof is omitted, but the switching circuit SW is omitted.
The switching control signal Sc supplied to is in a signal form in which it becomes a high level in, for example, ¼ period at the beginning of each period in which the logical value of the input signal (light detection signal) Vin is determined. The 1/4 period is a period in which the optical output is always 0. Therefore, the signal Va output from the source follower circuit 1 at the first stage is always at the high level in the 1/4 period. From this, the switching circuit SW is turned on in the 1/4 period, so that the high level in the 1/4 period is clamped to the reference potential Vdd1.

Therefore, the output terminal φo of the output circuit 53 is
The signal Vout output from ut is the reference potential Vdd1 during the ¼ period when the optical signal indicates the logical value “1”.
Then, when the optical signal has a logical value “0” when the signal waveform sharply drops to the low level from the time when the 1/4 period has passed, the 1/4 period is set to the reference potential Vdd1.
The signal waveform has a signal level that gradually drops to a low level from the time when the quarter period has passed.

The decoder 52 uses the signal Vout output from the output circuit 53 from the ¼ period to the predetermined period τ.
Potential is detected, and the detected potential and the reference potential Vdd1
If the potential difference (detection voltage) with the reference voltage Vr is higher than the reference voltage Vr, that is, if the detection voltage is V _H , it is recognized as a logical value “1”, and if it is lower than the reference voltage Vr, the detection voltage is V _L. At this time, it has a circuit configuration in which it is recognized as logic "0" and is output as digital code information Dc.
The code information Dc from the decoder 52 is supplied to, for example, a system controller (not shown) and controlled according to the code information Dc.

In this case, the output circuit 53 is
As shown in FIG. 6, since the limiter circuit 4 is connected to the latter stage of the clamp circuit 5, the potential in the high impedance portion (connection point h with the output line of the switching circuit SW) is increased due to light leakage. Even if Vc rises, the potential rise is limited to the reference potential Vdd1 + threshold Vth by the limiter circuit 4, and the N-MOS is provided in the subsequent stage of the limiter circuit 4.
Since the source follower circuit 3 formed of a transistor is connected, the potential Vo appearing at the output terminal φout is
It is possible to suppress ut below the reference potential Vdd1.

As a result, the output level from the output circuit 53 can be regulated within the rating, and the decoder 5 in the subsequent stage can be controlled.
The conversion into the code information Dc in 2 can be performed well.

In the output circuit 53, the source follower circuit 3 formed of an N-MOS transistor is connected to the subsequent stage of the limiter circuit 4, but the source follower circuit 3 is replaced by the second embodiment shown in FIG. You may make it connect the voltage follower circuit 11 which concerns. Also in this case, the output terminal φou of the first source follower circuit 13
The potential Vout appearing from t is the reference potential V designed by the rating.
It becomes dd1 or less.

As another configuration, the circuit configuration shown in FIG. 6 is adopted as the output circuit 53, but the circuit configuration according to the fourth embodiment shown in FIG. 7 may be used. In this case, both the increase in the potential of the high impedance portion h and the increase in the potential Vout appearing at the output terminal φout can be limited to the reference potential Vdd1.

[0141]

As described above, according to the electronic circuit of the present invention, the high impedance generating portion is connected to the potential limiting circuit for limiting the potential of the portion to a predetermined potential, so that the high impedance is generated. The level of potential change at the generation site can be suppressed to a predetermined potential to regulate the output potential within the rating, and reliable circuit operation can be achieved.

Further, according to the solid-state image pickup device of the present invention, the output circuit for converting the signal charge into an electric signal having a level corresponding to the amount of the charge and outputting it as the image pickup signal is formed on the same substrate together with the image pickup section. In the solid-state image pickup device described above, the high-impedance generating portion of the output circuit is connected to the potential limiting circuit that limits the potential at the portion to a predetermined potential, so that in the output circuit formed on the same substrate. The level of potential change at the high impedance generation site can be suppressed to a predetermined potential, and the output level of the output circuit can be regulated within the rating.

Further, according to the output circuit of the solid-state image pickup device of the present invention, the signal charge of the image pickup section transferred through the transfer register is converted into an electric signal having a level corresponding to the amount of the electric charge and is output as an image pickup signal. In the output circuit of the solid-state image pickup device, in addition to the main line which is the output line of the image pickup signal, a branch line for detecting the peak level of the image pickup signal is provided, and a potential at that portion is set to a high impedance generation part of the branch line. Since the potential limiting circuit for limiting the potential is connected, it is possible to suppress the level of potential change at the high impedance generating portion in the output circuit formed on the same substrate together with the imaging unit and the transfer register to a predetermined potential. ,
The output level from the output circuit can be regulated within the rating.

Further, according to the image pickup apparatus of the present invention, the solid-state image pickup element for focus control and the gain control means for performing control for obtaining an appropriate signal output level based on the output from the solid-state image pickup element are provided. In the imaging device that has
As the output circuit of the solid-state imaging device for focus control, a main line that outputs a signal including a signal component corresponding to the amount of accumulated signal charge and a branch line that detects the peak level of the signal component are provided, and at least the above Since the high impedance generating portion of the branch line is connected to a potential limiting circuit that limits the potential of the portion to a predetermined potential, in an image pickup apparatus equipped with a solid-state image pickup element for focus control,
It is possible to suppress the level of potential change at a high impedance generating portion of the output circuit formed on the same substrate together with the image pickup unit and the transfer register in the solid-state image pickup device to a predetermined potential, and thereby the solid-state image pickup device for focus control. The output level from the output circuit can be regulated within the rating, and the imaging characteristics can be improved.

Further, according to the light receiving device of the present invention, the photoelectric conversion unit for converting the incident light from the subject into the signal charge of the amount corresponding to the light amount, and the signal charge of the level corresponding to the charge amount. In a light-receiving device in which an output circuit for converting into an electric signal and outputting as a light-receiving signal is formed on the same substrate, a high-impedance generating part of the output circuit is provided with a potential limiting circuit for limiting the potential of the part to a predetermined potential. Since it is configured to be connected, it is possible to suppress the level of potential change at the high impedance generation portion of the output circuit formed on the same substrate together with the photoelectric conversion unit to a predetermined potential, and thereby the output from the output circuit. The level can be regulated within the rating, and the light receiving characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a first embodiment in which an electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.

FIG. 2 is a waveform diagram showing a potential change at a high impedance portion and an output terminal in the signal output circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment example in which the electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.

FIG. 4 is a waveform chart showing potential changes at a high impedance portion and an output terminal in the signal output circuit according to the second embodiment.

5 is a diagram showing a general configuration of a voltage follower circuit, FIG. 5A is a block diagram, and FIG. 5B is a circuit diagram.

FIG. 6 is a circuit diagram showing a third embodiment example in which the electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.

FIG. 7 is a circuit diagram showing a fourth embodiment example in which the electronic circuit according to the present invention is applied to a signal output circuit having an amplification stage.

FIG. 8 is a configuration diagram showing an example of an embodiment (hereinafter, simply referred to as a linear sensor according to the embodiment) in which the solid-state imaging device according to the present invention is applied to a linear sensor having a transfer stage having a CCD structure.

FIG. 9 is a circuit diagram showing a first configuration example of the signal output circuit of the linear sensor according to the present embodiment.

FIG. 10 is a circuit diagram showing a second configuration example of the signal output circuit of the linear sensor according to the present embodiment.

FIG. 11 is a circuit diagram showing a third configuration example of the signal output circuit of the linear sensor according to the present embodiment.

FIG. 12 is a timing chart showing signal processing on the main line of a third configuration example of the signal output circuit of the linear sensor according to the present embodiment.

FIG. 13 is a circuit diagram showing a fourth configuration example of the signal output circuit of the linear sensor according to the present embodiment.

FIG. 14 is a configuration diagram showing an embodiment example in which the imaging device according to the present invention is applied to a camera device using a linear sensor having a transfer stage of CCD structure for focus control.

FIG. 15 is a configuration diagram showing an embodiment example (hereinafter, referred to as a remote sensor according to the embodiment) in which the light receiving device according to the present invention is applied to a remote sensor on the receiving side used for optical communication, for example.

FIG. 16 is a timing chart showing signal processing in the output circuit of the remote sensor according to the present embodiment.

FIG. 17 is a circuit diagram showing a configuration of a conventional signal output circuit in a linear sensor.

FIG. 18 is a waveform diagram showing potential changes at a high impedance portion and an output terminal of a signal output circuit according to a conventional example.

[Explanation of symbols]

1 first stage source follower circuit, 2 peak hold circuit, 3 latter stage source follower circuit, 4 limit circuit, 5 clamp circuit, D1, D2, D diode,
11 voltage follower circuit, 22 sensor array, 24
Transfer register, 26 charge-electrical signal converter, 28
Signal output circuit, L1 main line, L2 branch line, Lp power line, 31 camera body, 32 linear sensor, 33
Gain control means, 42 timing generation circuit, 43 exposure adjustment circuit, 44 arithmetic circuit, 45 focus lens,
46 autofocus control circuit, 51 sensor section, 5
2 decoders, 53 output circuits

Claims (60)

[Claims] 1. An electronic circuit, wherein a high impedance generating portion is connected to a potential limiting circuit for limiting the potential at the portion to a predetermined potential. 2. The potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential generating source and the high impedance generating portion.
Electronic circuit as described. 3. The electronic circuit according to claim 2, further comprising a correction circuit connected to suppress a potential increase of a threshold value of a diode which constitutes the potential limiting circuit in the high impedance generating portion. . 4. The electronic circuit according to claim 1, 2 or 3, wherein the high impedance generating portion is a capacitance connection point in a peak hold circuit connected to a front stage of the high input impedance portion. 5. The peak hold circuit is configured by a diode connected in a reverse direction with respect to a signal input direction and a capacitor connected between an anode of the diode and ground. 4. The electronic circuit according to 4. 6. A correction circuit that suppresses a potential increase corresponding to a threshold value of a diode that constitutes the potential limiting circuit in the high impedance generating portion is connected to a stage subsequent to the capacitance connection point. The electronic circuit according to claim 4 or 5. 7. The correction circuit is an n-channel type MOSF.
7. The electronic circuit according to claim 6, which is a source follower circuit by ET. 8. The electronic circuit according to claim 6, wherein the correction circuit is a source follower circuit including a p-channel MOSFET connected to a feedback system in the voltage follower circuit. 9. The electronic circuit according to claim 1, 2 or 3, wherein the high impedance generating portion is a selective supply point of a clamp voltage in a clamp circuit connected to a front stage of the high input impedance portion. . 10. The clamp circuit comprises a coupling capacitance connected to an input signal line and a switching circuit connected between an output side electrode of the coupling capacitance and a clamp voltage generation source. The electronic circuit according to claim 9. 11. A potential increase corresponding to the threshold value of the diode constituting the potential limiting circuit in the high impedance generating portion is suppressed between the selective supply point of the clamp voltage and the diode constituting the potential limiting circuit. 11. The electronic circuit according to claim 9, further comprising a correction circuit connected thereto. 12. The correction circuit is a p-channel type MOS.
12. The electronic circuit according to claim 11, wherein the electronic circuit is a source follower circuit including a FET. 13. An image pickup unit in which a large number of photoelectric conversion units for converting incident light from a subject into a signal charge corresponding to the amount of light are arranged, and the signal charge accumulated in the image pickup unit is transferred to an output side. In the solid-state image pickup device, the transfer register and the output circuit for converting the signal charge transferred through the transfer register into an electric signal having a level corresponding to the amount of the electric charge and outputting the electric signal as an image pickup signal are formed on the same substrate. A solid-state image pickup device, wherein a potential limiting circuit for limiting a potential at a high impedance generating portion of the output circuit to a predetermined potential is connected to the high impedance generating portion. 14. The output circuit has, in addition to a main line which is an output line of the image pickup signal, a branch line to which a peak detection circuit for detecting a peak level of the image pickup signal is connected, and a height of the branch line. 14. The solid-state imaging device according to claim 13, wherein the potential limiting circuit is connected to the impedance generating portion. 15. The solid-state image sensor according to claim 13, wherein the potential limiting circuit is connected to a high impedance generation portion of a main line which is an output line of the image pickup signal in the output circuit. . 16. The solid state according to claim 13, 14 or 15, wherein the potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential generating source and the high impedance generating portion. Image sensor. 17. The solid-state imaging device according to claim 16, further comprising a correction circuit connected to suppress a potential increase of a diode composing the potential limiting circuit in the high impedance generating portion by a threshold value. element. 18. The solid-state imaging device according to claim 14, wherein the high impedance generating portion of the branch line is a capacitance connection point in a peak hold circuit connected to a front stage of the high input impedance portion. element. 19. The peak hold circuit comprises a diode connected in a reverse direction to a signal input direction and a capacitor connected between the anode of the diode and ground. 18. The solid-state image sensor according to item 18. 20. A correction circuit for suppressing a potential increase of a threshold value of a diode constituting the potential limiting circuit in the high impedance generating portion is connected to a stage subsequent to the capacitance connection point. The solid-state image sensor according to claim 18 or 19. 21. The correction circuit is an n-channel type MOS.
21. The solid-state image sensor according to claim 20, which is a source follower circuit including an FET. 22. The solid-state imaging device according to claim 20, wherein the correction circuit is a source follower circuit including a p-channel type MOSFET connected to a feedback system in the voltage follower circuit. 23. The high impedance generating portion of the main line is a selective supply point of a clamp voltage in a clamp circuit connected to a front stage of the high input impedance portion, according to claim 15, 16 or 17. Solid-state image sensor. 24. The clamp circuit is composed of a coupling capacitance connected to an input signal line and a switching circuit connected between an output side electrode of the coupling capacitance and a clamp voltage generation source. The solid-state image sensor according to claim 23. 25. Between the selective supply point of the clamp voltage and the diode forming the potential limiting circuit, a potential increase of the threshold value of the diode forming the potential limiting circuit in the high impedance generating portion is suppressed. 25. The solid-state image sensor according to claim 23, further comprising a correction circuit connected thereto. 26. The correction circuit is a p-channel type MOS.
26. The solid-state image sensor according to claim 25, which is a source follower circuit including an FET. 27. An image pickup section in which a large number of photoelectric conversion sections for converting incident light from a subject into a signal charge of an amount corresponding to the light quantity are arranged, and the signal charge accumulated in the image pickup section is transferred to an output side. Which is formed on the same substrate together with a solid-state image sensor having a transfer register for converting the signal charge transferred through the transfer register into an electric signal having a level corresponding to the amount of the electric charge and outputs the electric signal as an image pickup signal. In the output circuit of the solid-state image pickup device, in addition to the main line which is the output line of the image pickup signal, a branch line for detecting the peak level of the image pickup signal is provided, and a potential at the high impedance generation part of the branch line is predetermined. An output circuit of a solid-state imaging device, to which a potential limiting circuit for limiting a potential is connected. 28. The output circuit of a solid-state image pickup device according to claim 27, wherein the potential limiting circuit is connected to a high impedance generating portion of a main line which is an output line of the image pickup signal. 29. The solid-state image pickup device according to claim 27, wherein the potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential generating source and the high impedance generating portion. Output circuit. 30. The solid-state imaging device according to claim 29, further comprising a correction circuit connected to suppress a potential increase of a diode composing the potential limiting circuit in the high impedance generating portion by a threshold value. Output circuit of the element. 31. The solid-state imaging device according to claim 27, wherein the high impedance generating portion of the branch line is a capacitance connection point in a peak hold circuit connected to a front stage of the high input impedance portion. Output circuit of the element. 32. The peak hold circuit comprises a diode connected in a reverse direction to a signal input direction and a capacitor connected between an anode of the diode and ground. 31. An output circuit of the solid-state image sensor according to item 31. 33. A correction circuit for suppressing a potential increase of a threshold voltage of a diode constituting the potential limiting circuit in the high impedance generating portion is connected to a stage subsequent to the capacitance connection point. The output circuit of the solid-state image sensor according to claim 31 or 32. 34. The correction circuit is an n-channel type MOS.
34. The output circuit of the solid-state image pickup device according to claim 33, which is a source follower circuit including an FET. 35. The output circuit of a solid-state image pickup device according to claim 33, wherein the correction circuit is a source follower circuit including a p-channel MOSFET connected to a feedback system in the voltage follower circuit. 36. The high impedance generating portion of the main line is a selective supply point of a clamp voltage in a clamp circuit connected to the preceding stage of the high input impedance portion, according to claim 28, 29 or 30. Output circuit of solid-state image sensor. 37. The clamp circuit is composed of a coupling capacitance connected to an input signal line and a switching circuit connected between an output side electrode of the coupling capacitance and a clamp voltage generation source. An output circuit of the solid-state image sensor according to claim 36. 38. Between the selective supply point of the clamp voltage and the diode forming the potential limiting circuit, a potential increase of the threshold value of the diode forming the potential limiting circuit in the high impedance generating portion is suppressed. 38. The output circuit of the solid-state image pickup device according to claim 36, wherein the correction circuit is connected. 39. The correction circuit is a p-channel type MOS.
39. The output circuit of the solid-state image pickup device according to claim 38, which is a source follower circuit including an FET. 40. A solid-state imaging device for focus control,
In an image pickup apparatus having a gain control means for performing control for obtaining an appropriate signal output level based on an output from the solid-state image pickup element, the output circuit of the solid-state image pickup element for focus control is configured to store accumulated signal charges. Has a main line that outputs a signal containing a signal component corresponding to the amount of electric charge of and a branch line that detects the peak level of the signal component. At least in the high impedance generation part of the branch line, the potential at that part is set to a predetermined potential. An imaging device, to which a potential limiting circuit for limiting is connected. 41. The gain control means performs focus adjustment based on at least a signal component from a main line in the output circuit, and a solid state for imaging based on a peak level from a branch line in the output circuit. 41. The image pickup apparatus according to claim 40, further comprising exposure adjusting means for adjusting an exposure time of the image pickup element. 42. The image pickup apparatus according to claim 40, wherein the potential limiting circuit is connected to a high impedance generation portion of a main line which is an output line of the image pickup signal. 43. The image pickup device according to claim 40, 41 or 42, wherein the potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential source and the high impedance generating portion. apparatus. 44. The image pickup device according to claim 43, further comprising a correction circuit connected to suppress a potential increase corresponding to a threshold value of a diode which constitutes the potential limiting circuit in the high impedance generating portion. . 45. The image pickup device according to claim 40, wherein the high impedance generating portion of the branch line is a capacitance connection point in a peak hold circuit connected to a front stage of the high input impedance portion. . 46. The peak hold circuit comprises a diode connected in a reverse direction to a signal input direction and a capacitor connected between an anode of the diode and ground. 45. The imaging device according to item 45. 47. A correction circuit for suppressing a potential increase of a threshold value of a diode constituting the potential limiting circuit in the high impedance generating portion is connected to a stage subsequent to the capacitance connection point. The imaging device according to claim 45 or 46. 48. The correction circuit is an n-channel type MOS.
The image pickup apparatus according to claim 47, wherein the image pickup apparatus is a source follower circuit including an FET. 49. The image pickup apparatus according to claim 47, wherein the correction circuit is a source follower circuit including a p-channel MOSFET connected to a feedback system in the voltage follower circuit. 50. The high impedance generating portion of the main line is a selective supply point of a clamp voltage in a clamp circuit connected to the preceding stage of the high input impedance portion, according to claim 42, 43 or 44. Imaging device. 51. The clamp circuit comprises a coupling capacitance connected to an input signal line, and a switching circuit connected between an output side electrode of the coupling capacitance and a clamp voltage generating source. The imaging device according to claim 50. 52. A potential increase of the threshold value of the diode forming the potential limiting circuit in the high impedance generating portion is suppressed between the selective supply point of the clamp voltage and the diode forming the potential limiting circuit. 52. The image pickup apparatus according to claim 50, further comprising a correction circuit connected to the image pickup device. 53. The correction circuit is a p-channel type MOS.
53. The image pickup device according to claim 52, which is a source follower circuit including an FET. 54. A photoelectric conversion unit that converts incident light from a subject into a signal charge of an amount corresponding to the amount of light, and a photoelectric conversion unit that converts the signal charge into an electric signal of a level corresponding to the amount of charge and outputs as a light reception signal. In the light receiving device in which the output circuit and the output circuit are formed on the same substrate, a potential limiting circuit for limiting the potential at the high impedance generating portion of the output circuit to a predetermined potential is connected. Light receiving device. 55. The light receiving device according to claim 54, wherein the potential limiting circuit is composed of a diode connected in a reverse direction between a predetermined potential generating source and the high impedance generating portion. 56. The light receiving device according to claim 55, further comprising a correction circuit connected to suppress a potential increase of a threshold voltage of a diode which constitutes the potential limiting circuit in the high impedance generating portion. . 57. The light receiving device according to claim 54, 55 or 56, wherein the high impedance generating portion is a selective supply point of a clamp voltage in a clamp circuit connected to a stage preceding the high input impedance portion. . 58. The clamp circuit is composed of a coupling capacitance connected to an input signal line and a switching circuit connected between an output side electrode of the coupling capacitance and a clamp voltage generation source. The light receiving device according to claim 57. 59. A potential increase corresponding to a threshold value of the diode forming the potential limiting circuit in the high impedance generating portion is suppressed between the selective supply point of the clamp voltage and the diode forming the potential limiting circuit. 59. The light-receiving device according to claim 57 or 58, further comprising a correction circuit that is connected. 60. The correction circuit is a p-channel type MOS.
The light receiving device according to claim 59, wherein the light receiving device is a source follower circuit including an FET.