JPH11234567A - Output circuit for ccd solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the frequency characteristics of the output circuit without increasing power consumption by a CCD solid-state image pickup element in the case that the output circuit is configured through cascade connection of a plurality of source follower circuits. SOLUTION: A source follower circuit at a final stage consists of a push-pull circuit consisting of an N-channel MOS transistor(TR) MN and a P-channel MOS TR Mp . Then the N-channel MOS transistor(TR) MN acts like a drive TR of the source follower at the rising state of an input signal and the P- channel MOS TR Mp acts like the drive TR of the source follower at the trailing state of the input signal. Thus, the source follower is actively driven even in the trailing state similarly to the case with the rising state and the trailing speed is quickened without increasing current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cascade connection of a plurality of source follower circuits for detecting signal charges transferred by a horizontal register of a CCD solid-state imaging device, converting the signal charges into a low output impedance, and outputting the output. C
The present invention relates to an output circuit of a CD solid-state imaging device.

[0002]

2. Description of the Related Art A CCD solid-state imaging device has a schematic configuration as shown in FIG. In the figure, reference numeral 1 denotes an image area (imaging area) in which light receiving elements are arranged vertically and horizontally, and a vertical transfer register is provided corresponding to each light receiving element vertical column. Reference numeral 2 denotes a horizontal transfer register, which transfers signal charges vertically transferred from each vertical transfer register in the horizontal direction. F
D is a floating diffusion region provided on the output end side of the horizontal transfer register 2, and is repeatedly reset to a predetermined reset potential, and thereafter, receives a signal charge from the horizontal transfer register 2 and repeats an operation of becoming a potential corresponding to the signal charge. . 3 is its output circuit (output buffer circuit)
FIG. 3 shows one such conventional example.

[0005] M1 is a MOS transistor having a gate connected to the floating diffusion region FD, forming a drive transistor of a source follower circuit in the first stage, and a drain connected to a power supply _VDD terminal. M2 is a MOS transistor forming a current supply means thereto, its gate receiving a constant voltage V _GG, drain MO
The source of the S transistor M1 is grounded via a resistor R _SS . M3 is a MOS transistor forming a drive transistor of a source follower circuit of the next stage, M4
Is a MOS transistor as a current supply means, M5 is a MOS transistor as a drive transistor of the last source follower circuit, and M6 is a MOS transistor as a current supply means. These transistors M1 to M6 are all N-channel MOS transistors, and drive MOS transistors M1, M3, M5
Is enhancement mode, load MOS transistor M
2, M4 and M6 are depletion modes.

As described above, the signal charges conveyed by the horizontal transfer register 2 of the solid-state image sensor are impedance-converted by an output circuit including a multi-stage source follower circuit and output to the outside (outside the solid-state image sensor). Incidentally, as a general method of extracting the output, FDA (floati
ng diffussion amplifier) and FGA (floating gate)
amplifier) method, but in any case, the potential of the floating diffusion region (FD) or the floating gate electrode, which becomes a potential corresponding to the amount of signal charge, is impedance-converted by an output circuit using a source follower circuit and output. And there is no change in that respect.

[0005]

By the way, the output circuit of the CCD solid-state imaging device is required to improve the frequency characteristics, and it is also required to realize this without increasing the current consumption. ing. This will be described in detail below.

The current HD (High Definition) CCD solid-state imaging device has a configuration provided with two horizontal transfer registers. The driving frequency is 37 MHz, and the frequency characteristics of the output circuit are set to, for example, about 150 MHz. ing.
The total current consumption of the output circuit of the CCD solid-state imaging device is, for example, about 10 mA. By the way, with the promotion of digitalization of television broadcasting, a demand for higher image quality has become stronger, and a plan for progressive scanning with 1080 effective scanning lines has been progressing. MTF (modul)
There is also a move to improve ation transfer function).

However, when the number of horizontal transfer registers is reduced to 1, the driving frequency becomes 74 MHz, which is twice 37 MHz.
As a result, the frequency characteristic required for the output circuit is about 300 MHz, which is twice the current frequency characteristic. On the other hand, if an attempt is made to respond only by increasing the current of the output circuit, the current consumption of the CCD solid-state imaging device becomes about 40 mA, which greatly deviates from the range actually allowed. There is no practicality at all. Therefore, the inventor of the present application has sought to improve the frequency characteristics to a required height without increasing current consumption by reviewing the circuit format of the CCD solid-state imaging device.
The following describes the search process.

First, what has governed the improvement of the frequency characteristics of the output circuit of the CCD solid-state imaging device has been considered. Here, the subject of consideration is limited to only the source follower circuit at the final stage where most of the current consumption is determined. This is because the first stage of the output circuit 3 and the next stage are CC like the last stage.
D It does not supply a corresponding output current to the outside of the solid-state imaging device, so that the output current can be extremely small. As a result, the rise time and the fall time can be easily shortened. Since the stage needs to send a considerable amount of output current to the outside, most of the current consumption is occupied by the final stage, and as a natural consequence, it is difficult to increase the speed. The reason is that the frequency characteristics are generally determined and the frequency characteristics are determined.

FIG. 4A shows a final-stage source follower circuit in a conventional CCD solid-state imaging device. In the figure, _CL is the load, and the load can thus be regarded as pure capacity. V _IN is an input signal, which may be considered as a substantially rectangular wave. Here, assuming that the input signal V _IN is at a low level and the circuit is in a steady state, the output in the steady state also becomes a low level. The current flowing at this time the load transistor M _L (corresponding to M6 of FIG. 3) and Io, the output voltage at this time is V _L. The operation when the input signal V _IN (which has been at the low level until now) is switched to the high level from the state shown in FIG. 4A is as shown in FIG. 4B.
At this time, the input voltage to the final stage is V _B + ΔV, where ΔV is the amplitude of the input signal V _IN . And drive MO
(Corresponding to M5 in Figure 3.) S transistor M _D since a state operating in the saturation region, the current I flowing therethrough M _D, the formula number 1 below.

[0010]

(Equation 1)

[0011] Here, Leff: effective gate length of the transistor M _D, W: gate width of the transistor M _D, dox: thickness of the gate oxide film, ox: SiO ₂ constituting the gate oxide film
, Neff: effective mobility of electrons.

Here, assuming that the rising time of the output voltage is t, C _L .DELTA.V = I _L .t.
(C _L · ΔV) I _L That is, the rise time
t is to inversely proportional to I _L. Therefore, in order to shorten the rise time t, the driving transistor M _D (W
Neff) / (Leff.dox), that is, gm should be increased.

Next, consider the case where the input signal V _IN falls from the high level to the low level. In the source follower circuit of the final stage, when the input signal V _IN is a circuit at a high level were in steady state, the output becomes a high level, the load MOS transistor M _L is operating as a constant current source, the when the current flowing through the load MOS transistor M _L also Io. Note that the output voltage at this time is V _H.

FIG. 4C shows the operation when the input signal V _IN switches from the high level to the low level in this state. Input voltage at this time is V _B + [Delta] V: Back from ([Delta] V amplitude of the input pulse) to V _B. V from the time the load capacitance C _L charge accumulated in becomes the form of a current I _L the load MOS transistor M discharged the output voltage through _L is V _H
L (V _L : output voltage at low level).
Then, the load MOS transistor M _L as described above is a constant current source, the current Io flowing therethrough is a certain value, the discharge current I _L is not possible to exceed the constant current Io . That is, I _L ≦ Io, and dVout
/ A dt ≦ Io / C _L.

[0015] Therefore, in order to shorten the fall time, current flowing in the load MOS transistor M _L in the final stage of the CCD solid-state imaging device, i.e., it is necessary to increase the current value Io of the constant current source, Then, naturally, CCD
This increases the current value of the solid-state imaging device.
In other words, according to the conventional output circuit as shown in FIG.
By increasing m, the frequency characteristics can be improved.
Is governed by the slew rate determined only by transistor M _L load current Io flowing in the capacitor C _L, the load capacitor C _L is constant, is impossible to improve the high speed and without increasing the current Io is there. At least, if the current constant current Io is kept within the allowable range (several dozen mA), it is impossible to obtain a frequency characteristic that can cope with the unification of the horizontal transfer register described above.

The present invention has been made in order to solve such a problem. In an output circuit of a CCD solid-state imaging device having a plurality of source follower circuits connected in cascade, a C
An object of the present invention is to improve frequency characteristics without increasing power consumption of a CD solid-state imaging device.

[0017]

According to a first aspect of the present invention, an output circuit of a CCD solid-state imaging device includes a source follower circuit at a final stage,
N-channel MOS transistor and P-channel MOS
It is characterized by comprising a push-pull circuit composed of a transistor.

Therefore, according to the output circuit of the CCD solid-state image pickup device of the first aspect, a MOS transistor which conventionally only functions as a current supply MOS transistor and only serves as a constant current source is constituted by a P-channel MOS transistor. An input signal (input signal to the source follower circuit at the last stage) is also applied to the P-channel MOS transistor. Therefore, when the input signal rises, the N-channel MOS which has conventionally served as a drive transistor is used. The transistor can function as a source follower drive transistor, and the P-channel MOS transistor can function as a source follower drive transistor at the time of falling. Therefore, high-speed operation at the time of falling can be enhanced by increasing gm of the P-channel MOS transistor without increasing current consumption.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An output circuit of a CCD solid-state image pickup device according to the present invention comprises a source follower circuit at the final stage constituted by a push-pull circuit comprising an N-channel MOS transistor and a P-channel MOS transistor. When both the N-channel MOS transistor and the P-channel MOS transistor are in the depletion mode, an idling current can flow in a steady state. Then, by allowing the idling current to flow, a decrease in the conversion efficiency can be prevented, and the frequency characteristics can be improved. However, flowing an idling current is not absolutely necessary. The present invention can also be implemented in a mode in which both transistors constituting the push-pull circuit are both set to the enhancement mode.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a circuit diagram showing a first embodiment 3a of an output circuit of a CCD solid-state imaging device according to the present invention. In the drawing,
M1 is an MO having a gate connected to the floating diffusion region FD (see FIG. 2) of the CCD solid-state imaging device.
The S transistor forms a driving transistor of the first source follower circuit, and the drain is connected to the power supply _VDD terminal. M2 is an MO for supplying current thereto.
An S transistor whose gate receives a constant voltage V _GG ,
The drain is connected to the source of the MOS transistor M1, and the source is grounded via the resistor R _SS . M3 is a MOS transistor as a drive transistor of a source follower circuit of the next stage, M4 is a MOS transistor as a current supply means, and its source is grounded via the resistor R _SS .
The gate receives a constant voltage V _GG . M1 to M4 are N-channel MOS transistors, drive MOS transistors M1 and M3 are in an enhancement mode,
The transistors M2 and M4 are depletion mode transistors.

M _N and M _P are MOs constituting the final stage of the output circuit.
S transistor, M _N is an N channel MOS transistor, M _P is a P channel MOS transistor,
Both of them receive the output signal of the second-stage source follower circuit composed of M3 and M4 and perform a push-pull operation. And
The MOS transistors M _N and M _P are both in a depletion mode so that an idling operation is performed, specifically, an idling current (for example, about 10 mA) flows in a steady state.

According to such an output circuit, when the input signal to the final stage has risen N-channel MOS transistor M _N is turned on, P-channel MOS transistor M _P is substantially off (transistor M _P is depression Since it is in the mode, it does not turn off completely and a little current flows.) Therefore, the N-channel MOS transistor M _N
Function as a driving transistor of the emitter follower circuit, and the output side (load capacitance) is charged through the transistor _MN . In this case, since the P-channel MOS transistor _MP is substantially cut off, the load capacitance can be charged faster than in the past, and the rising speed can be increased.

Next, when the input signal to the final stage falls, the N-channel MOS transistor M _N is substantially turned off (this transistor M _N is not completely turned off because this transistor M _N is in the depletion mode). MOS transistor M _P is turned on. Thus, this time is P-channel MOS transistor M _P is the last stage and functions as a driving transistor of a source follower circuit, the output side (load capacitance) is discharged through the transistor M _P. The on and so can be discharged through the transistor M _P becomes saturated, it is possible to increase the falling speed falling significantly than the conventional case.

In other words, in the prior art, the falling edge had to be discharged through a load MOS transistor (constantly a passive element since it does not perform an active operation) as a constant current means. According, so as to discharge through the P-channel MOS transistors M _P to the active operation, it is possible to make do with actively operate the falling operation not rising operation only. Therefore, it is possible to solve the problem that the falling speed in the related art cannot be increased without increasing the current.

Accordingly, the progressive scan of the HD-CCD type solid-state imaging device can be realized, and the HD-CC
In the D-type solid-state image sensor, a single horizontal transfer register can be used, and the frequency characteristics (especially, the power consumption can be reduced without increasing the power consumption or contributing to the reduction in power consumption of a normal CCD solid-state image sensor). (Falling speed) can be improved.

[0026] The present output circuit to flow the N-channel MOS transistors M _N of the last stage, the lowest one value at any time in the both depletion mode P-channel MOS transistors M _P idling current (e.g., 10 mA) The reason for doing so is described below. There are two reasons. The first is to prevent a decrease in conversion efficiency. FIG. 5 (A) is a circuit diagram showing a problem when MOS transistor M _N and M _P which constitute a push-pull circuit were both ene fan performs instruction mode. Here, it is assumed that the two MOS transistors M _N and M _P are both in the enhancement mode, and the threshold voltage Vth is 0.5 V.
It is assumed that the power supply voltage V _DD is 10 V and the input signal IN is a 2 V _PP rectangular wave. When the input signal is at low level (4
V), the N-channel MOS transistor M _N is turned off, the P-channel MOS transistor M _P is turned on, and the output signal is also at the low level, but the output level OUT is higher than the gate of the P-channel MOS transistor M _N. 4.5V higher by the threshold voltage (0.5V)
Becomes Conversely, when the input signal IN goes high (6 V), the N-channel MOS transistor M _N turns on,
The P-channel MOS transistor _MP is turned off, and the output signal is also at the high level, but the potential is 5.5 V lower than the gate of the transistor _MN by 0.5 V. Therefore, the amplitude of the input signal is 2V (6-4V), but the amplitude of the output signal is as small as 1V (5.5-4.5V). That is, the amplitude of the output signal is smaller than the amplitude of the input signal by the sum of the threshold voltages of the two transistors M _N and M _P. This is because there is a period during which the two transistors M _N and M _P are both off during the operation of the circuit. Therefore, if at least one of the transistors is always turned on, such a decrease in the conversion efficiency occurs.

Therefore, FIG.
As shown in (B), a bias circuit may be provided so that a voltage (for example, 1 V) higher than the threshold voltage Vth of the transistor is always applied between the gate and the source. However, in such a case, current also flows through the bias circuit, which causes an increase in current consumption.
In addition, the load on the source follower circuit in the preceding stage increases, and as a result, there is a problem that the frequency characteristic is reduced.
This leads to an increase in the number of elements. Therefore, it is not suitable as an output circuit for a CCD solid-state imaging device.

After all, it can be said that it is optimal to set both transistors M _N and M _P in the depletion mode so that a current of a certain value or more (for example, 10 mA) always flows at any time. .

The second reason that the idling current always flows at a minimum is to enhance the frequency characteristics of the source follower circuit. That is, the frequency characteristics of the source follower circuit shown schematically in FIG. 5 (C) fc (cutoff _{frequency), fc = gm / 2πC L (} C L: Load capacitance), and then the square root of the gm current I Since it is proportional, gm cannot be increased unless a certain amount of current I flows, and the frequency characteristic cannot be increased unless gm can be increased. For example, 400
In order to obtain a frequency characteristic of about MHz (cutoff frequency), it seems that it is necessary to flow a current of about 10 mA as an idling current.

However, if the various disadvantages described above are tolerated, the last two transistors MN and MP may both be in the enhancement mode.

[0031]

According to the output circuit of the CCD solid-state image pickup device of the first aspect, a P-channel MOS transistor is used as a MOS transistor which conventionally functions only as a current supply MOS transistor and serves only as a constant current source. Since the input signal is also applied to the P-channel MOS transistor, when the input signal rises, the N-channel MOS transistor, which has conventionally served as the driving transistor, performs the function of the source follower driving transistor. In addition, at the time of falling, the P-channel MOS transistor can function as a source follower driving transistor. Therefore, high-speed operation at the time of falling can be enhanced by increasing gm of the P-channel MOS transistor without increasing current consumption.

According to the output circuit of the CCD solid-state image pickup device of the present invention, both the N-channel MOS transistor and the P-channel MOS transistor, which constitute the final stage, are in the depletion mode. An idling current can be caused to flow, so that a decrease in conversion efficiency and a decrease in frequency characteristics do not occur.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an output circuit of a CCD solid-state imaging device according to the present invention.

FIG. 2 is a schematic configuration diagram of a solid-state imaging device (regardless of the conventional example and the present invention).

FIG. 3 is a circuit diagram showing a conventional example of an output circuit of a CCD solid-state imaging device.

FIGS. 4A to 4C are circuit diagrams for explaining the problems of the conventional example, in which FIG. 4A shows the final stage of the output circuit of the CCD solid-state imaging device, and FIG. (C) shows the operation when the input voltage falls.

FIGS. 5A to 5C are circuit diagrams illustrating the reason why an idling current flows.

[Explanation of symbols]

1 ... CCD solid-state imaging device, 3a ... Output circuit, M
N-channel MOS transistor forming the final stage of the _N ··· output circuit, P-channel MOS transistor forming the final stage of the M _P ··· output circuit.

Claims (2)

[Claims] 1. An output circuit of a CCD solid-state imaging device comprising a plurality of source follower circuits connected in cascade, wherein the last source follower circuit is constituted by a push-pull circuit comprising an N-channel MOS transistor and a P-channel MOS transistor. CC characterized by the following
Output circuit of D solid-state imaging device. 2. An N-channel MOS transistor and a P-channel MOS transistor constituting a final stage,
2. A depletion mode.
An output circuit of the CCD solid-state imaging device described in the above.