JP3832570B2 - Variable gain amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable gain amplifier capable of controlling gain used in an integrated circuit. In particular, the present invention relates to a variable gain amplifier used in an integrated circuit for digital satellite broadcast reception that requires a high input dynamic range.
[0002]
[Prior art]
A typical configuration of a conventional variable gain amplifier is shown in FIG. The conventional variable gain amplifier includes a variable gain amplifier circuit A1 and a variable gain amplifier circuit A2.
[0003]
First, the configuration of the variable gain amplifier circuit A1 will be described. Input signal V_in1Is connected to the base of an NPN-type input transistor Q11, and the input signal V_in2Is connected to the base of the NPN type input transistor Q12. The emitter of the input transistor Q11 and the emitter of the input transistor Q12 are connected via a resistor R7. The emitter of the input transistor Q11 is bias current I_CAnd the emitter of the input transistor Q12 is connected to the bias current I._CIs grounded via a constant current source 12 for supplying
[0004]
The emitter of the NPN transistor Q4 and the emitter of the NPN transistor Q5 are commonly connected to the collector of the input transistor Q11. Further, the emitter of the NPN transistor Q6 and the emitter of the NPN transistor Q7 are commonly connected to the collector of the transistor Q12.
[0005]
And constant voltage V_CCAre commonly connected to the collector of the transistor Q5 and the collector of the transistor Q6.
[0006]
Furthermore, the bias voltage V_biasAre connected in common to the base of the transistor Q4 and the base of the transistor Q7. Further, the control voltage V which is a reference control voltage_AGCAre connected in common to the base of the transistor Q5 and the base of the transistor Q6.
[0007]
Next, the configuration of the variable gain amplifier circuit A2 will be described. Input signal V_in1Is connected to the base of an NPN type input transistor Q10, and the input signal V_in2Is connected to the base of an NPN-type input transistor Q13. The emitter of the input transistor Q10 and the emitter of the input transistor Q13 are connected via a resistor R8. The emitter of the input transistor Q10 is bias current I_CAnd the emitter of the input transistor Q13 is connected to the bias current I._CIs grounded via a constant current source 13 for supplying
[0008]
The emitter of the NPN transistor Q2 and the emitter of the NPN transistor Q3 are commonly connected to the collector of the input transistor Q10. Further, the emitter of the NPN transistor Q8 and the emitter of the NPN transistor Q9 are commonly connected to the collector of the input transistor Q13.
[0009]
And constant voltage V_CCAre connected in common to one end of the output load resistor R5, the collector of the transistor Q3, the collector of the transistor Q8, and one end of the output load resistor R6. Further, the collector of the transistor Q2 is connected to the other end of the output load resistor R5, and the collector of the transistor Q9 is connected to the other end of the output load resistor R6.
[0010]
Furthermore, the bias voltage V_biasAre commonly connected to the base of the transistor Q2 and the base of the transistor Q9. Control voltage V_AGCAre connected in common to the base of the transistor Q3 and the base of the transistor Q8 via a resistor R3. The connection point between the resistor R3 and the transistors Q3 and Q8 is grounded via the resistor R4.
[0011]
The variable gain amplifier circuits A1 and A2 having such a configuration are connected in parallel. That is, the collector of the transistor Q2 and the collector of the transistor Q4 are connected to the output signal V._out1Are connected in common to the output terminal of the transistor Q7, the collector of the transistor Q7 and the collector of the transistor Q9 are connected to the output signal V_out2Is connected in common to the terminal that outputs.
[0012]
In the variable gain amplifiers A1 and A2, the noise figure characteristic and the intermodulation distortion characteristic are in a trade-off relationship. Therefore, the variable gain amplifier circuit A1 is a variable gain amplifier circuit with good noise figure characteristics, and the variable gain amplifier circuit A2 is a variable gain amplifier circuit with good intermodulation distortion characteristics.
[0013]
Next, the operation of the conventional variable gain amplifier shown in FIG. 7 will be described. Input signal V_in1And V_in2When the level is small, the control voltage V_AGCAnd the base potentials of the transistors Q2, Q4, Q7, and Q9 are made higher than the base potentials of the transistors Q3, Q5, Q6, and Q8. As a result, almost no current flows through the transistors Q3, Q5, Q6, and Q8, and most of the collector current of the input transistor flows through the transistors Q2, Q4, Q7, and Q9, so that a large current flows through the output load resistors R5 and R6. The gain of the variable gain amplifier increases.
[0014]
On the other hand, the input signal V_in1And V_in2When the level is large, the control voltage V_AGCTo increase the base potential of the transistors Q2, Q4, Q7, and Q9 with respect to the base potential of the transistors Q3, Q5, Q6, and Q8. Then, most of the collector current of the input transistor flows through the transistors Q3, Q5, Q6, and Q8, and almost no current flows through the transistors Q2, Q4, Q7, and Q9, so that the current flowing through the output load resistors R5 and R6 The gain of the variable gain amplifier is reduced.
[0015]
In addition, the bases of transistors Q5 and Q6Control voltageV_AGCIs applied, and the control voltage V is applied to the bases of the transistors Q3 and Q8._AGCSince the partial pressure is applied, the control voltage V at which the damping operation starts_AGCAre the variable gain amplifier circuit A1 and the variable gain amplifier circuit A.2And different. Variable gain amplifier circuitAV at which 1 starts gain attenuation operation_AGCSet the voltage threshold to V_B1, Variable gain amplifier circuitA2 starts gain attenuation operation_AGCSet the voltage threshold to V_B2(V_B1<V_B2). V_B1And V_B2Is a potential difference between both ends of the resistor R3.
[0016]
Since the variable gain amplifier circuit A1 and the variable gain amplifier circuit A2 are connected in parallel, the gain G of the conventional variable gain amplifier is_totalIs the gain G of the variable gain amplifier circuit A1._A1And the gain G of the variable gain amplifier circuit A2._A2And the total. Therefore, the control voltage V_AGCOf conventional variable gain amplifier with respect to_totalThe characteristics are as shown in FIG. In the case where the level of the input signal is low, that is, the control voltage V_AGCIs small, the gain G of the variable gain amplifier circuit A1_A1In the region where the input signal level is high, that is, the control voltage V_AGCIs large, the gain G of the variable gain amplifier circuit A2_A2Becomes dominant, so that the intermodulation distortion characteristics are improved.
[0017]
[Problems to be solved by the invention]
However, the conventional variable gain amplifier has the following two problems. The first problem is that the intermodulation distortion characteristics deteriorate when a high-frequency signal is input, and the second problem is that the voltage drop due to the output load resistance increases as the number of variable gain amplifier circuits connected in parallel increases. .
[0018]
The reason why the first problem occurs, that is, the reason why the intermodulation distortion characteristic deteriorates when a high-frequency signal is input will be described.
[0019]
In the conventional variable gain amplifier shown in FIG._AGCIs the threshold value V at which the attenuation operation of the variable gain amplifier circuit A1 starts._B1Is larger, the current flowing through the transistors Q4 and Q7 decreases, and the gain of the variable gain amplifier circuit A1 is attenuated. However, the constant current sources 11 and 12_AGCConstant bias current I regardless of the value of_CTherefore, the signal amplified by the input transistor Q11 is input to the emitter of the transistor Q4, and the signal amplified by the input transistor Q12 is input to the emitter of the transistor Q7.
[0020]
When a high-frequency signal is input, the signal amplified by the input transistor Q11 leaks to the output load output load resistor R5 via the parasitic capacitance between the emitter and collector of the transistor Q4, and the signal amplified by the input transistor Q12 becomes the emitter- It leaks to the output load output load resistor R6 through the parasitic capacitance between the collectors.
[0021]
Therefore, when the high frequency signal is input, the control voltage V_AGCEven if the gain is increased, the gain attenuation of the variable gain amplifier circuit A1 is saturated. As a result, the control voltage V_AGCIn a large range, the gain difference D between the variable gain amplifier circuit A1 and the variable gain amplifier circuit A2 becomes small. Note that the gain attenuation of the variable gain amplifier circuit A2 is saturated when a high frequency signal is input, but the gain attenuation of the variable gain amplifier circuit A2 is not saturated because there is almost no gain at the time of saturation.
[0022]
It will be described that the intermodulation distortion characteristics deteriorate as the gain difference D decreases. The total input / output characteristics of the variable gain amplifier circuit A1, the variable gain amplifier circuit A2, and the variable gain amplifier are shown in FIG. A straight line (1) _1 indicates input / output characteristics of the fundamental wave component in the variable gain amplifier circuit A1, a straight line (1) _3 indicates input / output characteristics of the third harmonic component in the variable gain amplifier circuit A1, and a straight line (2) _1 indicates The input / output characteristics of the fundamental wave component in the variable gain amplifier circuit A2, the straight line (2) _3 is the input / output characteristics of the third harmonic component in the variable gain amplifier circuit A2, and the straight line t_1 is the fundamental wave component in the total variable gain amplifier. The input / output characteristics and the straight line t_3 indicate the input / output characteristics of the third harmonic component in the total variable gain amplifier. In the graph of FIG. 10, the horizontal axis indicates the input level and the vertical axis indicates the output level in dB.
[0023]
The input level at which the output level of the fundamental wave component and the output level of the third harmonic component virtually match each other is called an input intercept point (IIP3). The higher this value, the better the intermodulation distortion characteristics. The input intercept points when the input signal level in the variable gain amplifier circuit A1, variable gain amplifier circuit A2, and variable gain amplifier total is p are set as IIP3_1 (p), IIP3_2 (p), and IIP3_total (p), respectively. Further, the output level differences between the third harmonic component and the fundamental component when the input signal level is p in the variable gain amplifier circuit A1, variable gain amplifier circuit A2, and variable gain amplifier total are IM3_1 (p) and IM3_2, respectively. (p) and IM3_total (p).
[0024]
From the relationship that the slope of the straight line (1) _1 is 1 and the slope of the straight line (1) _3 is 3, from FIG.
IIP3_1 (p) = p + IM3_1 (p) / 2 (1)
Is required. Further, from FIG. 10, the relationship that the slope of the straight line t_1 is 1 and the slope of the straight line t_3 is 3,
IIP3_total (p) = p + [D + [IM3_1 (p)]] / 2 (2)
Is required. Therefore, IIP3_total (p) can be calculated from formulas (1) and (2).
IIP3_total (p) = IIP3_1 (p) + D / 2 (3)
It can be expressed as.
[0025]
From equation (3), it can be seen that in order to increase the total input intercept point IIP3 of the variable gain amplifier, that is, to improve the intermodulation distortion characteristic, the gain difference D must be increased. However, as described above, in the conventional variable gain amplifier shown in FIG. 7, when the input signal level becomes large at the time of high frequency input, the gain difference D cannot be made large, so that the intermodulation distortion characteristic is deteriorated.
[0026]
Next, the reason why the second problem occurs, that is, the reason why the voltage drop due to the output load resistance increases as the number of variable gain amplifier circuits connected in parallel increases will be described.
[0027]
Control voltage V_AGCIn order to make the gain characteristic curve of the variable gain amplifier a smooth curve, a configuration in which a large number (n) of variable gain amplifier circuits are connected in parallel as shown in FIG. In FIG. 11, the same parts as those in FIG. The variable gain amplifier circuits A3 to An have the same configuration as the variable gain amplifier circuit A1.
[0028]
Since the variable gain amplifier of FIG. 11 has an n-fold current flowing through the output load resistors R5 and R6 as compared with a single variable gain amplifier circuit, the voltage drop at the output load resistors R5 and R6 is also n times. Become. Therefore, the bias current I output from the constant current source or the resistance value of the output load resistor is reduced._COtherwise, the transistor in the variable gain amplifier may saturate and not operate. However, since the amplitude of the output signal is the product of the resistance values of the output load resistors R5 and R6 and the alternating current value of the signal, the gain of the variable gain amplifier is reduced when the resistance values of the output load resistors R5 and R6 are reduced. End up. Also, the bias current I output from the constant current source_CDecreasing the value will reduce the input dynamic range.
[0029]
In view of the above problems, an object of the present invention is to provide a variable gain amplifier having good intermodulation distortion characteristics even when a high-frequency signal is input. Another object of the present invention is to provide a variable gain amplifier in which the voltage drop due to the output load resistance does not increase even if the number of variable gain amplifier circuits connected in parallel is increased.
[0030]
[Means for Solving the Problems]
  In order to achieve the above object, in a variable gain amplifier according to the present invention, a first transistor and a second transistor to which a differential input voltage is applied between bases, and the first transistor and the second transistor are applied. A first differential amplifier circuit having a current source that outputs a bias current to supply current to the first transistor, and a third transistor and a fourth transistor having an emitter commonly connected to the collector of the first transistor. And the signal amplified by the first transistor according to the difference between the first control voltage applied to the base of the third transistor and the bias voltage applied to the base of the fourth transistor. A second differential amplifier circuit that attenuates and outputs, a fifth transistor having an emitter commonly connected to the collector of the second transistor, and a second transistor And the second transistor according to a difference between the first control voltage applied to the base of the fifth transistor and the bias voltage applied to the base of the sixth transistor. A plurality of variable gain amplifier circuits connected in parallel to each other, and the first control voltage from an externally input reference control voltage. Voltage shift means for generating each variable gain amplifier circuit, and current control means for variably controlling the bias current value for each variable gain amplifier circuit.The current control means generates from the reference control voltage a second control voltage that is shifted by a predetermined voltage with respect to the first control voltage; and the predetermined voltage with respect to the bias voltage. A bias voltage shift means for generating a second bias voltage shifted from the bias voltage by a voltage corresponding to the second voltage, and a value of the bias current according to a difference between the plurality of second control voltages and the second bias voltage. Control means for variably controlling each variable gain amplifier circuitLike that.
[0032]
The second control voltage may be smaller than the reference control voltage. The control voltage shift means may include a plurality of impedance elements connected in series, and a voltage at each connection point of the impedance elements may be used as the second control voltage. Furthermore, the impedance element may be a resistor.
[0033]
Also, the abovecontrolA voltage shift means converts the reference control voltage from an analog value into a digital value, and digitally calculates the reference control voltage of the digital value output from the A / D conversion means to It is good also as a structure provided with the calculating means which produces | generates the said 2nd control voltage, and the D / A conversion means which converts the said 2nd control voltage output from the said calculating means from a digital value to an analog value.
[0035]
Further, the calculation means may perform digital calculation by time division processing. Further, the D / A conversion means may perform conversion by time division processing.
[0036]
The current control means may set the value of the bias current in the variable amplifier circuit to zero according to the reference control voltage. Further, the variable gain amplifier circuit that operates is switched according to the reference control voltage, and when the variable gain amplifier that operates is switched, the variable gain amplifier circuit that ends the operation by switching and the operation that starts by switching is started. A range of the reference control voltage that operates together with the variable gain amplifier circuit may be provided.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings. The configuration of the variable gain amplifier according to the first embodiment of the present invention is shown in FIG. In addition, the same code | symbol is attached | subjected to the part same as FIG. 7, and description is abbreviate | omitted.
[0038]
In the variable gain amplifier of the first embodiment, the current source included in the variable gain amplifier circuit A1 is composed of the transistors Q19, Q20, and Q23, and the bias current I_A1Is a current mirror circuit. That is, instead of the constant current sources 11 and 12 of FIG. 7, an NPN transistor Q19 whose collector is connected to the emitter of the transistor Q11, an NPN transistor Q20 whose collector is connected to the emitter of the transistor Q12, An NPN transistor Q23 having a base and a collector connected in common is provided at the base of Q20. The emitters of the transistors Q19, Q20, and Q23 are grounded.
[0039]
The variable gain amplifier according to the first embodiment includes the differential amplifier circuit 1 that controls the collector current of the transistor Q23. The differential amplifier circuit 1 includes a PNP transistor Q16 and a PNP transistor Q17. The emitter of transistor Q16 and the emitter of transistor Q17 are connected in common and are connected to the collector of PNP transistor Q25. The collector of transistor Q16 is grounded, and the collector of transistor Q17 is connected to the collector and base of transistor Q23.
[0040]
Further, in the variable gain amplifier of the first embodiment, the current source included in the variable gain amplifier circuit A2 is composed of transistors Q18, Q21, and Q22, and the bias current I_A2Is a current mirror circuit. That is, instead of the constant current sources 10 and 13 of FIG. 7, an NPN transistor Q18 whose collector is connected to the emitter of the transistor Q10, an NPN transistor Q21 whose collector is connected to the emitter of the transistor Q13, An NPN transistor Q22 having a base and a collector connected in common is provided at the base of Q21. The emitters of the transistors Q18, Q21, and Q22 are grounded.
[0041]
The variable gain amplifier according to the first embodiment includes the differential amplifier circuit 2 that controls the collector current of the transistor Q22. The differential amplifier circuit 2 includes a PNP transistor Q14 and a PNP transistor Q15. The emitter of transistor Q14 and the emitter of transistor Q15 are connected in common and connected to the collector of PNP transistor Q24. The collector of the transistor 15 is grounded, and the collector of the transistor Q14 is connected to the collector and base of the transistor Q22.
[0042]
Furthermore, the variable gain amplifier of the first embodiment includes a current mirror circuit that supplies a constant current to the differential amplifier circuits 1 and 2. This current mirror circuit includes transistors Q24, Q25, and Q26. Constant voltage V_CCAre connected in common to the bases and collectors of the transistors Q24, Q25, and Q26. The collector of the transistor Q26 is grounded via the constant current source 3.
[0043]
The bases of the transistors Q14 and Q16 are connected to the emitter of the NPN transistor Q27. The emitter of transistor Q27 is grounded through resistor R10. The base and collector of the transistor Q27 are connected in common, and the constant voltage V is supplied via the bases of the transistors Q2, Q4, Q7, and Q9 and the resistor R9._CCConnected to the supplied terminal
[0044]
The base of the transistor Q15 is connected to one end of the resistor R1, and the base of the transistor Q17 is connected to the other end of the resistor R1. One end of the resistor R1 is connected to the emitter of the NPN transistor Q1, and the other end of the resistor R1 is grounded via the resistor R2. The base and collector of the transistor Q1 are connected in common and the control voltage V_AGCIs connected to the terminal to which is supplied.
[0045]
Next, the operation of the variable gain amplifier according to the first embodiment having such a configuration will be described. The base potential of the transistors Q2, Q4, Q7, and Q9 is V_bias1, The base potential of the transistors Q14 and Q16 is V_bias2far. V_bias1And V_bias2Is a potential difference corresponding to the base-emitter voltage of the transistor Q27. On the other hand, the potential difference between the base potentials of the transistors Q5 and Q6 and the base potential of the transistor Q15 is the base-emitter voltage of the transistor Q1. Therefore, if the resistance values of the resistor R1 and the resistor R3, and the resistor R2 and the resistor R4 are equal, the differential amplifier circuit composed of the transistors Q4 and Q5 and the differential amplifier circuit composed of the transistors Q6 and Q7 start control of attenuation. Voltage V_AGCIs a control voltage V at which a bias current starts flowing in the variable gain amplifier circuit A2 by the differential amplifier 2_AGCThe control voltage V at which the differential amplifier circuit composed of the transistors Q2 and Q3 and the differential amplifier circuit composed of the transistors Q8 and Q9 start the attenuating operation._AGCThe control voltage V is such that the bias current hardly flows to the variable gain amplifier circuit A1 by the differential amplifier 1._AGCIt matches the threshold value of. That is, the control voltage V_AGCThe gain characteristic and the bias current characteristic with respect to are as shown in FIG.
[0046]
V_AGC<V_B1When V_bias1Since the base potentials of the transistors Q3, Q5, Q6, and Q8 are lower than those of the transistors Q3, Q5, Q6, and Q8, the variable gain amplifier circuits A1 and A2 are not attenuated. This increases the gain. Also, V_AGC<V_B1At this time, if attention is paid only to the base potentials of the transistors Q2 to Q9, both the variable gain amplifiers A1 and A2 are operating._A2Hardly flows, so that only the variable gain amplifier circuit A1 is in operation, and a good noise figure characteristic can be obtained.
[0047]
V_B1<V_AGCControl voltage V_AGCIncreases as the gain G of the variable gain amplifier circuit A1 increases._A1Decreases and bias current I_A1Decreases, and the operation of the variable gain amplifier circuit A1 is stopped. At the same time, the bias current I_A2Therefore, the current flowing through the transistors Q18 and Q21 increases, and the variable gain amplifier circuit 2 starts to operate. And the control voltage V_AGCBecomes larger and V_B2<V_AGCThe bias current I_A1Therefore, the variable gain amplifier circuit A1 stops operating, and only the variable gain amplifier circuit A2 operates. At this time, the variable gain amplifier circuit A1 uses the gain G of the variable gain amplifier._totalTherefore, good intermodulation distortion characteristics can be obtained.
[0048]
Further, since only the operating variable gain amplifier circuit draws current from the output load resistors R5 and R6, the voltage drop at the output load resistors R5 and R6 does not increase. This eliminates the possibility of the transistor in the variable gain amplifier becoming saturated and not operating. Also, the bias current I_A1And I_A2Control voltage V_AGCDepending on the bias current I of the conventional variable gain amplifier_CSince it is made smaller, current consumption can be suppressed as compared with the conventional variable gain amplifier. Further, when switching the variable gain amplifier circuit that operates, the control voltage V at which the variable gain amplifier circuit that ends the operation by switching and the variable gain amplifier circuit that starts the operation by switching operate together._AGCRange (V_B1<V_AGC<V_B2) Is provided, it is possible to prevent the gain of the variable gain amplifier circuit from being lowered when switching the operating variable gain amplifier circuit.
[0049]
In the variable gain amplifier of the first embodiment described above, the two variable gain amplifier circuits A1 and A2 are connected in parallel for the sake of simplicity._AGCIt is desirable to connect more variable amplifier circuits in parallel in order to make the gain characteristic with respect to a smooth curve. FIG. 3 shows a variable gain amplifier according to the present invention having a configuration in which such a large number of variable amplifier circuits are connected in parallel. In addition, the same code | symbol is attached | subjected to the part same as FIG.
[0050]
The variable gain amplifier shown in FIG. 3 has a control voltage applied to the variable gain amplifier circuit A1, the variable gain amplifier circuit A2, the variable gain amplifier circuit A3 to An, and the variable gain amplifier circuit A2 to An having the same configuration as the variable gain amplifier circuit A1, respectively. Voltage shift circuits B2 to Bn and current control circuits 4 for controlling the bias currents of the variable gain amplifier circuits A1 to An, respectively, and the variable gain amplifier circuits A1 to An are connected in parallel. In the present invention, only the variable gain amplifier circuit operating as described above can reduce the voltage drop at the output load resistance by drawing the current from the output load resistance. This is particularly useful in a variable gain amplifier in which circuits are connected in parallel.
[0051]
Next, the variable gain amplifier according to the second embodiment of the present invention will be described. The configuration of the variable gain amplifier of the second embodiment is shown in FIG. In addition, the same code | symbol is attached | subjected to the part same as FIG. 1, and description is abbreviate | omitted.
[0052]
The A / D conversion circuit 5 has a control voltage V that is an analog value._AGCIs converted to a digital value voltage and output to the voltage shift arithmetic circuit 6. The voltage shift operation circuit 6 shifts the digital value voltage output from the A / D conversion circuit 5 by different predetermined amounts, respectively._D1, V_D2Is output to the D / A conversion circuit 7. The D / A converter circuit 7 is a digital voltage V_D1, V_D2For each analog value voltage V_A1, V_A2Converted to a voltage V_A1To the base of the transistor Q17, the voltage V_A2Are output to the base of the transistor Q15.
[0053]
Note that the control voltage V at which the differential amplifier circuit including the transistors Q4 and Q5 and the differential amplifier circuit including the transistors Q6 and Q7 start the attenuation operation._AGCOf the bias current I is applied to the variable gain amplifier circuit A2 by the differential amplifier 2._A2Voltage V begins to flow_AGCThe control voltage V at which the differential amplifier circuit composed of the transistors Q2 and Q3 and the differential amplifier circuit composed of the transistors Q8 and Q9 start the attenuating operation._AGCOf the bias current I is applied to the variable gain amplifier circuit A1 by the differential amplifier 1._A1Is the control voltage V_AGCSo that the voltage shift arithmetic circuit 6 matches the digital voltage V_D1And V_D2A predetermined shift amount used for calculating is set. As a result, the variable gain amplifier of the second embodiment can operate in the same manner as the variable gain amplifier of the first embodiment.
[0054]
Next, a variable gain amplifier according to a third embodiment of the present invention will be described. The configuration of the variable gain amplifier of the third embodiment is shown in FIG. In addition, the same code | symbol is attached | subjected to the part same as FIG. 4, and description is abbreviate | omitted.
[0055]
The A / D conversion circuit 5 has a control voltage V that is an analog value._AGCIs converted to a digital value voltage and output to the voltage shift arithmetic circuit 6. The voltage shift operation circuit 6 shifts the digital value voltage output from the A / D conversion circuit 5 by different predetermined amounts, respectively._D1', V_D2'Is output to the D / A conversion circuit 7'. The D / A conversion circuit 7 'includes a voltage-current conversion amplifier (not shown), and the digital voltage V_D1', V_D2′ Is converted into an analog value voltage, and the analog value voltage is converted into an analog value current I by a voltage-current conversion amplifier (not shown)._A1, I_A2Into the current I_A1To the collector of transistor Q23Flow I _A2Are output to the collector of the transistor Q22.
[0056]
Note that the control voltage V at which the differential amplifier circuit including the transistors Q4 and Q5 and the differential amplifier circuit including the transistors Q6 and Q7 start the attenuation operation._AGCThreshold isVariable gain amplifier circuitA2 is bias current I_A2Voltage V begins to flow_AGCThe control voltage V at which the differential amplifier circuit composed of the transistors Q2 and Q3 and the differential amplifier circuit composed of the transistors Q8 and Q9 start the attenuating operation._AGCThreshold isVariable gain amplifier circuitA1 is bias current I_A1Is the control voltage V_AGCSo that the voltage shift operation circuit 4 matches the digital voltage V_D1'And V_D2A predetermined shift amount used for calculating 'is set. As a result, the variable gain amplifier of the third embodiment can operate in the same manner as the variable gain amplifiers of the first and second embodiments.
[0057]
Here, an embodiment of the voltage shift arithmetic circuit 6 provided in the variable gain amplifiers of the second and third embodiments described above will be described. FIG. 6 (a) shows a voltage shift operation circuit in which the operations are processed in parallel, and FIG. 6 (b) shows a voltage shift operation circuit in which the operations are time-division processed.
[0058]
First, the voltage shift arithmetic circuit shown in FIG. The terminal 60 inputs a digital voltage from the A / D conversion circuit 5. The arithmetic circuit 61 performs a digital calculation by subtracting a predetermined shift amount ΔV 1 from the voltage value input at the terminal 60, and outputs the calculation result to the terminal 63. The arithmetic circuit 62 performs a digital calculation by subtracting a predetermined shift amount ΔV 2 from the voltage value input to the terminal 60, and outputs the calculation result to the terminal 64.
[0059]
Next, as shown in FIG.Voltage shift operation circuitWill be described. The terminal 65 receives a digital voltage from the A / D conversion circuit 5. The control circuit 67 controls connection of the switch 66.Voltage shift operation circuitPerforms the calculation according to the following procedure. First, the switch 66 is connected to the terminal a side. At this time, the arithmetic circuit 68 performs a digital calculation by subtracting a predetermined shift amount ΔV1 from the voltage value input to the terminal 65, and the calculation result is output to the terminal 69Output to. Thereafter, the switch 66 is connected to the terminal b side. At this time, the arithmetic circuit 68 performs a digital operation for subtracting the predetermined shift amount ΔV1 from the voltage value output by itself, that is, a digital operation for subtracting twice the predetermined shift amount ΔV1 from the voltage value input to the terminal 65. Thereafter, the switch 66 is again connected to the terminal a side, and the calculation is terminated. In such a configuration, since only one arithmetic circuit is required, the circuit scale can be reduced. This is particularly useful when a large number of variable gain amplifier circuits are provided as will be described later.
[0060]
Further, when the voltage shift calculation circuit 6 is configured to perform time division processing as shown in FIG. 6B, the D / A conversion circuit 7 or 7 ′ may be configured to perform conversion by time division processing. . As a result, the circuit scale of the D / A conversion circuit 7 or 7 'can be reduced.
[0061]
In the variable gain amplifiers of the second and third embodiments described above, two variable gain amplifier circuits are connected in parallel for the sake of simplicity._AGCIt is desirable to connect more variable amplifier circuits in parallel in order to make the gain characteristic with respect to a smooth curve. Further, in order to reduce the error of the voltage output to the bases of the transistors Q3 and Q8, an A / D conversion circuit, a voltage shift arithmetic circuit, and a D / A conversion are used instead of the voltage shift means comprising the resistors R3 and R4 A voltage shift means comprising a circuit may be used.
[0062]
In the variable gain amplifier circuit of the first to third embodiments described above, the control voltage V_AGCBased on the bias current I_A1And I_A2However, the present invention is not limited to this, and the control voltage V_AGCBias current I based on an external control voltage independent of_A1And I_A2It is good also as a structure which controls variably.
[0063]
【The invention's effect】
According to the present invention, since the current control means for variably controlling the value of the bias current output from the current source provided in the first differential amplifier circuit is provided for each variable gain amplifier circuit, the variable gain having good noise figure characteristics is provided. By reducing the bias current in the amplifier circuit, the leakage current flowing through the parasitic capacitance when a high frequency signal is input can be reduced, and saturation of gain attenuation can be prevented. As a result, a gain difference between the variable gain amplifier circuit having a good noise figure characteristic and another variable gain amplifier circuit can be secured, and the intermodulation distortion characteristic can be improved even when a high frequency signal is input. In addition, the voltage drop at the output load resistor can be reduced by reducing the bias current of only some variable gain amplifier circuits, and the input dynamic range can be reduced by not reducing the bias current of other variable gain amplifier circuits. Can be secured. Thereby, it is possible to prevent the transistor of the variable gain amplifier from being saturated without reducing the input dynamic range.
[0064]
Further, according to the present invention, the current control means shifts by a predetermined voltage with respect to the first control voltage input to the second differential amplifier circuit and the third differential amplifier circuit. Control voltage shift means for generating a voltage from a reference control voltage, and a second bias voltage that is shifted by a predetermined voltage with respect to bias voltages input to the second differential amplifier circuit and the third differential amplifier circuit A bias voltage shift means for generating the bias current from the bias voltage, and a control means for variably controlling the value of the bias current for each variable gain amplifier circuit according to the difference between the plurality of second control voltages and the second bias voltage; Therefore, the attenuation operation of the variable gain amplifier circuit and the value of the bias current can be controlled simultaneously by the reference control voltage.
[0065]
Further, according to the present invention, since the second control voltage is made smaller than the reference control voltage, the voltage shift by the control voltage shift means and the bias voltage shift means is easy.
[0066]
According to the present invention, the control voltage shift means includes a plurality of impedance elements connected in series, and the voltage at each connection point of the impedance elements is set as the second control voltage. realizable.
[0067]
According to the present invention, since the impedance element is a resistor, the control voltage shift means can be realized with a simpler configuration.
[0068]
Moreover, according to the present invention,controlThe voltage shift means digitally calculates the reference control voltage of the digital value output from the A / D conversion means for converting the reference control voltage from an analog value to a digital value, and the second digital value. Since the control means for generating the control voltage and the D / A conversion means for converting the second control voltage output from the calculation means from a digital value to an analog value are provided, the second is compared with the configuration using the impedance element. The control voltage error is reduced.
[0070]
Further, according to the present invention, since the arithmetic means performs digital arithmetic by time division processing, the circuit scale of the arithmetic means can be reduced.
[0071]
Further, according to the present invention, since the D / A conversion means performs the conversion by time division processing, the circuit scale of the D / A conversion means can be reduced.
[0072]
Further, according to the present invention, since the current control means sets the value of the bias current in the variable amplifier circuit to zero according to the reference control voltage, the variable gain amplifier circuit can be prevented from operating regardless of the attenuation operation. Thereby, the intermodulation distortion characteristic can be improved even when a high frequency signal is input. Further, it is possible to more reliably prevent the transistor of the variable gain amplifier from being saturated without reducing the input dynamic range.
[0073]
Further, according to the present invention, the variable gain amplifier circuit that operates is switched according to the reference control voltage, and when the variable gain amplifier that operates is switched, the variable gain amplifier circuit that ends the operation by switching and the operation is started by the switching. Since the reference control voltage range in which the variable gain amplifier circuit operates together is provided, it is possible to prevent the gain of the variable gain amplifier circuit from being lowered when the variable gain amplifier circuit to be operated is switched.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a variable gain amplifier according to a first embodiment of the present invention.
2 is a diagram illustrating gain characteristics of the variable gain amplifier of FIG. 1 and bias current characteristics of each variable gain amplifier circuit included in the variable gain amplifier of FIG. 1;
FIG. 3 is a diagram showing a configuration when a large number of variable gain amplifier circuits are provided in the variable gain amplifier of the first embodiment.
FIG. 4 is a diagram showing a configuration of a variable gain amplifier according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a variable gain amplifier according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an embodiment of a voltage shift arithmetic circuit provided in the variable gain amplifiers of the second and third embodiments.
FIG. 7 is a diagram showing a configuration of a conventional variable gain amplifier.
FIG. 8 is a diagram showing gain characteristics of a conventional variable gain amplifier.
FIG. 9 is a graph showing gain characteristics of a conventional variable gain amplifier when a high frequency signal is input.
FIG. 10 is a diagram showing input / output characteristics of a conventional variable gain amplifier.
FIG. 11 is a diagram showing another configuration of a conventional variable gain amplifier.
[Explanation of symbols]
1, 2 Differential amplifier circuit
3 Constant current source
4 Current control circuit
5 A / D conversion circuit
6 Voltage shift operation circuit
7, 7 'D / A conversion circuit
65, 69 terminals
66 switch
67 Control circuit
68 Arithmetic circuit
A1, A2, An Variable gain amplifier circuit
B2, Bn Voltage shift circuit
Q1-Q9 transistors
Q10 to Q13 Input transistor
Q14 to Q27 Transistor
R1-R4 resistance
R5, R6 Output load resistance

Claims (9)

A first transistor and a second transistor to which a differential input voltage is applied between the bases, and a first current source that outputs a bias current to supply current to the first transistor and the second transistor. Differential amplifier circuit of
A third transistor and a fourth transistor having an emitter commonly connected to a collector of the first transistor; a first control voltage applied to a base of the third transistor; A second differential amplifier circuit that attenuates and outputs the signal amplified by the first transistor in accordance with a difference from a bias voltage applied to the base;
The fifth transistor and the sixth transistor having emitters commonly connected to the collector of the second transistor, and the first control voltage and the sixth transistor applied to the base of the fifth transistor A third differential amplifier circuit that attenuates and outputs the signal amplified by the second transistor in accordance with a difference from the bias voltage applied to the base of
And a plurality of variable gain amplifier circuits connected in parallel.
In a variable gain amplifier comprising voltage shift means for generating the first control voltage for each of the variable gain amplifier circuits from a reference control voltage input from the outside,
Current control means for variably controlling the value of the bias current for each variable gain amplifier circuit ;
The current control unit generates a second control voltage that shifts by a predetermined voltage with respect to the first control voltage from the reference control voltage, and the predetermined voltage with respect to the bias voltage. A bias voltage shift means for generating a second bias voltage shifted by a voltage from the bias voltage, and a value of the bias current according to a difference between the plurality of second control voltages and the second bias voltage. And a control means for variably controlling each of the variable gain amplifier circuits . The variable gain amplifier according to claim 1, wherein the second control voltage is smaller than the reference control voltage . 3. The variable gain amplifier according to claim 2, wherein the control voltage shift means includes a plurality of impedance elements connected in series, and a voltage at each connection point of the impedance elements is the second control voltage . The variable gain amplifier according to claim 3, wherein the impedance element is a resistor . The control voltage shift means is
A / D conversion means for converting the reference control voltage from an analog value to a digital value;
Arithmetic means for digitally calculating the reference control voltage of the digital value output from the A / D conversion means to generate the second control voltage of the digital value;
D / A conversion means for converting the second control voltage output from the calculation means from a digital value to an analog value;
A variable gain amplifier according to claim 1 . 6. The variable gain amplifier according to claim 5, wherein the computing means performs digital computation by time division processing . The variable gain amplifier according to claim 6, wherein the D / A conversion means performs conversion by time division processing . The variable gain amplifier according to claim 1, wherein the current control unit sets a value of a bias current in the variable amplifier circuit to zero according to the reference control voltage . The operating variable gain amplifier circuit is switched according to the reference control voltage,
9. The reference control voltage range in which the variable gain amplifier circuit that ends operation by switching and the variable gain amplifier circuit that starts operation by switching operates when the operating variable gain amplifier switches. A variable gain amplifier according to 1.

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