JP3834422B2 - Variable gain amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable gain amplifier that amplifies a signal in a so-called IF (Intermediate Frequency) frequency band or RF (Radio Frequency) frequency band in a so-called TV tuner, BS tuner, etc. with an amplification degree according to its input level, In particular, the present invention relates to an improvement in distortion characteristics during gain attenuation.
[0002]
[Prior art]
Conventionally, this type of circuit is, for example, as shown in FIG. The conventional circuit will be generally described below with reference to FIG.
This conventional circuit has a difference between a first differential amplifier circuit 100 configured to perform a differential amplification operation on an input signal and one of differential output signals of the first differential amplifier circuit 100. The second differential amplifier circuit 101A configured to operate dynamically is configured to operate differentially with respect to the other differential output signal of the first differential amplifier circuit 100. And a third differential amplifier circuit 102A.
A predetermined third bias voltage Vc is applied to the bases of the first and second transistors 1 and 2 constituting the first differential amplifier circuit 100 via resistors 19 and 20, respectively, and an input signal Is applied, and the amplified output is input to the second and third differential amplifier circuits 101A and 102A.
Further, a predetermined first bias voltage VA is applied to the bases of the third transistor 3 constituting the second differential amplifier circuit 101A and the sixth transistor 6 constituting the third differential amplifier circuit 102A. Is applied to each base of the fourth transistor 4 constituting the second differential amplifier circuit 101A and the fifth transistor 5 constituting the third differential amplifier circuit 102A. A second bias voltage VB that changes in accordance with the magnitude of the input signal is applied.
As a result of controlling the current flowing through the resistors 11 and 12 by the change of the second bias voltage VB, the output gain is changed.
[0003]
[Problems to be solved by the invention]
By the way, in such an amplifier circuit, when the gain is lowered, so-called output distortion characteristics are deteriorated. However, in order to improve the distortion characteristics, in general, a sufficient drive current is allowed to flow through the amplification transistor, and sufficient characteristics are obtained. It is preferable to use a collector-emitter voltage VCE to use an operation region with less distortion. In other words, it can be said that a high power supply voltage and sufficient so-called drive current are required to obtain good distortion characteristics.
However, in general, the power supply voltage is naturally limited depending on the conditions of the device to be used, etc., and it is often impossible to use a sufficiently high voltage in consideration of distortion characteristics. Therefore, a sufficient current cannot flow. Always.
The present invention has been made in view of the above circumstances, and provides a variable gain amplifier circuit capable of ensuring stable operation without deteriorating output distortion characteristics at the time of gain reduction.
Another object of the present invention is to provide a variable gain amplifier capable of suppressing deterioration of output distortion characteristics when gain is reduced with a simple configuration.
[0004]
[Means for Solving the Problems]
A variable gain amplifier circuit according to the invention of claim 1 is provided.
A first differential amplifier circuit configured to operate differentially with respect to an input signal;
A second differential amplifier circuit configured to operate differentially with respect to one of the differential output signals of the first differential amplifier circuit;
A third differential amplifier circuit configured to operate differentially with respect to the other differential output signal of the first differential amplifier circuit;
The first differential amplifier circuit includes first and second transistors, and each of the first and second transistors has an input terminal to which an input signal is applied in a predetermined bias state.
The second differential amplifier circuit uses third and fourth transistors, and the emitters of the third and fourth transistors are connected to the collector of the first transistor of the first differential amplifier circuit. Connected,
The third differential amplifier circuit uses fifth and sixth transistors, and the emitters of the fifth and sixth transistors are connected to the collector of the second transistor of the first differential amplifier circuit. Connected,
A power supply voltage is applied to the collectors of the third and sixth transistors,
A power supply voltage is applied to each collector of the fourth and fifth transistors via a load resistor,
The bases of the third and sixth transistors have a first bias voltage having a predetermined voltage, and the bases of the fourth and fifth transistors have a second bias voltage that changes according to an input signal. In each variable gain amplifier configured to be applied,
A first bias power source that outputs the first bias voltage is connected to the bases of the third and sixth transistors via a first bias resistance element,
The bases of the fourth and fifth transistors are connected to a second bias power source that outputs the second bias voltage via a second bias resistance element.
[0005]
In this configuration, in particular, the base bias voltages of the third and sixth transistors are applied via the first bias resistance element, and the base bias voltages of the fourth and fifth transistors are set to the second. By applying the voltage via the bias resistive element, the distortion in the first differential amplifier circuit and the distortion in the second and third differential amplifier circuits are canceled out, and the output at the time of gain reduction is obtained. The distortion characteristics are not deteriorated and stable operation can be secured.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first circuit configuration example will be described with reference to FIG. The same components as those in the conventional circuit shown in FIG. The variable gain amplifier circuit is roughly divided into a first differential amplifier circuit 100 constituting an input stage and second and third differential amplifier circuits 101 and 102 constituting the next stage. It has become.
The first differential amplifier circuit 100 includes npn-type first and second transistors (indicated as “Q1” and “Q2” in FIG. 1 respectively) 1 and 2 as main components. The first input terminal 7 is connected to the base of the transistor 1, and the second input terminal 8 is connected to the base of the second transistor 2, and each base serves as an input terminal. .
[0007]
The base of the first transistor 1 is connected to a tenth resistor (in FIG. 1) via a ninth resistor (indicated as “R9” in FIG. 1) 19. Are both connected to a third bias power source 27 via a power supply 20 and a predetermined third bias voltage VC is applied thereto.
On the other hand, the emitter of the first transistor 1 is a third resistor (denoted as “R3” in FIG. 1) 13 as an emitter resistor, and the emitter of the second transistor 2 is an emitter resistor. The fourth resistor (indicated as “R4” in FIG. 1) 14 is connected to the ground, and both emitters are connected to a fifth resistor (in FIG. 1 as a current feedback resistor). Are connected to each other via 15).
[0008]
Further, the collector of the first transistor 1 is the emitter of the third and fourth transistors (indicated as “Q3” and “Q4” in FIG. 1) 3 and 4 constituting the second differential amplifier circuit 101, respectively. The collectors of the second transistors 2 are the emitters of the fifth and sixth transistors (indicated as “Q5” and “Q6” in FIG. 1) 5 and 6 constituting the third differential amplifier circuit 102, respectively. Are connected to each other.
[0009]
The second differential amplifier circuit 101 has npn-type third and fourth transistors 3 and 4 as main components, and the third and fourth transistors 3 and 4 have the emitter first. As described above, while being commonly connected to the collector of the first transistor 1, a predetermined power supply voltage Vcc is applied to the collector of the third transistor 3.
On the other hand, the collector of the fourth transistor 4 is connected to a first resistor (denoted as “R1” in FIG. 1) 11 as a load resistor, and a power source is connected via the first resistor 11. A voltage Vcc is applied, and the voltage Vcc is connected to the first output terminal 9 and serves as an output terminal.
[0010]
Further, the base of the third transistor 3 is mutually connected to the base of the sixth transistor 6 constituting the third differential amplifier circuit 102, and a sixth resistor as a first biasing resistive element. A predetermined first bias voltage VA is applied to the first bias power supply 25 via a device (denoted as “R6” in FIG. 1) 16.
On the other hand, the base of the fourth transistor 4 is mutually connected to the base of the fifth transistor 5 constituting the third differential amplifier circuit 102, and a seventh resistor as a second biasing resistive element is connected. The second bias voltage VB as described below is applied to the second bias power supply 26 via a device (indicated as “R7” in FIG. 1) 17.
[0011]
That is, the second bias power supply 26 is realized by a so-called AGC circuit configured to generate a so-called AGC (Automatic Gain Control) signal according to the strength of the input signal, and a circuit for generating such an AGC signal. For example, it may be a well-known or well-known circuit such as an average value AGC circuit, a peak value AGC circuit, a keyed AGC circuit, etc., and need not be limited to any specific one. It will be omitted.
In this circuit configuration example, the second bias voltage VB is set to decrease as the input signal applied from the external circuit to the first and second input terminals 7 and 8 increases. It has been made.
[0012]
The third differential amplifier circuit 102 has npn-type fifth and sixth transistors 5 and 6 as main components, and the connection of each base and emitter is as described above.
The collector of the fifth transistor 5 is connected to a second resistor 12 (denoted as “R2” in FIG. 1) 12 as a load resistor, and a power source is connected via the second resistor 12. A voltage Vcc is applied, and the voltage Vcc is connected to the second output terminal 10 and serves as an output terminal.
A predetermined power supply voltage Vcc is applied to the collector of the sixth transistor 6.
[0013]
Next, the operation in the above configuration will be described.
First, as a premise, the voltage VB of the second bias power supply 26 changes according to the change of the input signal applied to the first and second input terminals 7 and 8, and when the input signal is small, It is assumed that the voltage VB is large and the voltage VB is small when the input signal is large. Further, when the second bias voltage VB is small, the mutual relationship is set in advance so that the magnitude thereof is equal to or lower than the voltage VA of the first bias power supply 25.
Under this assumption, when an input signal is applied to the first and second input terminals 7 and 8, the input signal is amplified by the first differential amplifier circuit 100, and the amplified output is The signals are input to the second and third differential amplifier circuits 101 and 102. For example, when the input signals applied to the first and second input terminals 7 and 8 are reduced, the second bias voltage VB is increased accordingly, and when the first bias voltage VA of a predetermined voltage is exceeded, the fourth bias voltage VB is increased. The emitter currents of the third and fourth transistors 4 and 5 start to increase, while the emitter currents of the third and sixth transistors 3 and 6 decrease.
[0014]
When the input signal is further reduced and the second bias voltage VB is sufficiently larger than the first bias voltage VA having a predetermined voltage, the emitter currents of the third and sixth transistors 3 and 6 do not flow. The emitter currents of the fourth and fifth transistors 4 and 5 are maximum, and are equal to the collector currents of the first and second transistors 1 and 2 in the input stage, respectively. Therefore, the second input signals applied to the first and second input terminals 7 and 8 and input to the second and third differential amplifier circuits 101 and 102 via the first differential amplifier circuit 100 are obtained. The attenuation by the third and sixth transistors 3 and 6 is minimized. On the other hand, in this case, since the amplification degree of the fourth and fifth transistors 4 and 5 is maximized, the input signal that has passed through the first differential amplifier circuit 100 is generated by the fourth and fifth transistors 4 and 5. In response to the maximum amplification, the maximum output is obtained at the first and second output terminals 9 and 10 .
[0015]
Next, the operation when the input signal increases will be described. In this case, the second bias voltage VB decreases as the input signal increases. When the second bias voltage VB becomes equal to or lower than the first bias voltage VA, the respective emitter currents of the fourth and fifth transistors 4 and 5 decrease, while the third and sixth transistors 3 and 3 Both emitter currents of 6 will increase.
[0016]
When the input signal becomes larger and the second bias voltage VB becomes sufficiently smaller than the first bias voltage VA, the emitter currents of the fourth and fifth transistors 4 and 5 do not flow. The emitter current of each of the third and sixth transistors 3 and 6 has a maximum value, and the current is equal to the collector current of each of the first and second transistors 1 and 2 in the input stage. Therefore, the emitter input impedances of the third and sixth transistors 3 and 6 are minimized, and the attenuation amount with respect to the input signal in the third and sixth transistors 3 and 6 is maximized. In other words, the third and sixth transistors 3 and 6 act as shunt transistors for the input signal. On the other hand, since the emitter currents of the fourth and fifth transistors 4 and 5 do not flow at this time, the amplification degree with respect to the input signal in the fourth and fifth transistors 4 and 5 is minimized. The output signals at the second output terminals 9 and 10 are in a minimum state.
[0017]
As described above, in this variable gain amplifier circuit, the change in the emitter input impedance of the third and sixth transistors 3 and 6 and the change in the amplification factor by the current control of the fourth and fifth transistors 4 and 5 Due to the double effect, a large gain control can be obtained.
In this variable gain amplifier circuit, the first bias voltage VA is applied to the bases of the third and sixth transistors 3 and 6 through the sixth resistor 16 and the seventh resistor 17 through the seventh resistor 17. By applying the second bias voltage VB to the bases of the fourth and fifth transistors 4 and 5, the output distortion characteristics at the time of low gain can be improved.
[0018]
Specifically, the improvement of the output distortion characteristic can be confirmed by a test example as described below.
First, FIG. 3 shows the first circuit configuration example described above, the second circuit configuration example described later, and the output level and intermodulation distortion level with respect to the change of the second bias voltage VB in each of the conventional circuits. The test example about the difference is shown, and the figure will be described below.
First, in this test example, when 45 MHz is input as the first input signal and 47 MHz is input as the second input signal at both −30 dBm, the second bias voltage VB is changed. .
In FIG. 3, in the row labeled “FULL-GAIN”, the values described in the “Conventional example”, “Configuration example 1”, and “Configuration example 2” columns indicate that the circuit is in the maximum gain state. In this case, the respective output levels are shown. According to the figure, it is shown that an output level of 20 dB is obtained. In the figure, “−10 dBm OUT-IMD” means the difference between the output level of −10 dBm and the level of intermodulation distortion when the output level of −10 dBm is obtained. The numerical values described in the columns of “example”, “configuration example 1”, and “configuration example 2” represent the difference. Note that the meanings of “−20 dBm OUT-IMD” and “−30 dBm OUT-IMD” also conform to the meaning of “−10 dBm OUT-IMD” described above.
[0019]
Therefore, in the test example, when the conventional example and the configuration example 1 are viewed, when the output level is −30 dBm, the difference between the output level and the intermodulation distortion level is 50 dB in the conventional example. In the configuration example 1, it can be confirmed that 61 dB is improved by 11 dB from the conventional example. Configuration example 2 will be described later.
FIG. 4 shows a characteristic diagram shown in the diagram for the configuration example 1 among the test results described above. In the figure, the characteristic curve indicated by a two-dot chain line is as described above. This shows a change in output level accompanying a change in the second bias voltage under various input conditions. In the same figure, the characteristic curve indicated by the solid line shows the change in the intermodulation distortion (intermodulation) level accompanying the change in the second bias voltage for each of the two input signals (45 MHz and 47 MHz). is there. In FIG. 4, “IMD level” means an intermodulation distortion level.
[0020]
Next, a second circuit configuration example will be described with reference to FIG.
The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different points will be mainly described.
In the second circuit configuration example, the first bias power supply 25 is directly connected to the bases of the third and sixth transistors 3 and 6, and an eighth resistor as a first bias resistance element is used. This configuration is also connected to the bases of the fourth and fifth transistors 4 and 5 via 18.
In this configuration, in particular, the base voltages of the fourth and fifth transistors 4 and 5 are obtained by superimposing the second bias voltage VB on the first bias voltage VA that is a predetermined voltage.
The amplifying operation of the entire circuit is basically the same as that of the circuit configuration example shown in FIG. 1, and detailed description thereof will be omitted here.
[0021]
Here, regarding the second circuit configuration example, in the test example shown in FIG. 3, when the output level is −30 dBm, the difference between the output level and the intermodulation distortion level is 58 dB. On the other hand, in the conventional example, it is 50 dB, and it can be confirmed that this second circuit configuration example has improved by 8 dB.
[0022]
In the embodiments of the present invention described above, each circuit configuration example uses an npn-type transistor. However, of course, the invention is not limited to this, and may be configured similarly using a pnp-type transistor. Instead of the bipolar transistor, another type of transistor such as a field effect transistor may be used.
Further, the first and second bias resistance elements may be replaced with resistors, for example, by providing a transistor, and utilizing the resistance in the operating state of the transistor.
[0023]
【The invention's effect】
As described above, according to the present invention, a fixed bias voltage is applied to the bases of the third and sixth transistors whose collectors are connected to the power supply via the first bias resistance element. In addition, a second bias resistance element is provided at the base of each of the fourth transistor that constitutes the differential amplifier circuit with the third transistor and the fifth transistor that constitutes the differential amplifier circuit with the sixth transistor. By applying a second bias voltage that varies with the magnitude of the input signal through a simple configuration, the output distortion characteristics at the time of gain reduction are not deteriorated and a stable operation can be ensured with a simple configuration. .
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first circuit configuration example according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a second circuit configuration example according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a test example of a difference between an output level and an intermodulation distortion level with respect to a change in a second bias voltage.
4 is a characteristic curve showing a change characteristic of an output level and a change characteristic of an intermodulation distortion level with respect to a change of a second bias voltage in the first circuit configuration example in the test example shown in FIG. 3; .
FIG. 5 is a circuit diagram showing a conventional circuit example.
[Explanation of symbols]
16 ... Sixth resistor (first biasing resistance element)
17 ... Seventh resistor (second biasing resistance element)
18: Eighth resistor (first biasing resistance element)
25 ... 1st bias power supply 26 ... 2nd bias power supply 100 ... 1st differential amplifier circuit 101 ... 2nd differential amplifier circuit 102 ... 3rd differential amplifier circuit

Claims (4)

A first differential amplifier circuit configured to operate differentially with respect to an input signal;
A second differential amplifier circuit configured to operate differentially with respect to one of the differential output signals of the first differential amplifier circuit;
A third differential amplifier circuit configured to operate differentially with respect to the other differential output signal of the first differential amplifier circuit;
The first differential amplifier circuit includes first and second transistors, and each of the first and second transistors has an input terminal to which an input signal is applied in a predetermined bias state.
The second differential amplifier circuit uses third and fourth transistors, and the emitters of the third and fourth transistors are connected to the collector of the first transistor of the first differential amplifier circuit. Connected,
The third differential amplifier circuit uses fifth and sixth transistors, and the emitters of the fifth and sixth transistors are connected to the collector of the second transistor of the first differential amplifier circuit. Connected,
A power supply voltage is applied to the collectors of the third and sixth transistors,
A power supply voltage is applied to each collector of the fourth and fifth transistors via a load resistor,
The bases of the third and sixth transistors have a first bias voltage having a predetermined voltage, and the bases of the fourth and fifth transistors have a second bias voltage that changes according to an input signal. In each variable gain amplifier configured to be applied,
A first bias power source that outputs the first bias voltage is connected to the bases of the third and sixth transistors via a first bias resistance element,
A variable gain characterized in that a base of each of the fourth and fifth transistors is connected to a second bias power source that outputs the second bias voltage via a second bias resistance element. amplifier. A first differential amplifier circuit configured to operate differentially with respect to an input signal and a differential output signal of the first differential amplifier circuit so as to operate differentially. A second differential amplifier circuit configured;
A third differential amplifier circuit configured to operate differentially with respect to the other differential output signal of the first differential amplifier circuit;
The first differential amplifier circuit includes first and second transistors, and each of the first and second transistors has an input terminal to which an input signal is applied in a predetermined bias state.
The second differential amplifier circuit uses third and fourth transistors, and the emitters of the third and fourth transistors are connected to the collector of the first transistor of the first differential amplifier circuit. Connected,
The third differential amplifier circuit uses fifth and sixth transistors, and the emitters of the fifth and sixth transistors are connected to the collector of the second transistor of the first differential amplifier circuit. Connected,
A power supply voltage is applied to the collectors of the third and sixth transistors,
A power supply voltage is applied to each collector of the fourth and fifth transistors via a load resistor,
The bases of the third and sixth transistors have a first bias voltage having a predetermined voltage, and the bases of the fourth and fifth transistors have a second bias voltage that changes according to an input signal. In each variable gain amplifier configured to be applied,
A first bias power source is directly connected to the bases of the third and sixth transistors,
The bases of the fourth and fifth transistors are connected to the first bias power source via a first bias resistance element and to the second bias resistance element via the second bias resistance element . A variable gain amplifier, characterized in that a second bias power supply for outputting a bias voltage is connected.   3. The variable gain amplifier according to claim 1, wherein the first and second bias resistance elements are resistors.   3. The variable gain amplifier according to claim 1, wherein the first and second bias resistance elements are made of semiconductor elements.

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