JP3831380B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3831380B2
JP3831380B2 JP2004009253A JP2004009253A JP3831380B2 JP 3831380 B2 JP3831380 B2 JP 3831380B2 JP 2004009253 A JP2004009253 A JP 2004009253A JP 2004009253 A JP2004009253 A JP 2004009253A JP 3831380 B2 JP3831380 B2 JP 3831380B2
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semiconductor element
semiconductor device
lead
semiconductor
resin
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JP2004165695A (en
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敏幸 高橋
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Hitachi Ltd
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Hitachi Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、薄型を要する半導体装置に関し、特に、ワイヤボンディングを用いた半導体装置の製造技術に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device that requires thinness, and particularly relates to a technique that is effective when applied to a manufacturing technique of a semiconductor device using wire bonding.

従来におけるワイヤボンディングを用いた半導体装置の製造は、リードフレームに設けられたダイ(アイランド)に接着剤や接着テープで半導体素子を固定し、半導体素子とリードフレームのインナーリードとをワイヤで電気的に接続して、半導体素子とインナーリードとを樹脂で封止することによって行われていた(例えば、非特許文献1)。   In the conventional manufacturing of a semiconductor device using wire bonding, a semiconductor element is fixed to a die (island) provided on a lead frame with an adhesive or an adhesive tape, and the semiconductor element and the inner lead of the lead frame are electrically connected with a wire. And the semiconductor element and the inner lead are sealed with resin (for example, Non-Patent Document 1).

最新サーフェイス・マウント・テクノロジー(工業調査会発行1986年6月1初版)、159〜161頁。The latest Surface Mount Technology (Industry Research Council, published June 1, 1986, first edition), pages 159-161.

本発明者は、上記従来技術を検討した結果、以下の問題点を見いだした。
従来のワイヤボンディングを用いた半導体装置の製造方法では、半導体素子の固定部であるダイと固定用の接着剤や接着テープの厚さが半導体装置の厚さの一部となり、薄型にするが困難であるという問題点があった。
また、半導体素子の電極パッ面とリードフレームのインナーリードのボンディングパッ面では段差ができることにより、チップ周辺部とショートを考慮に入れると、ボンディングワイヤのループが高くなるため、いっそう薄型化が困難であった。
本発明の目的は、半導体装置の厚さを薄くすることが可能な技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
As a result of studying the above prior art, the present inventor has found the following problems.
In the conventional method of manufacturing a semiconductor device using wire bonding, the thickness of the die, which is a fixing portion of the semiconductor element, and the fixing adhesive or adhesive tape are part of the thickness of the semiconductor device, making it difficult to reduce the thickness. There was a problem that.
In addition, since the can step in bonding pad surface of the inner lead electrode pad surface and the lead frame of the semiconductor device, taking into account the chip peripheral portion and a short, since the bonding wire loop is high, even thinner It was difficult.
An object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
(1)半導体装置は、半導体素子と、前記半導体素子を挟んでその両側に配置されたリードと、前記各リードの一方の面と対応する前記半導体素子の電極とをそれぞれ接続するワイヤと、前記半導体素子と前記ワイヤと前記リードを封止する樹脂とによって構成され、前記半導体素子の裏面と前記各リードの他方の面が略同一面になるように配置され前記封止樹脂から露出した構成を有することを特徴とする。
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor device includes: a semiconductor element; leads arranged on both sides of the semiconductor element; wires connecting the electrodes of the semiconductor element corresponding to one surface of each lead; A semiconductor element, a wire, and a resin that seals the lead; and a configuration in which the back surface of the semiconductor element and the other surface of each lead are disposed on substantially the same surface and exposed from the sealing resin. It is characterized by having.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
前記(1)の手段によれば、本発明の半導体装置は、前記半導体素子の裏面と前記各リードの他方の面が略同一面になるように配置され、かつ前記封止樹脂から露出した構成になっていることから、半導体装置の厚さを薄くすることが可能となる。
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means of (1), the semiconductor device of the present invention is arranged such that the back surface of the semiconductor element and the other surface of each lead are substantially flush with each other and exposed from the sealing resin. Therefore, the thickness of the semiconductor device can be reduced.

以下、本発明の構成について、実施例とともに説明する。なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, the configuration of the present invention will be described together with examples. In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.

図1は、本発明の一実施例である半導体装置の製造方法を説明するための図である。なお、本実施例の製造方法を簡単に説明するため、全ての図面は、半導体装置を中央付近で切った断面図を用い、説明する上で必要ないものは省略している。
図1において、1はリードフレーム(フレーム枠の記載を除いてある)、2は接着テープ、3は半導体素子、4はワイヤ、5は樹脂をそれぞれ示す。
FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. Note that, in order to briefly describe the manufacturing method of the present embodiment, all the drawings are cross-sectional views of the semiconductor device cut in the vicinity of the center, and those unnecessary for description are omitted.
In FIG. 1, 1 is a lead frame (except for the frame frame), 2 is an adhesive tape, 3 is a semiconductor element, 4 is a wire, and 5 is a resin.

本実施例の半導体装置の製造は、まず、図1(a)に示すように、半導体素子搭載するダイの無いリードフレーム1を用意し、図1(b)に示すように、リードフレーム1に接着テープ2を貼り付け、続いて、図1(c)に示すように、接着テープ2の所定位置にダイシングされた半導体素子3を接着する。
この接着テープ2は、粘着テープならそのまま、粘着性の無いものなら接着剤を使用して付ける。
In the manufacture of the semiconductor device of this embodiment, first, as shown in FIG. 1A, a lead frame 1 without a die for mounting a semiconductor element is prepared, and as shown in FIG. The adhesive tape 2 is affixed, and then the diced semiconductor element 3 is adhered to a predetermined position of the adhesive tape 2 as shown in FIG.
The adhesive tape 2 is attached using an adhesive if it is a pressure-sensitive adhesive tape, and if it is not sticky.

また、半導体装置の信頼性の向上のために、接着テープ2の貼り付けは、半導体素子の裏面全体に行なわず、半導体素子裏面の中心部のみを接着し、かつ、リードフレームもインナーリードの部分だけ接着しないようにし、後述する樹脂封止の工程で樹脂が半導体素子、インナーリードに回り込めるようにしてもよい。   Further, in order to improve the reliability of the semiconductor device, the adhesive tape 2 is not applied to the entire back surface of the semiconductor element, but only the central portion of the back surface of the semiconductor element is bonded, and the lead frame is also a part of the inner lead. However, the resin may be wrapped around the semiconductor element and the inner lead in the resin sealing step described later.

次に、図1(d)に示すように、半導体素子3の電極パッ部とリードフレーム1のボンディングパッ部を金線等のワイヤ4を使い、ワイヤボンディングで接続し、図1(e)に示すように、ポッティング等の方法で製品の保護を必要とする部分を樹脂5で封止する。これにより半導体素子3とリードフレーム1を固定する。 Next, as shown in FIG. 1 (d), using a wire 4 of gold or the like bonding pad portion of the electrode pad portion and the lead frame 1 of the semiconductor element 3 is connected by wire bonding, FIG. 1 (e As shown in FIG. 5, the part that needs protection of the product is sealed with a resin 5 by a method such as potting. Thereby, the semiconductor element 3 and the lead frame 1 are fixed.

そして、図1(f)に示すように、半導体素子3とリードフレーム1を固定していた接着テープ2を取り除き、樹脂流れ止めのダムバーを除去し、リードフレームの切断除去を施し、図1(g)に示す半導体装置を得る。   Then, as shown in FIG. 1 (f), the adhesive tape 2 that has fixed the semiconductor element 3 and the lead frame 1 is removed, the dam bar for preventing resin flow is removed, and the lead frame is cut and removed. The semiconductor device shown in g) is obtained.

また、例えば、図8に示すように、リードフレーム1のボンディングパッド部が平らになるようにコイニング等で段差をつけることにより、ワイヤボンディングの接着性が向上し、かつ、その段差部分がポッティングの樹脂のストッパーの役目を果たし、流動性の高い樹脂を用いて封止することができるので、半導体装置の厚さをより薄くコントロールできる。
最後に、図1(h)に示すように、必要に応じてリードフレーム1のアウタリードを折り曲げる。
Further, for example, as shown in FIG. 8, by providing a step by means of coining or the like so that the bonding pad portion of the lead frame 1 becomes flat, the adhesion of wire bonding is improved, and the step portion is potted. Since it serves as a resin stopper and can be sealed with a highly fluid resin, the thickness of the semiconductor device can be controlled to be thinner.
Finally, as shown in FIG. 1H, the outer lead of the lead frame 1 is bent as necessary.

次に、図1(f)に示した接着テープ2の取り除き工程を具体的に挙げ、以下に説明する。
図2、図3は、本実施例の半導体装置の製造方法における接着テープ取り除き工程の具体的手段を説明するための図である。
図2、図3において、10は突き上げ針、11はリードフレームの枠押さえ、12はテープはぎ取り金型をそれぞれ示す。
Next, the step of removing the adhesive tape 2 shown in FIG.
2 and 3 are diagrams for explaining specific means of the adhesive tape removing step in the method of manufacturing a semiconductor device according to this embodiment.
2 and 3, reference numeral 10 denotes a push-up needle, 11 denotes a frame holder for the lead frame, and 12 denotes a tape stripping mold.

本実施例の接着テープ取り除き工程の第一の手段は、図2に示すように、接着テープ2の下から複数の針10を用いて半導体素子とリードフレーム1を突き上げ、取り除くものである。   As shown in FIG. 2, the first means of the adhesive tape removing process of the present embodiment is to push up the semiconductor element and the lead frame 1 using a plurality of needles 10 from below the adhesive tape 2 and remove them.

第二の手段は、図3(a)に示すように、リードフレーム1の端を枠押さえ11で押さえておき、リードフレーム1の穴あき部分からテープはぎ取り金型12で接着テープ2を押し出すことによって取り除くものである。
上述したいずれかの手段を用いることにより、容易に接着テープ2の取り除くことができる。なお、接着テープ取り除き手段は、これに限定されない。
As shown in FIG. 3A, the second means is to hold the end of the lead frame 1 with a frame presser 11 and push out the adhesive tape 2 from the holed portion of the lead frame 1 with a tape stripping mold 12. Is to be removed.
By using any of the means described above, the adhesive tape 2 can be easily removed. The adhesive tape removing means is not limited to this.

次に、本実施例の製造方法の応用について図4を用いて説明する。
まず、リードの長さが短いリードフレームと長いリードフレームとでそれぞれ上述した製造方法を用いて半導体装置の製造を行い、図4(a)に示すように、それぞれのリードを折り曲げ、リード形形状の長短を組み合わせることにより半導体装置の積層化が可能となる。
Next, application of the manufacturing method of the present embodiment will be described with reference to FIG.
First, the manufacturing of the semiconductor device by the manufacturing method described above, respectively and short lead frame length of the lead and a long lead frame, as shown in FIG. 4 (a), bending each lead, the lead formed shape By combining the shape length, the semiconductor device can be stacked.

また、図1(h)に示したリードの折り曲げ工程で、リードを反対方向に折り曲げることにより、図4(b)に示すようなリバース曲げタイプの半導体装置を製造することができる。
さらに、リバース曲げタイプの半導体装置において、パワーを要するものは、本実施例のリードの折り曲げ工程の後に、図4(c)に示すように、半導体素子及びリードフレームの一部に絶縁された両面テープ20を介在させ、放熱板21を貼り付ける工程を設けることにより、効率よく熱を逃がすことが可能な半導体装置を製造できる。
Further, by bending the lead in the opposite direction in the lead bending process shown in FIG. 1H, a reverse bending type semiconductor device as shown in FIG. 4B can be manufactured.
Further, in the reverse bend type semiconductor device, the one requiring power is a double-sided surface insulated by a part of the semiconductor element and the lead frame as shown in FIG. 4C after the lead bending process of this embodiment. By providing the step of attaching the heat sink 21 with the tape 20 interposed, a semiconductor device capable of efficiently releasing heat can be manufactured.

図5は、本実施例の製造方法で製造された半導体装置における各部分の厚さを示した図であり、図5(a)が単体のものであり、図5(b)が二つの単体を重ねた積層タイプのものである。   FIG. 5 is a diagram showing the thickness of each part in the semiconductor device manufactured by the manufacturing method of the present embodiment. FIG. 5A is a single unit, and FIG. 5B is two single units. Is a laminated type of

図5(a)に示すように、本実施例の製造方法で製造された半導体装置における各部分の厚さは、金線ループの高さが0.2mm、ループ上の樹脂厚が0.1mm、半導体素子の厚さが0.28mm、リードフレームの厚さが0.17±0.05mm、リードを折り曲げないときの半導体装置全体の厚さが0.58mmである。
これにより、従来の方法で製造された半導体装置にあったダイと半導体素子固定用テープがなくなり、全体の厚さが薄くなっていることがわかり、さらに、金線のループの高さ、樹脂の厚さも薄くなっていることもわかる。
As shown in FIG. 5A, the thickness of each part in the semiconductor device manufactured by the manufacturing method of the present embodiment is such that the height of the gold wire loop is 0.2 mm and the resin thickness on the loop is 0.1 mm. The thickness of the semiconductor element is 0.28 mm, the thickness of the lead frame is 0.17 ± 0.05 mm, and the thickness of the entire semiconductor device when the leads are not bent is 0.58 mm.
As a result, it can be seen that the die and the semiconductor element fixing tape in the semiconductor device manufactured by the conventional method are eliminated, and the overall thickness is reduced. Further, the height of the loop of the gold wire, the resin It can also be seen that the thickness is getting thinner.

また、図5(b)に示すように、二つの単体を重ねた積層タイプの半導体装置全体の厚さは、1.16〜1.9mmである。
したがって、上述したように本実施例では、半導体素子の固定部であるダイ及び半導体素子固定のための接着剤や接着テープが半導体装置の厚さの一部とはならないため、半導体装置の厚さを薄くすることができる。
Further, as shown in FIG. 5B, the thickness of the entire stacked semiconductor device in which two single bodies are stacked is 1.16 to 1.9 mm.
Therefore, as described above, in this embodiment, the die that is the fixing portion of the semiconductor element and the adhesive or adhesive tape for fixing the semiconductor element do not become a part of the thickness of the semiconductor device. Can be made thinner.

また、半導体素子の固定部であるダイ及びその接着剤や接着テープを用いる必要がなくなることにより、半導体素子の電極パッ面とリードフレームのインナーリードのボンディングパッ面では段差が小さくなり、低ループのワイヤボンディングができるので、半導体装置の厚さを薄くすることが可能となる。 Further, by the need not to use a die and the adhesive or adhesive tape which is a fixed part of the semiconductor element, the step is reduced in the bonding pad surface of the electrode pad surface of the lead frame the inner leads of the semiconductor device, the low Since the loop wire bonding can be performed, the thickness of the semiconductor device can be reduced.

以上、本発明の一実施例として、リードを有する半導体装置の製造方法について説明してきたが、本発明は、これに限定されず、プリント基板に半導体素子を直接搭載するCOB型(Chip On Board)、P/B−LCC(Print Board Leadless Chip Carrier) 型半導体装置の製造にも同様に応用可能であり、ここではCOB型半導体装置を例に挙げて以下に説明する。   As described above, the manufacturing method of the semiconductor device having leads has been described as an embodiment of the present invention. However, the present invention is not limited to this, and the COB type (Chip On Board) in which the semiconductor element is directly mounted on the printed board. The present invention can be similarly applied to the manufacture of a P / B-LCC (Print Board Leadless Chip Carrier) type semiconductor device. Here, a COB type semiconductor device will be described as an example.

図6は、本発明の他の実施例であるCOB型半導体装置の製造方法を説明するための図である。
図6において、30はプリント基板を示す。
FIG. 6 is a diagram for explaining a method of manufacturing a COB type semiconductor device according to another embodiment of the present invention.
In FIG. 6, reference numeral 30 denotes a printed circuit board.

本実施例のCOB型半導体装置の製造は、まず、図6(a)に示すように、プリント基板30に半導体素子3が入る大きさのスルーホールを形成し、図6(b)に示すように、素子が形成されていない裏面に接着テープ2を貼り付け、続いて、図6(c)に示すように、プリント基板30の所定位置にダイシングされた半導体素子3を接着する。   In the manufacture of the COB type semiconductor device of the present embodiment, first, as shown in FIG. 6A, a through hole having a size into which the semiconductor element 3 can enter is formed in the printed circuit board 30, and as shown in FIG. Then, the adhesive tape 2 is attached to the back surface on which no element is formed, and then the diced semiconductor element 3 is bonded to a predetermined position of the printed circuit board 30 as shown in FIG.

次に、図6(d)に示すように、半導体素子3の電極パッ部とプリント基板30のボンディングパッ部を金線等のワイヤ4を使い、ワイヤボンディングで接続し、図6(e)に示すように、ポッティング等の方法で製品の保護を必要とする部分を樹脂5で封止する。これにより半導体素子3とプリント基板30を固定する。
Next, as shown in FIG. 6 (d), using a wire 4 of gold or the like bonding pad portion of the electrode pad and the circuit board 30 of the semiconductor element 3 is connected by wire bonding, FIG. 6 (e As shown in FIG. 5, the part that needs protection of the product is sealed with a resin 5 by a method such as potting. Thereby, the semiconductor element 3 and the printed circuit board 30 are fixed.

そして、図6(f)に示すように、半導体素子3とプリント基板30を固定していた接着テープ2を取り除き、図6(g)に示す半導体装置を得る。
なお、接着テープ2のはぎ取りは、図2に示したものと同様に、接着テープ2の下から複数の針10を用いて半導体素子3とプリント基板30を突き上げ、取り除くものを用いる。
Then, as shown in FIG. 6F, the adhesive tape 2 that has fixed the semiconductor element 3 and the printed board 30 is removed to obtain the semiconductor device shown in FIG.
Note that the adhesive tape 2 is peeled off by using a plurality of needles 10 to push up and remove the semiconductor element 3 and the printed circuit board 30 from below the adhesive tape 2 in the same manner as shown in FIG.

また、P/B−LCC型半導体装置の製造もCOB型半導体装置と同じ製造工程である。
このように、前述のリードを有する半導体装置の場合と同様な工程を行うことにより、COB型、P/B−LCC型半導体装置でも薄型化が可能となる。
The manufacture of the P / B-LCC type semiconductor device is the same manufacturing process as the COB type semiconductor device.
As described above, by performing the same process as that of the semiconductor device having the above-described leads, the COB type and P / B-LCC type semiconductor devices can be thinned.

次に、上述した本実施例の方法で製造した半導体装置を積層する場合について図7を用いて説明する。
まず、図6(a)、図6(b)に示したスルーホール付きプリント基板30に接着テープ2を貼り付け工程を、スルーホール付きプリント基板30の代わりに、図7(a)に示すように、スルーホール付きの段差があるプリント基板(以下、ザグリ基板と記す)30aと、接着テープ2の代わりに、ザグリ基板30aの段差と嵌合する形状の段差を有する段差接着テープ2aとを用いて行い、以下、上述同様に製造していくと、図7(b)に示す半導体装置が得られる。
Next, the case where the semiconductor devices manufactured by the method of the present embodiment described above are stacked will be described with reference to FIG.
First, the process of attaching the adhesive tape 2 to the printed circuit board 30 with through holes shown in FIGS. 6A and 6B is performed as shown in FIG. 7A instead of the printed circuit board 30 with through holes. In addition, a printed circuit board 30a having a step with a through hole (hereinafter referred to as a counterbore substrate) 30a and a step adhesive tape 2a having a stepped shape that fits with the step of the counterbore substrate 30a are used instead of the adhesive tape 2. Then, the semiconductor device shown in FIG. 7 (b) is obtained.

この図7(b)に示したザグリ基板を有する半導体装置と図6(g)に示したザグリ基板を有しない半導体装置を組み合わせることにより、図7(c)に示すように、COB型、P/B−LCC型の半導体装置でも積層化できる。   By combining the semiconductor device having the counterbore substrate shown in FIG. 7B and the semiconductor device not having the counterbore substrate shown in FIG. 6G, as shown in FIG. A / B-LCC type semiconductor device can also be stacked.

次に、上述してきた各半導体装置を金型を用いて製造する方法について説明する。
図9は、本実施例の金型を用いた半導体装置の製造方法を説明するための図である。
本実施例の金型を用いた半導体装置の製造方法は、まず、図9(a)に示すように、仮固定治具35に接着剤36を塗布しておき、図9(b)に示すように、リードフレーム1を用意し、図9(c)に示すように、リードフレーム1を仮固定治具35に固定する。
Next, a method for manufacturing each of the semiconductor devices described above using a mold will be described.
FIG. 9 is a diagram for explaining a method of manufacturing a semiconductor device using the mold of this embodiment.
In the method of manufacturing a semiconductor device using the mold of this embodiment, first, as shown in FIG. 9A, an adhesive 36 is applied to the temporary fixing jig 35, and the process shown in FIG. Thus, the lead frame 1 is prepared, and the lead frame 1 is fixed to the temporary fixing jig 35 as shown in FIG.

そして、図9(d)に示すように、半導体素子3を仮固定治具35に固定し、図9(e)に示すように、リードフレーム1と半導体素子3をワイヤ4でボンディングする。
その後、図9(f)に示すように、金型の上型40、41下型で用いて、図9(g)に示すように、樹脂5で封止し、図9(h)に示すように、金型40、41を取り外す。
Then, the semiconductor element 3 is fixed to the temporary fixing jig 35 as shown in FIG. 9D, and the lead frame 1 and the semiconductor element 3 are bonded with the wire 4 as shown in FIG.
Thereafter, as shown in FIG. 9 (f), the upper molds 40 and 41 of the mold are used in the lower mold and sealed with the resin 5 as shown in FIG. 9 (g), as shown in FIG. 9 (h). As such, the molds 40 and 41 are removed.

その後、図9(i)に示すように、仮固定治具35と接着剤36を取り除き、図9(j)に示すように、アウタリードを曲げる。
なお、ここでは、リードを有する半導体装置について説明したが、COB型、P/B−LCC型の半導体装置の製造も同様に行うことができる。
Thereafter, the temporary fixing jig 35 and the adhesive 36 are removed as shown in FIG. 9 (i), and the outer lead is bent as shown in FIG. 9 (j).
Although a semiconductor device having a lead has been described here, a COB type or P / B-LCC type semiconductor device can be manufactured in the same manner.

以上、本発明者によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の一実施例である半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device which is one Example of this invention. 本実施例の半導体装置の製造方法におけるテープ取り除き工程の具体的手段を説明するための図である。It is a figure for demonstrating the specific means of the tape removal process in the manufacturing method of the semiconductor device of a present Example. 本実施例の半導体装置の製造方法におけるテープ取り除き工程の具体的手段を説明するための図である。It is a figure for demonstrating the specific means of the tape removal process in the manufacturing method of the semiconductor device of a present Example. 本実施例の半導体装置の応用例について説明するための図である。It is a figure for demonstrating the application example of the semiconductor device of a present Example. 本実施例の半導体装置における各部分の厚さを示した図である。It is the figure which showed the thickness of each part in the semiconductor device of a present Example. 本発明の他の実施例であるCOB型、P/B−LCC型の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the COB type | mold and P / B-LCC type | mold semiconductor device which are the other Examples of this invention. 本実施例の半導体装置を積層する場合について説明するための図である。It is a figure for demonstrating the case where the semiconductor device of a present Example is laminated | stacked. 本実施例の半導体装置の応用例について説明するための図である。It is a figure for demonstrating the application example of the semiconductor device of a present Example. 本実施例の金型を用いた半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device using the metal mold | die of a present Example.

符号の説明Explanation of symbols

1…リードフレーム(フレーム枠の記載を除いてある)
2、2a…接着テープ
3…半導体素子
4…ワイヤ
5…樹脂
10…突き上げ針
11…リードフレームの枠押さえ
12…テープはぎ取り金型
30、30a…プリント基板
35…仮固定治具
36…接着剤
40…金型の上型
41…金型の下型。
1 ... Lead frame (except for frame frame)
2, 2a ... Adhesive tape 3 ... Semiconductor element 4 ... Wire 5 ... Resin 10 ... Push-up needle 11 ... Frame holder of lead frame 12 ... Tape stripping mold 30, 30a ... Printed circuit board 35 ... Temporary fixing jig 36 ... Adhesive 40 ... Mold upper mold 41 ... Mold lower mold.

Claims (4)

半導体素子と、前記半導体素子を挟んでその両側に配置されたリードと、前記各リードの一方の面と対応する前記半導体素子の電極とをそれぞれ接続するワイヤと、前記半導体素子と前記ワイヤと前記リードを封止する樹脂とによって構成され、前記半導体素子の裏面と前記各リードの他方の面が同一面になるように配置され前記封止樹脂から露出した構成を有することを特徴とする半導体装置。 A semiconductor element, leads disposed on both sides of the semiconductor element, wires connecting one surface of each lead to the electrode of the semiconductor element, the semiconductor element, the wire, and the wire is constituted by a resin for sealing the lead, the semiconductor device backside and the other surface of each of said leads of said semiconductor device is characterized by having a structure that is exposed from the disposed the sealing resin so that the same surface . 半導体素子と、前記半導体素子を挟んでその両側に配置されたリードと、前記各リードと対応する前記半導体素子の電極とをそれぞれ接続するワイヤと、前記半導体素子と前記ワイヤと前記リードを封止する樹脂とによって構成され、前記半導体素子の裏側は樹脂封止部から露出しており、前記樹脂封止部側を下側にしてマウントし、前記半導体素子の裏側露出した構成としたことを特徴とする半導体装置。 A semiconductor element; leads disposed on both sides of the semiconductor element; wires connecting the electrodes of the semiconductor element corresponding to the leads; and the semiconductor element, the wire, and the lead sealed is constituted with the resin to the backside of the semiconductor element is exposed from the resin sealing portion, said resin sealing portion and the lower mount and the structure exposed to the back side of the semiconductor element A featured semiconductor device. 半導体素子と、前記半導体素子を挟んでその両側に配置されたリードと、前記各リードと対応する前記半導体素子の電極とをそれぞれ接続するワイヤと、前記半導体素子と前記ワイヤと前記リードが樹脂により封止され、前記半導体素子の裏側は樹脂封止部から露出するように構成されており、前記樹脂封止部側を下側にしてマウントされ、前記半導体素子の裏側露出面に放熱板が貼り付けられたことを特徴とする半導体装置。   A semiconductor element; leads disposed on both sides of the semiconductor element; wires connecting the electrodes of the semiconductor element corresponding to the leads; and the semiconductor element, the wire, and the lead made of resin. It is sealed, and the back side of the semiconductor element is configured to be exposed from the resin sealing part, mounted with the resin sealing part side facing down, and a heat sink is attached to the back side exposed surface of the semiconductor element. A semiconductor device characterized by being attached. 半導体素子と、前記半導体素子を挟んでその両側に配置されたリードと、前記各リードと対応する前記半導体素子の電極とをそれぞれ接続するワイヤと、前記半導体素子と前記ワイヤと前記リードを封止する樹脂とによって構成された半導体装置を複数個積層して構成した半導体装置積層体であって、前記半導体装置のそれぞれにおいて、前記リードは折り曲げられ、かつ前記半導体素子の裏面と前記各リードのインナーリードの一面が同一面になるように配置され前記封止樹脂から露出し、積層した上の前記半導体装置の前記リードのアウターリードは積層した下の前記半導体装置の前記リードのアウターリードよりも長くなって先端を前記下の半導体装置の前記アウターリードの先端の外側に位置させ、上下の半導体装置のアウターリードの先端の一面が同一面となる構成を有してなることを特徴とする半導体装置積層体。 A semiconductor element; leads disposed on both sides of the semiconductor element; wires connecting the electrodes of the semiconductor element corresponding to the leads; and the semiconductor element, the wire, and the lead sealed A plurality of semiconductor devices formed by laminating a plurality of semiconductor devices, wherein in each of the semiconductor devices, the lead is bent, and the back surface of the semiconductor element and the inner of each lead exposed from disposed the sealing resin as one side of the lead is the same surface, the lead of the outer leads of the semiconductor device on a laminate is longer than the lead of the outer leads of the semiconductor device under laminated The tip is positioned outside the tip of the outer lead of the lower semiconductor device, and the outer The semiconductor device stack one surface of the tip and characterized by having a structure in which the same plane.
JP2004009253A 2004-01-16 2004-01-16 Semiconductor device Expired - Fee Related JP3831380B2 (en)

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