JP3830803B2 - Manufacturing method of electronic circuit unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing an electronic circuit unit in which chip components are mounted on a substrate, and in particular, after mounting a large number of chip components on a large substrate, the large substrate is subdivided to obtain a large number. The present invention relates to a method for manufacturing an electronic circuit unit.
[0002]
[Prior art]
FIG. 3 is a cross-sectional view of an electronic circuit unit used as, for example, a high-frequency device. This electronic circuit unit includes a substrate 1 made of an insulating material such as glass epoxy resin and a wiring pattern 2 provided on the substrate 1. The chip component 3 is soldered to the solder land 2a. The substrate 1 is formed by subdividing the large-sized substrate 1A. As shown in FIG. 4, the large-sized substrate 1A is formed in a square shape. The inner region excluding the peripheral portion of the large-sized substrate 1A is a component mounting area S. In this component mounting area S, a large number of conductive patterns corresponding to the wiring pattern 2 and the solder land 2a of the substrate 1 are formed. Each set of conductive patterns is arranged in a matrix.
[0003]
FIG. 5 illustrates a known manufacturing process of an electronic circuit unit. First, as shown in FIG. 5A, each solder land formed in the component mounting area S of the large substrate 1A. After the cream solder is applied to 2a, the large substrate 1A is transported onto the base board 4 of the mounter, and the peripheral portion of the large substrate 1A is sandwiched from the side by the side clamp 5 and positioned on the base board 4. Next, as shown in FIG. 2B, a large number of chip components 3 are mounted on the corresponding solder lands 2a by vacuum suction. Thereafter, the large substrate 1 is transported to a reflow furnace, and the cream solder is melted in the reflow furnace to solder the electrodes 3a of the chip components 3 to the corresponding solder lands 2a. Thereafter, the large-sized substrate 1 is subdivided into a matrix along the vertical and horizontal dividing lines P1 and P2, so that a large number of electronic circuit units having the chip component 3 mounted on the substrate 1 are obtained as shown in FIG. The
[0004]
[Problems to be solved by the invention]
By the way, the large-sized substrate 1A used in the above-described manufacturing process is not necessarily flat. In particular, as the area of the large-sized substrate 1A increases, warping tends to occur more easily. In this case, if the warpage of the large substrate 1A is generated so as to protrude downward, the peripheral portion of the large substrate 1A is pressed downward by the side clamp 5 to substantially correct the warpage of the large substrate 1A. can do. However, if the warping of the large substrate 1A occurs so as to be convex upward, the warping of the large substrate 1A cannot be corrected by the side clamp 5, and the lower surface of the large substrate 1A as shown in FIG. The center is in a state of being largely lifted from the base board 4. As a result, when the chip component 3 is mounted on the large substrate 1A, the large substrate 1A may be deformed downward by an excessive pushing force, and the chip component 3 may be displaced with respect to the solder land 2a. If the chip component 3 is mounted with the position shifted in this manner, solder balls may be generated during subsequent reflow soldering, or the chip component 3 may be pulled up to one solder land 2a side and stand up. As a result, the yield of the electronic circuit unit is reduced.
[0005]
The present invention has been made in view of the actual situation of the prior art, and an object thereof is to provide a method of manufacturing an electronic circuit unit having a high yield by correcting warping of a large-sized substrate.
[0006]
[Means for Solving the Problems]
In the method for manufacturing an electronic circuit unit according to the present invention, a large board placed on a base board is clamped and positioned from the side, and an arbitrary place in a component mounting area of the large board is directed from above to the base board. In this state, after mounting a large number of chip components on the component mounting area excluding the pressed portion, the electronic circuit unit is configured to subdivide the large substrate and take a large number of substrates on which the chip components are mounted . In the manufacturing method, a plurality of locations in the component mounting area of the large-sized substrate are formed as dummy spaces on which chip components are not mounted, a copper foil pattern is formed on the entire surface of the dummy spaces, and the dummy spaces are moved upward by pressing pins. It was made to press from .
[0007]
If comprised in this way, since the curvature of a large-sized board | substrate can be corrected at the time of mounting of chip components, it can prevent that chip components displace with respect to the solder land 2a by an excessive pushing force, and a yield improves. In addition, a plurality of locations in the component mounting area of the large-sized substrate is a dummy space where chip components are not mounted, and a copper foil pattern is formed on the entire surface of the dummy space, and these dummy spaces are pressed from above by pressing pins. It is possible to reliably prevent the large substrate from being damaged by the pressing force from the pressing pin, and to further increase the yield.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a large-sized substrate, FIG. 2 is an explanatory view showing a manufacturing process of an electronic circuit unit, and corresponds to FIGS. The parts are given the same reference numerals.
[0010]
As shown in FIG. 1, a large substrate 1 </ b> A made of an insulating material such as glass epoxy resin is formed in a square shape, and an inner region excluding the peripheral edge portion is a component mounting area S. In this component mounting area S, a large number of conductive patterns having wiring patterns 2 and solder lands 2a are formed, and the conductive patterns of each set are arranged in a matrix. However, hatched portions in the figure are dummy spaces 6, and the dummy spaces 6 are set at a plurality of locations including the vicinity of the center of the component mounting area S. Although the wiring pattern 2 and the solder land 2a may be formed in the dummy space 6, since the chip component 3 is not mounted in the dummy space 6 as will be described later, in this embodiment, the entire surface of the large substrate 1A is formed. When the conductive pattern is formed by etching the copper foil pattern provided on the dummy space 6, the copper foil pattern is left exposed on the entire surface of the dummy space 6.
[0011]
A manufacturing process for taking a large number of individual electronic circuit units from the large substrate 1A shown in FIG. 1 will be described. First, after applying cream solder to each solder land 2a formed in the component mounting area S of the large substrate 1A. As shown in FIG. 2 (a), the large substrate 1A is transferred onto the base board 4 of the mounter, and the periphery of the large substrate 1A is sandwiched from the side by the side clamp 5 and positioned on the base board 4. To do. In the present embodiment example, the base board 4 is configured by a large number of backup pins 4a having the same height at the upper end surface, and the lower surface of the large-sized substrate 1A is supported by the backup pins 4a. A base board 4 similar to the conventional example described above may be used. At this time, if the warpage of the large substrate 1A occurs so as to protrude downward, the warp of the large substrate 1A is corrected by pressing the peripheral portion of the large substrate 1A downward with the side clamp 5. However, if the warping of the large-sized substrate 1A is generated so as to protrude upward, the center of the lower surface of the large-sized substrate 1A is largely lifted from the base board 4 as shown in FIG. .
[0012]
Next, as shown in FIG. 2 (b), each dummy space 6 of the large substrate 1A is pressed downward by the pressing pin 7 and the lower surface of the large substrate 1A is pressed against the upper end surface of each backup pin 4a. The warpage of the convex large-sized substrate 1A is corrected. At this time, since the copper foil pattern is formed on the entire surface of each dummy space 6, it is possible to reliably prevent the large substrate 1A from being damaged by the pressing force from the pressing pin 7. Next, as shown in FIG. 3C, a large number of chip components 3 are mounted on the corresponding solder lands 2a by vacuum suction. In this case, the chip component 3 is not mounted on the dummy space 6 pressed by the pressing pin 7.
[0013]
Thereafter, the large substrate 1 is transferred to a reflow furnace, and the solder 3 is soldered to the solder lands 2a by melting cream solder in the reflow furnace. Thereafter, as in the conventional example described above, a large substrate 1 is subdivided into a matrix along vertical and horizontal dividing lines P1 and P2, so that a large number of electronic circuit units having chip components 3 mounted on the individual substrates 1 are obtained. A piece is taken (see FIG. 3). In this case, the dummy space 6 of the large board 1 is discarded without being used as a product, but the proportion of the dummy space 6 occupying the total area of the component mounting area S is extremely small, so the discarded portion is extremely small. It becomes.
[0014]
According to the above-described embodiment, the large substrate 1A placed on the base board 4 is positioned by being sandwiched from the side by the side clamp 5 and set at a plurality of locations in the component mounting area S of the large substrate 1A. Since the formed dummy space 6 is pressed from above with the pressing pin 7, each chip component 3 can be mounted at a predetermined position in a state where the warpage of the large substrate 1A is corrected. Therefore, it is possible to prevent the chip component 3 from being displaced from the solder land 2a by an excessive pushing force at the time of mounting, and to eliminate defects such as the generation of solder balls after reflow and the rising of the chip component 3, and accordingly. The yield of the electronic circuit unit can be increased.
[0015]
Further, since the wiring pattern 2 and the solder land 2a are not formed in the dummy space 6 and the copper foil pattern is exposed on the entire surface of the dummy space 6, the pressing force from the pressing pin 7 is applied to the large substrate 1A via the dummy space 6. In addition to reliably preventing damage to the large substrate 1A, when the large substrate 1A is subdivided into individual substrates 1, the product substrate and the discarded substrate can be easily sorted. Can do.
[0016]
【The invention's effect】
The present invention is implemented in the form as described above, and has the following effects.
[0017]
The large board mounted on the base board is clamped from the side and positioned, and any part in the component mounting area of this large board is pressed from above toward the base board. You can mount the chip components in correction state at a predetermined position of the component mounting area, and therefore prevents the chip components to misalignment for the solder run de by excessive pushing force, the solder after reflow Defects such as ball generation and chip component standing can be eliminated, yield can be increased , and multiple locations within the component mounting area of the large-sized board are made dummy spaces where chip components are not mounted, and the entire dummy space In order to form a copper foil pattern and press the dummy space from above with a pressing pin, the pressing force from the pressing pin Furthermore it is possible to increase the yield can be prevented reliably that determine the substrate may be damaged.
[Brief description of the drawings]
FIG. 1 is a plan view of a large substrate used in an embodiment.
FIG. 2 is an explanatory view showing a manufacturing process of the electronic circuit unit according to the embodiment.
FIG. 3 is a cross-sectional view of an electronic circuit unit.
FIG. 4 is a plan view of a large-sized substrate.
FIG. 5 is an explanatory view showing a manufacturing process of an electronic circuit unit according to a conventional example.
FIG. 6 is an explanatory diagram showing a problem of a conventional example.
[Explanation of symbols]
1A large-sized substrate 2 wiring pattern 2a solder land 3 chip component 4 base board 4a backup pin 5 side clamp 6 dummy space 7 pressing pin S component mounting area P1, P2 dividing line

Claims (1)

The large board mounted on the base board is clamped and positioned from the side, and an arbitrary place in the component mounting area of the large board is pressed from above toward the base board, and in this state, the pressing part is A method of manufacturing an electronic circuit unit in which a large number of chip components are mounted on a component mounting area excluding, and then the large substrate is subdivided to obtain a large number of substrates on which chip components are mounted .
A plurality of locations in the component mounting area of the large substrate are used as dummy spaces in which chip components are not mounted, a copper foil pattern is formed on the entire surface of the dummy spaces, and these dummy spaces are pressed from above by pressing pins. A method for manufacturing an electronic circuit unit.

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