JP3822194B2 - Data playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generates a sampling clock phase-synchronized with a reproduction signal from a reproduction signal read from an optical recording medium such as an optical disk by a PLL circuit, and automatically adjusts the frequency characteristic of the reproduction signal by an adaptive equalization circuit. The present invention relates to a data reproducing apparatus.
[0002]
[Prior art]
In recent years, development of reproducing apparatuses that reproduce data recorded on various recording media such as a DVD has been actively performed.
[0003]
In general, in a reproducing apparatus for reproducing information recorded on an optical disk, a reference clock that is phase-synchronized with the reproduced signal is generated by a PLL (Phase-Locked Loop) circuit based on the reproduced signal read by the optical pickup. Thus, a process of taking bit synchronization is executed.
[0004]
In the reproducing apparatus, the reproduction signal is equalized by an equalization circuit, the reproduction signal subjected to the equalization process is binarized, and recorded data is reproduced from the binarized reproduction signal.
[0005]
Note that equalization processing refers to changing the frequency characteristics (amplitude or phase) of a reproduction signal based on a parameter indicating a predetermined equalization characteristic. That is, the reproduction signal shows a predetermined equalization characteristic by the above equalization processing. The equalization characteristic here means the frequency characteristic of the reproduction signal for realizing an optimum impulse response.
[0006]
Furthermore, even if there are variations in the characteristics (electrical and mechanical characteristics) of the optical recording medium and the playback device, the optimum equalization characteristics corresponding to the differences in the characteristics of the optical recording medium and playback device are automatically obtained. An adaptive equalization circuit that adaptively controls the above parameters may be used (for example, Patent Document 1). Here, adaptive control refers to automatic adjustment of the above parameters to an optimal state based on an output reproduction signal.
[0007]
[Patent Document 1]
JP-A-9-245435 (Claim 3)
[0008]
[Problems to be solved by the invention]
However, in a reproduction apparatus having an adaptive equalization circuit, if the reproduction signal input to the adaptive equalization circuit is abnormal, an equalization characteristic adjustment unit that performs adaptive control may malfunction. The reason for this will be described below.
[0009]
In general, the adaptive equalization circuit realizes adaptive control by binarizing a reproduction signal output from the adaptive equalization circuit and adjusting the parameters based on the binarized reproduction signal. That is, the reproduced signal to be output is fed back.
[0010]
Therefore, if there is an abnormality in the reproduction signal input to the adaptive equalization circuit, the parameter is adjusted based on the abnormal reproduction signal, so the parameter is abnormally adjusted. As a result, the adaptive equalization circuit further outputs an abnormal reproduction signal, the reproduction signal cannot be appropriately binarized, and the operation of the adaptive equalization circuit falls into a vicious circle.
[0011]
That is, once adaptive control is performed based on a parameter whose adjustment has greatly deviated, the adaptive equalization circuit falls into a so-called divergent state where the parameter cannot be automatically returned to the optimum state.
[0012]
In this respect, in the reproduction apparatus of Patent Document 1, an error is detected by an error detection circuit for the purpose of avoiding the divergence state, and if the error amount of the reproduction signal is a predetermined amount or more, an adaptive equalization circuit A method of resetting the predetermined parameter in FIG.
[0013]
Here, according to the above method, in order to detect the error amount based on the decoded reproduction signal, it is necessary to configure an error detection circuit in the subsequent stage of the adaptive equalization circuit, the binarization circuit, and the decoder. That is, the error detection circuit is provided at a later stage than the adaptive equalization circuit.
[0014]
Therefore, according to the above method, the error amount is detected based on the reproduction signal output from the adaptive equalization circuit, and the error amount of the reproduction signal input to the adaptive equalization circuit exceeds a predetermined amount. There may still be a situation where the adaptive control of the predetermined parameter is executed. Therefore, there arises a problem that the divergence of the adaptive equalization circuit cannot be prevented in advance.
[0015]
The present invention has been made in view of the above problems, and an object of the present invention is a reproducing apparatus that performs an equalization process of a reproduction signal by an adaptive equalization circuit, and prevents the divergence of the adaptive equalization circuit in advance. It is to provide a playback device that can be used.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the data reproducing apparatus of the present invention has predetermined phase error detection means for detecting the absolute value of the phase error between the reproduction signal read from the optical recording medium and the reference clock for the reproduction signal. An equalizing means for equalizing and outputting the reproduced signal based on the equalization characteristic indicated by the parameter, and a parameter adjusting means for adjusting the parameter based on the reproduced signal output by the equalizing means. The parameter adjustment means is characterized in that when the absolute value of the phase error is greater than or equal to a predetermined threshold, the parameter adjustment amount is suppressed more than when the absolute value is smaller than the predetermined threshold.
[0017]
In general, it can be said that the absolute value of the phase error of the reproduction signal with respect to the reference clock and the error amount of the reproduction signal have a positive correlation. Therefore, it can be determined that the larger the absolute value of the phase error of the reproduced signal with respect to the reference clock, the larger the error amount of the reproduced signal.
[0018]
According to the above configuration, the equalization means equalizes and outputs the reproduction signal based on the equalization characteristic indicated by the predetermined parameter, and the parameter adjustment means uses the reproduction signal output by the equalization means. The above parameters are adjusted. Further, the parameter adjustment means suppresses the adjustment amount of the parameter when the absolute value of the phase error is greater than or equal to a predetermined threshold value than when the absolute value is smaller than the predetermined threshold value. Thereby, since the adjustment of the parameter based on the reproduction signal is suppressed when the error amount of the reproduction signal becomes a certain level or more, the divergence of the equalizing means can be suppressed in advance.
[0019]
More specifically, according to the above configuration, the phase error detection unit does not need to be provided at the subsequent stage of the equalization unit, and therefore, when the error amount of the reproduction signal before being input to the equalization unit becomes a certain level or more. The adjustment amount of the parameter can be suppressed, and the divergence of the equalizing means can be suppressed in advance. In this respect, in Patent Document 1 in which an error detection circuit must be provided in the subsequent stage of the adaptive equalization circuit, the error amount is detected based on the reproduction signal output from the adaptive equalization circuit. Even after the error amount of the input reproduction signal exceeds a certain level, the predetermined parameter is adjusted, and the divergence of the adaptive equalization circuit cannot be prevented.
[0020]
In addition to the above configuration, the data reproducing apparatus of the present invention is characterized in that the parameter adjusting means sets the parameter adjustment amount to zero when the absolute value of the phase error is equal to or larger than a predetermined threshold value.
[0021]
According to the above configuration, when the absolute value of the phase error is equal to or greater than a predetermined threshold, the adjustment amount of the parameter is set to zero. Thereby, when the absolute value of the phase error is equal to or greater than a predetermined threshold, the adjustment of the parameter can be prohibited, and the divergence of the adaptive equalization circuit can be further prevented.
[0022]
In the data reproducing apparatus of the present invention, in addition to the above configuration, the phase error detecting means samples the reproduction signal with a time width indicated by the reference clock, and also samples the reproduction signal immediately before the zero cross and the reproduction signal. The absolute value of the phase error is detected based on the sampling value immediately after the zero crossing of the signal.
[0023]
The reproduced signal is sampled with a time width indicated by the reference clock. Therefore, the ratio between the sampling value immediately before the zero crossing of the reproduction signal and the sampling value immediately after the zero crossing approximates the ratio of the time interval before and after the zero crossing of the reproduction signal in the time width. Therefore, based on the sampling value immediately before the zero cross of the reproduction signal and the sampling value immediately after the zero cross, the phase error amount between the reproduction signal and the reference clock can be detected, and the absolute value of the phase error can also be detected.
[0024]
In the data reproducing apparatus of the present invention, in addition to the above-described configuration, the phase error detecting means may be configured to detect the reproduction signal based on a sampling value immediately before the zero cross of the reproduction signal and a sampling value immediately after the zero cross of the reproduction signal. An abnormality is detected.
[0025]
When a phase error occurs between the reproduced signal and the reference clock, it can be determined that the reproduced signal is in an abnormal state. Therefore, an abnormal state of the reproduction signal can be detected based on the sampling value immediately before the zero crossing of the reproduction signal and the sampling value immediately after the zero crossing.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
An optical disk reproducing apparatus using an adaptive equalization circuit as one embodiment of the present invention will be described below.
[0027]
FIG. 1 is a block diagram of an optical disc playback apparatus (data playback apparatus) 100 that plays back data recorded on the optical disc 1. Specific examples of the optical disc 1 include CD (Compact Disc), CD-R (CD Recordable), MD (Mini Disc), CD-RW (CD ReWritable), DVD (Digital Video Disk), DVD-R (DVD Recordable). ), DVD-RW (DVD ReWritable), DVD + RW (DVD ReWritable), and the like.
[0028]
The optical disk reproducing apparatus 100 includes a spindle motor 2, an optical pickup 3, an amplifier 4, a sampling clock generation circuit 5, an A / D converter 6, a phase error detector 7, an adaptive equalization circuit 8, and a binarization circuit 9. The
[0029]
The spindle motor 2 supports the optical disc 1 and controls the rotation of the optical disc 1. The optical pickup 3 reads the data recorded on the optical disc 1 by irradiating the optical disc 1 with laser light, receiving the light reflected from the optical disc 1, and converting the received light into an electrical signal. Is for. The electric signal is sent from the optical pickup 3 to the amplifier 4.
[0030]
The amplifier 4 is for outputting the reproduction signal S1 by amplifying the electric signal sent from the optical pickup 3. The reproduced signal S1 is output from the amplifier 4 and then sent to the sampling clock generation circuit 5 and the A / D converter 6.
[0031]
The sampling clock generation circuit 5 is a circuit for generating a sampling clock (reference clock) CLK having a frequency equal to the bit rate of the reproduction signal S1 and phase-synchronized with the reproduction signal S1. The sampling clock generation circuit 5 is configured by a PLL (Phase-Locked Loop) circuit. The sampling clock CLK is output to the A / D converter 6, the phase error detector 7, the adaptive equalization circuit 8, and the binarization circuit 9 after being output from the sampling clock generation circuit 5.
[0032]
An A / D (Analog to Digital) converter 6 quantizes the reproduction signal S1 into 8-bit digital data at the timing of the sampling clock CLK, for example, at the rising edge. Hereinafter, the quantized digital data is referred to as a quantized reproduction signal S2.
[0033]
The quantized reproduction signal S2 is output from the A / D converter 6 and then sent to the phase error detector 7 and the adaptive equalization circuit 8. In this embodiment, the quantized reproduction signal S2 is 8 bits. However, the quantized reproduction signal S2 is not particularly limited to 8 bits, and may be, for example, 12-bit or 16-bit digital data.
[0034]
The phase error detector (phase error detection means) 7 detects a shift in timing for quantizing the reproduction signal S1 using the quantized reproduction signal S2, that is, the sampling clock CLK and the reproduction signal S1 (read from the optical recording medium). This is a circuit for detecting a phase error from the reproduced signal.
[0035]
Furthermore, the phase error detector 7 of the present embodiment calculates the absolute value of the phase error, and activates the adaptation permission signal EN if the absolute value is less than the phase error threshold, and the absolute value is If the phase error threshold value is exceeded, the adaptive permission signal EN is deactivated and the adaptive permission signal EN is sent to the adaptive equalization circuit 8. The configuration of the phase error detector 7 will be described in detail later.
[0036]
The binarization circuit 9 outputs a binarized reproduction signal S4 obtained by binarizing the post-equalization quantized reproduction signal S3 output from the adaptive equalization circuit 8, and simultaneously applies a part of the binarized reproduction signal S4. This circuit feeds back to the equalization circuit 8.
[0037]
The adaptive equalization circuit (equalization means, parameter adjustment means) 8 equalizes and outputs the quantized reproduction signal S2 based on tap coefficients (predetermined parameters) indicating predetermined equalization characteristics. The adaptive equalization circuit 8 performs adaptive control of the equalization characteristic by automatically adjusting the tap coefficient based on the binarized reproduction signal (reproduction signal output from the equalization means) S4.
[0038]
Further, the adaptive equalization circuit 8 is set to suppress the adjustment amount of the parameter when the adaptation permission signal EN is inactive compared to when the adaptation permission signal EN is active.
[0039]
Here, it can be said that the absolute value of the phase error of the reproduction signal S1 with respect to the sampling clock CLK and the error amount of the reproduction signal S1 have a positive correlation. Therefore, it can be determined that the larger the absolute value of the phase error of the reproduction signal S1 with respect to the sampling clock, the larger the error amount of the reproduction signal S1.
[0040]
Therefore, according to the above configuration, when the error amount of the reproduction signal S1 exceeds a certain level, the adjustment of the parameter based on the binarized reproduction signal S4 can be suppressed, and the divergence of equalization characteristics in the adaptive equalization circuit 8 can be suppressed. Can be suppressed.
[0041]
Next, a configuration example of the phase error detector 7 will be described. FIG. 2 is a block diagram showing a configuration example of the phase error detector 7. The phase error detector 7 shown in FIG. 2 is a clock-synchronized digital circuit that operates at the timing indicated by the sampling clock CLK.
[0042]
The phase error detector 7 includes a register 21, a ROM (Read Only Memory) 22, an LPF (Low Pass Filter) 23, a digital comparator 24, and a ROM 25.
[0043]
The sampling clock CLK sent from the sampling clock generation circuit 5 is inputted to the register 21, and the quantized reproduction signal S 2 sent from the A / D converter 6 is inputted to the register 21 and the ROM 22.
[0044]
The register 21 is a set of Philip flops, and is a delay circuit for delaying the quantized reproduction signal S2 by one clock based on the sampling clock CLK. The delayed quantized reproduction signal S2 ′ is sent to the ROM 22.
[0045]
The ROM 22 outputs a phase error signal indicating the absolute value of the phase error between the sampling clock CLK and the reproduction signal S1 based on the quantized reproduction signal S2 ′ delayed by one clock and the quantized reproduction signal S2 before the delay. This is a calculation memory. That is, the ROM 22 can be said to be a memory for calculating the absolute value of the phase error between the sampling clock CLK and the reproduction signal S1. The phase error signal output from the ROM 22 (the signal indicating the phase error) is sent to the LPF 23.
[0046]
As will be described later, when the quantized reproduction signal S2 ′ delayed by one clock and the quantized reproduction signal S2 before delay are input, the ROM 22 outputs a phase error signal indicating the absolute value of the phase error. Stores calculation data.
[0047]
The LPF (also referred to as a high-frequency cutoff digital filter) 23 is a digital filter for removing a wide-range noise component from the phase error signal and outputting it. The phase error signal output from the LPF 23 is sent to the digital comparator 24.
[0048]
The digital comparator 24 is a comparator for comparing the magnitudes of the digital data, and compares the phase error signal from the LPF 23 with the phase error threshold value (predetermined threshold value) read from the ROM 25. The digital comparator 24 outputs an active adaptation permission signal EN when the absolute value of the phase error indicated by the phase error signal is less than the phase error threshold, and when the absolute value of the phase error is greater than or equal to the phase error threshold. The inactive adaptation enable signal EN is set to be output.
[0049]
Next, the calculation data stored in the ROM 22 will be described in detail. FIG. 4 is a diagram showing a waveform indicating the reproduction signal S1, and white circles in the figure indicate the quantization reproduction signal S2 quantized (sampled) at the timing (time width) indicated by the sampling clock CLK.
[0050]
In FIG. 4, α indicates a sampling value (amplitude) immediately after the zero crossing of the reproduction signal S1, and β indicates a sampling value (amplitude) immediately before the zero crossing of the reproduction signal S1. Note that the ratio of α and β is substantially equal to the ratio of the time intervals tα and tβ before and after the zero crossing at the above timing.
[0051]
Therefore, since it can be determined that there is no phase error when tα = tβ, it can be determined that there is no phase error even when α = β. On the other hand, when α and β are not equal, it can be determined that there is a phase error.
[0052]
Here, the absolute value of the phase error | Pe |
| Pe | = | (α−β) / (| α | + | β |) | (1)
Can be obtained.
[0053]
Equation (1) is obtained by normalizing the phase error by (α−β) and dividing by | α | + | β |. The reason for normalizing in this way is to suppress the change in the calculation result due to the change in the amplitude of the reproduction signal S1. When the change in the amplitude of the reproduction signal S1 is suppressed by configuring the AGC before the ROM 22, division by | α | + | β | is unnecessary.
[0054]
Further, the quantized reproduction signal S2 ′ after the delay process by the register 21 is delayed by one clock from the quantized reproduction signal S2 before the delay process, and α and β in FIG. 4 are separated by one clock. There is. Therefore, the quantized reproduction signal S2 before delay processing by the register 21 can be set to α, and the quantized reproduction signal S2 ′ after delay processing can be set to β.
[0055]
Then, the ROM 22 is set so that α is input to the upper 8 bits of the address in the ROM 22 and β is input to the lower 8 bits of the ROM 22. Further, the calculation result of (1) in all combinations of the α code and the β code is stored in the ROM 22. Further, when α and β are input to the ROM 22, the ROM 22 is set so that the calculation result of (1) corresponding to the input α and β is output.
[0056]
According to the ROM 22 as described above, when the signs of α and β to be input are different from each other, a phase error signal indicating the absolute value | Pe | of the phase error can be output. If the input α and β have the same sign, the ROM 22 outputs a phase error signal indicating “0 (no phase error)”.
[0057]
The absolute value | Pe | of the phase error calculated as described above is not only when the PLL circuit in the sampling clock generation circuit 5 is locked, but also when the reproduction signal S1 is disturbed not only by the pull-in process but also by a defect on the optical disc 1. Even if it is, it becomes a large value. This is because the amplitude value before and after the zero crossing is disturbed due to the defect, and the ratio of α and β is destroyed even if the sampling clock CLK is normal. Therefore, the phase error detector 7 also has a function as a defect detector.
[0058]
As described above, since the reproduction signal S1 is sampled with the time width indicated by the sampling clock, the sampling value (amplitude value) immediately before the zero cross and the sampling value (amplitude value) immediately after the zero cross of the reproduction signal S1 are obtained. The ratio approximates to the ratio of the time interval before and after the zero cross in the reproduction signal S1 in the above time width.
[0059]
Therefore, based on the sampling value immediately before the zero crossing of the reproduction signal S1 and the sampling value immediately after the zero crossing, that is, by executing the expression (1), the phase error amount between the reproduction signal S1 and the sampling clock CLK can be detected.
[0060]
In addition, when a phase error occurs between the reproduction signal S1 and the sampling clock CLK, it can be considered that the reproduction signal S1 is disturbed due to a defect on the optical disc 1. Therefore, the abnormal state of the reproduction signal can also be determined based on the sampling value immediately before the zero crossing of the reproduction signal S1 and the sampling value immediately after the zero crossing.
[0061]
Next, a configuration example of the adaptive equalization circuit 8 will be described. FIG. 3 is a block diagram showing the configuration of the adaptive equalization circuit 8. The adaptive equalization circuit 8 has a FIR type digital filter (FIR filter, equalization means) 31 as a main body. Then, adaptive control of equalization characteristics is executed by automatically adjusting tap coefficients C0, C1, and C2 given to the FIR digital filter 31 and exhibiting predetermined equalization characteristics. That is, the adaptive equalization circuit 8 of this embodiment is a 3-tap LMS type.
[0062]
Specifically, automatic adjustment of the tap coefficients C0, C1, and C2 is performed by a circuit having a configuration shown in FIG. 3 includes an FIR digital filter 31, a latency adjustment shift register 33, registers 34a, 34b, and 34c, tap coefficient supply means (parameter adjustment means) 40a, 40b, and 40c, a selector 38, and a selector. 312, an FIR digital filter (FIR filter) 32, a latency adjustment shift register 39, a subtractor 310, and a multiplier 311.
[0063]
The FIR digital filter 31 equalizes the input quantized reproduction signal S2 based on tap coefficients (predetermined parameters) C0, C1, and C2 supplied from the tap coefficient supply means 40a, 40b, and 40c. This is a digital filter that outputs a quantized reproduction signal S3 after equalization.
[0064]
The latency adjustment shift register 33 is a delay circuit that outputs an input quantized reproduction signal S2 with a predetermined clock delay.
[0065]
The registers 34a, 34b, and 34c are connected in series in this order, and are delay means for delaying an input signal by one clock and outputting it. Further, the register 34a and the tap coefficient adjusting means 40a are connected, the register 34b and the tap coefficient adjusting means 40b are connected, and the register 34c and the tap coefficient adjusting means 40c are connected.
[0066]
Here, the register 34a receives the quantized reproduction signal S2 output from the latency adjustment shift register 33, delays it by one clock, and outputs it to the register 34b and the tap coefficient supply means 40a. The register 34b delays the quantized reproduction signal S2 from the register 34a by one clock and outputs it to the register 34c and the tap coefficient supply means 40b. The register 34c delays the quantized reproduction signal S2 from the register 34b by one clock and outputs it to the tap coefficient supply means 40c.
[0067]
That is, the output of the register 34c is data that is 3 clocks past from the input of the register 34a, the output of the register 34b is data that is 2 clocks past the input of the register 34a, and the output of the register 34a is 1 from the input of the register 34a. Clock past data.
[0068]
Each tap coefficient supply means 40a, 40b, and 40c stores tap coefficients C0, C1, and C2 corresponding to the tap coefficient supply means 40a, 40b, and 40c, and tap coefficients C0, C1, and C2 based on the binarized reproduction signal S4 and the quantized reproduction signal S2. This is adaptive control means for automatically adjusting C1 and C2 (adaptive control). That is, the tap coefficient C0 is stored in the tap coefficient supply means 40a, the tap coefficient C1 is stored in the tap coefficient supply means 40b, and the tap coefficient C2 is stored in the tap coefficient supply means 40c.
[0069]
The selector 38 multiplies either the first gain adjustment constant or the second gain adjustment constant based on the adaptation permission signal EN (selection input S) from the digital comparator 24 included in the phase error detector 7. 311 is a circuit for outputting to 311. The second gain adjustment constant is set smaller than the first gain adjustment constant.
[0070]
Here, when the adaptation permission signal EN is active, the selector 38 outputs the first gain adjustment constant, and when the adaptation permission signal EN is inactive, the selector 38 outputs the second gain adjustment constant. Has been.
[0071]
The latency adjustment shift register 39 is a circuit for temporally adjusting the post-equalization quantized reproduction signal S3, which is the output of the FIR digital filter 31, and outputting it to the subtractor 310.
[0072]
The selector 312 is a circuit that converts the code indicated by the binarized reproduction signal S4, which is the output of the binarization circuit 9, into a predetermined code and outputs the code to the FIR digital filter 32. Specifically, the selector 312 converts “0” “1” data indicated by the binarized reproduction signal S4 into “−1” “1” data.
[0073]
The FIR type digital filter 32 is a digital filter for performing equalization processing on the binarized reproduction signal S4 sent from the selector 312 and outputting it to the subtractor 310. Note that tap coefficients for equalizing the binarized reproduction signal S4 output from the FIR digital filter 32 and the post-equalization quantized reproduction signal S3 having the optimum impulse response are set in the FIR digital filter 32. Has been.
[0074]
The subtractor 310 outputs an equalization error signal e by subtracting the post-equalization quantized reproduction signal S3 from the latency adjustment shift register 39 and the binary reproduction signal S4 from the FIR digital filter 32, This is a circuit for sending the output equalization error signal e to the multiplier 311.
[0075]
The multiplier 311 multiplies the first gain adjustment constant or the second gain adjustment constant, which is an output from the selector 38, and the equalization error signal e, which is an output from the subtractor 310, thereby obtaining an equalization error signal. e is a circuit for adjusting the gain of e. The gain-adjusted equalization error signal e is sent to the tap coefficient supply means 40a, 40b, and 40c.
[0076]
Next, each tap coefficient supply means 40a, 40b, 40c will be described. Since the tap coefficient supply units 40a, 40b, and 40c have the same configuration, only the tap coefficient supply unit 40a will be described below, and the description of the tap coefficient supply units 40b and 40c will be omitted.
[0077]
The tap coefficient supply means 40a includes a multiplier 35a, a register 36a, and an adder 37a.
[0078]
The multiplier 35a is a circuit for outputting the adjustment amount of the tap coefficient C0 by multiplying the equalization error signal e from the multiplier 311 and the quantized reproduction signal S2 delayed by the delay means. The output update amount is sent to the adder 37a.
[0079]
The register 36a is a memory for storing the tap coefficient C0. The adder 37a reads out the current tap coefficient C0 from the register 36a and adds an update amount output from the multiplier 35a to the read tap coefficient C0 to output an adjusted tap coefficient C0. It is. The adjusted tap coefficient C0 is stored in the register 36a.
[0080]
Next, the operation of the adaptive equalization circuit 8 shown in FIG. 3 will be described. Hereinafter, description of the tap coefficient supply means 40b and 40c is omitted.
[0081]
First, the FIR digital filter 31 equalizes the quantized reproduction signal S2 and outputs an equalized quantized reproduction signal S3. Then, the output post-equalization quantized reproduction signal S3 is temporally adjusted by the latency adjustment shift register 39 and input to the subtractor 310 for the calculation of the equalization error signal e.
[0082]
Also, the binarized reproduction signal S4 output from the binarization circuit 9 is converted from 1 and 0 data to 1 and −1 data by the selector 312. The converted binarized reproduction signal S4 is input to the FIR digital filter 32.
[0083]
Here, the tap coefficient of the FIR type digital filter 32 is set so that the output of the FIR type digital filter 32 is equalized with the post-equalization quantized reproduction signal S3 showing the optimum impulse response.
[0084]
Therefore, as long as there is no error in the binarized reproduction signal S4 output from the FIR type digital filter 32, the equalization error signal e output from the subtractor 310 is an equalized quantized reproduction signal S3 indicating an optimal impulse response. And the post-equalization quantized reproduction signal S3 output from the FIR digital filter 31.
[0085]
Then, the equalization error signal e output from the subtractor 310 is gain-adjusted by being multiplied by either the first gain adjustment constant or the second gain adjustment constant by the multiplier 311. Further, the gain-adjusted equalization error signal e is multiplied by the quantized reproduction signal S2 delayed by a clock unit by the multiplier 35a. Here, the output of the multiplier 35a corresponds to the adjustment amount of the tap coefficient C0.
[0086]
Further, the adjustment amount of the tap coefficient C0 is added to the current tap coefficient C0 stored in the register 36a by the adder 37a, and stored in the register 36a as the tap coefficient C0 after the addition adjustment (after update).
[0087]
According to the above configuration, when the absolute value of the phase error is smaller than the phase error threshold (the adaptive permission signal EN is active), the gain adjustment of the equalization error signal e is performed by the first gain adjustment constant. Further, when the absolute value of the phase error is equal to or larger than the phase error threshold (the adaptation permission signal EN is inactive), the gain adjustment of the equalization error signal e is performed by the second gain adjustment constant smaller than the first gain adjustment constant. It has become.
[0088]
Therefore, when the absolute value of the phase error is greater than or equal to the phase error threshold, the addition adjustment amount of the tap coefficient C0 can be made smaller than when the absolute value is smaller than the phase error threshold. That is, the adjustment amount of the tap coefficient C0, that is, the equalization characteristic, is suppressed when the absolute value of the phase error is equal to or larger than the phase error threshold than when the absolute value is smaller than the phase error threshold.
[0089]
In the above configuration, if the second gain adjustment constant is set to zero, the output from the multiplier 311 becomes zero when the absolute value of the phase error is equal to or greater than the phase error threshold, and therefore the adjustment amount of the tap coefficient C0. Becomes zero. Therefore, when the absolute value of the phase error is equal to or larger than the phase error threshold, the tap coefficient C0 is not adjusted, and the adaptive control of the tap coefficient C0, that is, the equalization characteristic can be prohibited.
[0090]
Further, the combination of the phase error detector 7 shown in FIG. 2 and the adaptive equalization circuit 8 shown in FIG. 3 can detect the phase error and simultaneously detect the abnormality of the reproduction signal S1 due to the defect. Can be prevented in advance.
[0091]
The phase error threshold described above will be described below.
[0092]
The “phase error” is not only detected due to a defect on the optical disc 1 but also may be detected due to a factor other than the defect. For example, the phase error is also detected by the medium noise of the optical disc 1, the photodetector noise, the circuit noise, and the jitter of the PLL circuit.
[0093]
Normally, the phase error detected due to factors other than the above-mentioned defects occurs sporadically and therefore does not cause the adaptive equalization circuit 8 to diverge. However, the phase error detected due to the defect occurs intensively for a long time, and causes the adaptive equalization circuit 8 to diverge.
[0094]
Therefore, in this embodiment, if the phase error threshold is set unnecessarily small, even in a situation where the phase error is detected due to a factor other than the above-described defect, that is, in a situation where the divergence of the adaptive equalization circuit 8 cannot occur. As a result, the adaptive control is suppressed, and there is a demerit that the purpose of the original adaptive control is hindered.
[0095]
On the other hand, if the phase error threshold value is set unnecessarily large, the adaptive control is not suppressed in a situation where the phase error is detected due to the defect, and the adaptive equalization circuit 8 diverges. Disadvantages arise.
[0096]
Therefore, as a method for setting the phase error threshold, a histogram showing the frequency distribution of the absolute value of the phase error is created in advance by experiment (for example, FIG. 5), and the absolute value of the phase error corresponding to half the maximum frequency is obtained. A value may be set as the phase error threshold. By setting the phase error threshold in this way, the balance between the advantages of adaptive control and the above-mentioned disadvantages can be kept optimal.
[0097]
The horizontal axis of the histogram of FIG. 5 indicates the absolute value of the phase error, and the vertical axis indicates the frequency of the phase error to be detected. According to this histogram, it can be seen that the frequency decreases as the absolute value of the phase error increases.
[0098]
In addition, when the above-described phase error threshold is set by the method described above, the value set by each device is different, but a value of about 0.25 is preferable according to the experiment conducted by the inventors of the present invention. Turned out to be. However, the phase error threshold value is not limited to a value in the vicinity of 0.25, but is a value that can be changed depending on the type and function of the apparatus.
[0099]
Note that the configuration examples of the phase error detector 7 and the adaptive equalization circuit 8 described above are merely examples, and it is needless to say that the design can be changed within the technical scope described in the claims.
[0100]
In addition, according to the equalization circuit that performs adaptive control by the conventional method, the gain adjustment multiplication constant is usually set so that the tap coefficient is converged by repeating the update of several hundred to several thousand clocks. Since the binarized playback signal is fed back to obtain the quantized playback signal after quantization, the sampling clock phase is abnormal, or the playback signal is abnormal for a long time due to a defect, etc. If the period that cannot be binarized continues for a long time, the period in which the value of the equalization error signal becomes abnormal continues for a long time, so that the tap coefficient is updated to an abnormal value. And once a tap coefficient becomes an abnormal value, it will fall into the vicious circle that normal binarization cannot be performed, and a tap coefficient will diverge.
[0101]
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
[0102]
【The invention's effect】
As described above, the data reproducing apparatus of the present invention includes phase error detection means for detecting the absolute value of the phase error between the reproduction signal read from the optical recording medium and the reference clock with respect to the reproduction signal, and predetermined parameters. Based on the equalization characteristic indicated by the reference signal, and an equalizing means for equalizing and outputting the reproduced signal, and a parameter adjusting means for adjusting the parameter based on the reproduced signal output by the equalizing means, The adjusting means is characterized in that when the absolute value of the phase error is greater than or equal to a predetermined threshold, the adjustment amount of the parameter is suppressed more than when the absolute value is smaller than the predetermined threshold.
[0103]
As a result, the adjustment of the parameter based on the reproduction signal is suppressed at the time when the error amount of the reproduction signal becomes equal to or greater than a certain value, so that the divergence of the equalizing means can be suppressed in advance.
[0104]
In addition to the above configuration, the data reproducing apparatus of the present invention is characterized in that the parameter adjusting means sets the parameter adjustment amount to zero when the absolute value of the phase error is equal to or larger than a predetermined threshold value.
[0105]
As a result, when the absolute value of the phase error is equal to or greater than a predetermined threshold value, the adjustment of the parameter can be prohibited, and the divergence of the adaptive equalization circuit can be further prevented.
[0106]
In the data reproducing apparatus of the present invention, in addition to the above configuration, the phase error detecting means samples the reproduction signal with a time width indicated by the reference clock, and also samples the reproduction signal immediately before the zero cross and the reproduction signal. The absolute value of the phase error is detected based on the sampling value immediately after the zero crossing of the signal.
[0107]
Thereby, based on the sampling value immediately before the zero crossing of the reproduction signal and the sampling value immediately after the zero crossing, the phase error amount between the reproduction signal and the reference clock can be detected, and the absolute value of the phase error can also be detected. Play.
[0108]
In the data reproducing apparatus of the present invention, in addition to the above-described configuration, the phase error detecting means may be configured to detect the reproduction signal based on a sampling value immediately before the zero cross of the reproduction signal and a sampling value immediately after the zero cross of the reproduction signal. An abnormality is detected.
[0109]
Thereby, based on the sampling value immediately before the zero crossing of the reproduction signal and the sampling value immediately after the zero crossing, an abnormal state of the reproduction signal can be detected.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an optical disk reproducing apparatus according to an embodiment.
2 is a block diagram showing a configuration of a phase error detector that is a component of the optical disc apparatus in FIG. 1. FIG.
3 is a block diagram showing a configuration of an adaptive equalization circuit that is a component of the optical disc apparatus in FIG. 1. FIG.
4 is a diagram showing a waveform of a reproduction signal in the optical disc apparatus of FIG. 1. FIG.
FIG. 5 is a histogram showing a frequency with respect to an absolute value of a phase error.
[Explanation of symbols]
5 Sampling clock generation circuit
6 A / D converter
7 Phase error detector (phase error detection means)
8 Adaptive equalization circuit (equalization means, parameter adjustment means)
9 Binarization circuit
31 FIR type digital filter (equalization means)
32 FIR type digital filter
33 Latency adjustment shift register
34a register
34b register
34c register
35a multiplier
36a register
37a Adder
38 selector
39 Latency adjustment shift register
40a Tap coefficient supply means (parameter adjustment means)
40b Tap coefficient supply means (parameter adjustment means)
40c Tap coefficient supply means (parameter adjustment means)
100 Optical disk playback device (data playback device)
310 Subtractor
311 multiplier
312 Selector

Claims (4)

Phase error detection means for detecting an absolute value of a phase error between a reproduction signal read from the optical recording medium and a reference clock with respect to the reproduction signal;
Equalization means for equalizing and outputting the reproduction signal based on equalization characteristics indicated by a predetermined parameter;
Parameter adjusting means for adjusting the parameters based on the reproduction signal output from the equalizing means,
The parameter adjustment means, when the absolute value of the phase error is greater than or equal to a predetermined threshold, suppresses the adjustment amount of the parameter more than when the absolute value is smaller than the predetermined threshold. 2. The data reproducing apparatus according to claim 1, wherein the parameter adjusting unit sets the adjustment amount of the parameter to zero when the absolute value of the phase error is equal to or greater than a predetermined threshold value. The phase error detecting means is
While sampling the reproduction signal in the time width indicated by the reference clock,
3. The data reproducing apparatus according to claim 1, wherein the absolute value of the phase error is detected based on a sampling value immediately before the zero crossing of the reproduction signal and a sampling value immediately after the zero crossing of the reproduction signal. . The phase error detecting means is
4. The data reproduction apparatus according to claim 3, wherein an abnormality of the reproduction signal is detected based on a sampling value immediately before the zero crossing of the reproduction signal and a sampling value immediately after the zero crossing of the reproduction signal.

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