JP3818402B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Nonvolatile semiconductor memory device and manufacturing method thereof Download PDF

Info

Publication number
JP3818402B2
JP3818402B2 JP29336396A JP29336396A JP3818402B2 JP 3818402 B2 JP3818402 B2 JP 3818402B2 JP 29336396 A JP29336396 A JP 29336396A JP 29336396 A JP29336396 A JP 29336396A JP 3818402 B2 JP3818402 B2 JP 3818402B2
Authority
JP
Japan
Prior art keywords
film
semiconductor memory
memory device
nonvolatile semiconductor
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29336396A
Other languages
Japanese (ja)
Other versions
JPH10125813A (en
Inventor
俊一 吉越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP29336396A priority Critical patent/JP3818402B2/en
Publication of JPH10125813A publication Critical patent/JPH10125813A/en
Application granted granted Critical
Publication of JP3818402B2 publication Critical patent/JP3818402B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Description

【0001】
【発明の属する技術分野】
本願の発明は、窒化膜と酸化膜との界面における捕獲準位に電荷を捕獲することによって情報を記憶する不揮発性半導体記憶装置及びその製造方法に関するものである。
【0002】
【従来の技術】
情報を電気的に書き換えることができ且つ電源を切っても情報を保持することができる不揮発性半導体記憶装置の一種として、絶縁膜と酸化膜との界面に存在する捕獲準位に電荷を捕獲してトランジスタの閾値電圧をシフトさせることによって情報を記憶する不揮発性半導体記憶装置がある。
【0003】
この不揮発性半導体記憶装置はMIOS(Metal Insulator Oxide Semiconductor)型やMOIOS(Metal Oxide Insulator Oxide Semiconductor)型と称されているが、絶縁膜としては主に窒化膜が用いられているので、これらは、特に、MNOS型やMONOS型と称されている。
【0004】
図2は、MONOS型の不揮発性半導体記憶装置の一従来例を示している。この一従来例では、Si基板(図示せず)上に、厚さが2nmであるトンネル用のSiO2膜11と、厚さが8nmであるSiN膜12と、厚さが4nmであるSiO2膜13とが順次に積層されており、更に、このSiO2膜13上にゲート電極としての多結晶Si膜(図示せず)等が形成されている。
【0005】
【発明が解決しようとする課題】
ところが、MNOS型やMONOS型の不揮発性半導体記憶装置では、大容量化のための微細化や低消費電力化のための低電圧動作化に伴って、1ビット当たりの面積やSiN膜12等の厚さが減少してきている。この結果、SiN膜12とSiO2膜11、13との界面の面積が減少すると共にSiN膜12中に含まれる捕獲準位量も減少することによって、捕獲電荷量が減少して記憶保持特性が低下していた。
【0006】
【課題を解決するための手段】
本願の発明による不揮発性半導体記憶装置は、窒化膜と酸化膜との界面における捕獲準位に電荷を捕獲することによって情報を記憶する不揮発性半導体記憶装置において、前記窒化膜中に酸化膜が含まれており、この酸化膜が前記界面に沿って離散的に広がっていることを特徴としている
【0007】
本願の発明による不揮発性半導体記憶装置の製造方法は、窒化膜と酸化膜との界面における捕獲準位に電荷を捕獲することによって情報を記憶する不揮発性半導体記憶装置の製造方法において、前記窒化膜中に点状にイオン注入した酸素によって前記窒化膜中に酸化膜を形成することを特徴としている
【0008】
本願の発明による不揮発性半導体記憶装置では、窒化膜中に酸化膜が含まれているので、同じ平面的な面積で比べると、窒化膜と酸化膜との界面の面積が広くて、捕獲電荷量が多い。しかも、窒化膜中の酸素に起因する深い捕獲準位も多く形成されているので、捕獲された電荷が自然放出されにくい。
【0009】
また、窒化膜中の酸化膜がそれらの界面に沿って離散的に広がっているので、窒化膜中の酸化物の含有量が同じでも、窒化膜と酸化膜との界面の面積が更に広くて、捕獲電荷量が更に多い
【0010】
本願の発明による不揮発性半導体記憶装置の製造方法では、窒化膜中に酸化膜を形成しているので、同じ平面的な面積が比べると、窒化膜と酸化膜との界面の面積を広くして、捕獲電荷量を多くすることができる。しかも、窒化膜中の酸素に起因する深い捕獲準位も多く形成されるので、捕獲された電荷が自然放出されにくくすることができる。
【0011】
また、窒化膜中に酸化膜を形成する際に酸素を窒化膜中に点状にイオン注入して、窒化膜との界面に沿って離散的に広がる酸化膜を形成することができるので、イオン注入する酸素の量が同じでも、窒化膜と酸化膜との界面の面積を更に広くして、捕獲電荷量を更に多くすることができる。
【0012】
【発明の実施の形態】
以下、本願の発明の第1及び第2実施形態を、図1を参照しながら説明する。第1実施形態では、例えば、抵抗加熱型の熱処理炉にO2/N2=300SCCM/10SLMのガスを供給してSi基板(図示せず)を希釈酸化することによって、このSi基板の表面に厚さが2nmのSiO2膜11を形成する。
【0013】
次に、例えば、抵抗加熱型の減圧CVD装置にNH3/SiH2Cl2=2000SCCM/50SCCMのガスを70Paで供給し、760℃、2分間の堆積を行って、厚さが3nmのSiN膜14をSiO2膜11上に形成する。なお、減圧CVD装置にロードロック機構を設けておいて、CVD炉内へSi基板を挿入する際は真空搬送を行い、且つ、純度の高いガスを用いることによって、酸素や炭化水素がSiN膜14中に混入することを極力避ける様にする。
【0014】
また、上述の堆積時の温度が比較的高温であるので、SiN膜14中への水素の混入も比較的抑制されている。以上の条件によって、膜質が均一で、緻密で、不純物や構造欠陥の少ないSiN膜14を形成することができる。この様なSiN膜14では、不純物や構造欠陥を介したリーク電流が少なくて、記憶保持特性を向上させることができる。
【0015】
次に、例えば、抵抗加熱型の減圧CVD装置にN2O/SiH2Cl2=200SCCM/1000SCCMのガスを70Paで供給し、800℃、5分間の堆積を行って、厚さが1nmのSiO2膜15をSiN膜14上に形成する。そして、SiN膜14を形成した場合と同じ条件で、厚さが3nmのSiN膜16をSiO2膜15上に形成する。
【0016】
その後、堆積時間を20分にすること以外はSiO2膜15を形成した場合と同じ条件で、厚さが4nmのSiO2膜13をSiN膜16上に形成する。そして、更に、ゲート電極等を従来公知の工程で形成して、この不揮発性半導体記憶装置を完成させる。
【0017】
SiO2膜11、13、15及びSiN膜14、16は巨視的には非晶質であるが、微視的には何れも規則的な構造を有しており、それらの界面には、結晶格子の様な構造欠陥が生じていて、この構造欠陥に起因する捕獲準位が形成されている。
【0018】
また、窒化膜内の酸素に起因して深い捕獲準位の形成されることが報告されており(V.J.Kapoor and S.B.Bibyk,“Energy distribution and electron trapping defects in thick-oxide MNOS structures",in“The Physics of MOS Insulators",edited by G.Lucousky et al.(Pergamon,New York,1980)p.117)、SiO2膜11、13、15とSiN膜14、16との界面には、この深い捕獲準位も形成されている。
【0019】
しかも、深い捕獲準位に捕獲された電荷がそこから脱出するためには、より大きなエネルギーが必要であるので、深い捕獲準位に捕獲された電荷は自然放出されにくい。このことは、一旦記憶された情報が失われにくいことを意味しており、このことによっても記憶保持特性を向上させることができる。
【0020】
次に、第2実施形態を説明する。この第2実施形態も、SiN膜16の堆積に先立って、例えば、ランプ加熱型の熱処理装置にNH3を1SLMで供給して、SiO2膜15の表面に対して1000℃、1分間の高速熱窒化を行うことを除いて、上述の第1実施形態と実質的に同様の工程を実行する。
【0021】
この様な熱窒化を行うと、次に行うSiN膜16の堆積に際して、堆積初期のSiO2膜15の表面における堆積種のマイグレーション等に起因するSiN膜16の表面荒れが抑制される。この結果、より膜質が均一で、より緻密なSiN膜16を形成することができて、記憶保持特性を更に向上させることができる。
【0022】
なお、以上の第1及び第2実施形態では、図1に示した様に、SiN膜14、16の間に単層のSiO2膜15が含まれているだけであるが、SiN膜とSiO2膜とが交互に積層された状態でSiN膜の間に複数層のSiO2膜が含まれていてもよい。
【0023】
また、以上の第1及び第2実施形態では、SiO2膜11上のSiN膜14、16及びSiO2膜13、15の総てを堆積によって形成したが、例えばSiN膜14の表面を熱酸化することによってSiO2膜15を形成してもよく、SiN膜14、16中に酸素を多量にイオン注入した後に熱処理を行うことによってSiO2膜15を形成してもよい。
【0024】
更に、SiN膜14、16中に酸素をイオン注入する際に、SiN膜14、16の全面に対してイオン注入を行うのではなく点状に行えば、SiN膜14、16との界面に沿って離散的に広がるSiO2膜15を形成することができるので、イオン注入する酸素の量が同じでも、SiN膜14、16とSiO2膜15との界面の面積を更に広くして、捕獲電荷量を更に多くすることができる。
【0025】
【発明の効果】
本願の発明による不揮発性半導体記憶装置では、同じ平面的な面積で比べると捕獲電荷量が多く、しかも、捕獲された電荷が自然放出されにくいので、微細化されていても記憶保持特性が優れている。
【0026】
また、窒化膜中の酸化膜がそれらの界面に沿って離散的に広がってい、捕獲電荷量が更に多いので、記憶保持特性が更に優れている
【0027】
本願の発明による不揮発性半導体記憶装置の製造方法では、同じ平面的な面積が比べると捕獲電荷量を多くすることができ、しかも、捕獲された電荷が自然放出されにくくすることができるので、微細化されていても記憶保持特性が優れている不揮発性半導体記憶装置を製造することができる。
【0028】
また、窒化膜中に酸化膜を形成する際に酸素を窒化膜中に点状にイオン注入して、捕獲電荷量更に多くすることができるので、記憶保持特性が更に優れている不揮発性半導体記憶装置を製造することができる。
【図面の簡単な説明】
【図1】 本願の発明の第1及び第2実施形態の要部の側断面図である。
【図2】 本願の発明の一従来例の要部の側断面図である。
【符号の説明】
11、13、15 SiO2膜 14、16 SiN膜
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device that stores information by trapping charges at a trap level at the interface between a nitride film and an oxide film, and a method for manufacturing the same.
[0002]
[Prior art]
As a type of nonvolatile semiconductor memory device that can rewrite information electrically and retain information even when the power is turned off, it traps charges at the trap level that exists at the interface between the insulating film and the oxide film. There is a nonvolatile semiconductor memory device that stores information by shifting the threshold voltage of a transistor.
[0003]
This nonvolatile semiconductor memory device is called a MIOS (Metal Insulator Oxide Semiconductor) type or a MOIOS (Metal Oxide Insulator Oxide Semiconductor) type, but a nitride film is mainly used as an insulating film. In particular, it is called MNOS type or MONOS type.
[0004]
FIG. 2 shows a conventional example of a MONOS type nonvolatile semiconductor memory device. In this conventional example, a tunnel SiO 2 film 11 having a thickness of 2 nm, a SiN film 12 having a thickness of 8 nm, and a SiO 2 having a thickness of 4 nm are formed on a Si substrate (not shown). A film 13 is sequentially stacked, and a polycrystalline Si film (not shown) as a gate electrode is formed on the SiO 2 film 13.
[0005]
[Problems to be solved by the invention]
However, in the MNOS type and MONOS type non-volatile semiconductor memory devices, the area per bit, the SiN film 12 and the like are increased in accordance with the miniaturization for increasing the capacity and the low voltage operation for reducing the power consumption. The thickness is decreasing. As a result, the area of the interface between the SiN film 12 and the SiO 2 films 11 and 13 is reduced and the amount of trap levels contained in the SiN film 12 is also reduced, thereby reducing the amount of trapped charges and improving the memory retention characteristics. It was falling.
[0006]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device that stores information by trapping charges at a trap level at an interface between a nitride film and an oxide film. The nitride film includes an oxide film. The oxide film is characterized by spreading discretely along the interface .
[0007]
A method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device that stores information by trapping charges at a trap level at an interface between a nitride film and an oxide film. An oxide film is formed in the nitride film by oxygen ion-implanted in the form of dots .
[0008]
In the nonvolatile semiconductor memory device according to the present invention, since the nitride film includes the oxide film, the area of the interface between the nitride film and the oxide film is large compared with the same planar area, and the trapped charge amount There are many. In addition, since many deep trap levels due to oxygen in the nitride film are formed, the trapped charges are not easily released spontaneously.
[0009]
Further, Runode oxide film in the nitride film stretches discretely along their interface, even a content of the oxide in the nitride film are the same, it is wider area of the interface between the nitride film oxide film More trapped charge .
[0010]
In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, an oxide film is formed in the nitride film. Therefore, when the same planar area is compared, the area of the interface between the nitride film and the oxide film is increased. The amount of trapped charges can be increased. In addition, since many deep trap levels due to oxygen in the nitride film are formed, it is possible to make it difficult to spontaneously release the trapped charges.
[0011]
In addition, when an oxide film is formed in the nitride film, oxygen can be ion-implanted into the nitride film in the form of dots to form an oxide film that spreads discretely along the interface with the nitride film. Even if the amount of oxygen to be injected is the same, the area of the interface between the nitride film and the oxide film can be further widened to further increase the amount of trapped charges.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, first and second embodiments of the present invention will be described with reference to FIG. In the first embodiment, for example, a gas of O 2 / N 2 = 300 SCCM / 10 SLM is supplied to a resistance heating type heat treatment furnace to dilute and oxidize a Si substrate (not shown), thereby forming a surface of the Si substrate. A SiO 2 film 11 having a thickness of 2 nm is formed.
[0013]
Next, for example, an NH 3 / SiH 2 Cl 2 = 2000 SCCM / 50 SCCM gas is supplied to a resistance heating type low pressure CVD apparatus at 70 Pa, and deposition is performed at 760 ° C. for 2 minutes to form a SiN film having a thickness of 3 nm. 14 is formed on the SiO 2 film 11. Note that when a Si substrate is inserted into the CVD furnace with a load lock mechanism provided in the low-pressure CVD apparatus, vacuum transfer is performed, and a high-purity gas is used so that oxygen and hydrocarbons are converted into SiN film 14. Try to avoid mixing in as much as possible.
[0014]
Further, since the deposition temperature is relatively high, the mixing of hydrogen into the SiN film 14 is relatively suppressed. Under the above conditions, it is possible to form the SiN film 14 having a uniform film quality, a dense film and few impurities and structural defects. In such a SiN film 14, there is little leakage current through impurities and structural defects, and the memory retention characteristics can be improved.
[0015]
Next, for example, a gas of N 2 O / SiH 2 Cl 2 = 200 SCCM / 1000 SCCM is supplied at 70 Pa to a resistance heating type low pressure CVD apparatus, and deposition is performed at 800 ° C. for 5 minutes to obtain SiO 2 having a thickness of 1 nm. Two films 15 are formed on the SiN film 14. Then, a SiN film 16 having a thickness of 3 nm is formed on the SiO 2 film 15 under the same conditions as when the SiN film 14 is formed.
[0016]
Thereafter, a SiO 2 film 13 having a thickness of 4 nm is formed on the SiN film 16 under the same conditions as those for forming the SiO 2 film 15 except that the deposition time is set to 20 minutes. Further, a gate electrode or the like is formed by a conventionally known process to complete the nonvolatile semiconductor memory device.
[0017]
The SiO 2 films 11, 13, 15 and the SiN films 14, 16 are macroscopically amorphous, but microscopically all have a regular structure, and there is a crystal at the interface between them. A structural defect such as a lattice is generated, and a trap level due to the structural defect is formed.
[0018]
It has also been reported that deep trap states are formed due to oxygen in the nitride film (VJ Kapoor and SBBibyk, “Energy distribution and electron trapping defects in thick-oxide MNOS structures”, in “The Physics of MOS Insulators ", edited by G. Lucousky et al. (Pergamon, New York, 1980) p. 117), this deep trap level at the interface between the SiO 2 films 11, 13, 15 and the SiN films 14, 16 Is also formed.
[0019]
In addition, since a larger amount of energy is required for the charge trapped in the deep trap level to escape from it, the charge trapped in the deep trap level is difficult to be spontaneously released. This means that information once stored is not easily lost, and this also improves the memory retention characteristics.
[0020]
Next, a second embodiment will be described. Also in the second embodiment, prior to the deposition of the SiN film 16, for example, NH 3 is supplied at 1 SLM to a lamp heating type heat treatment apparatus, and the surface of the SiO 2 film 15 is heated at 1000 ° C. for 1 minute. Except for performing thermal nitridation, substantially the same steps as those in the first embodiment are performed.
[0021]
When such thermal nitridation is performed, surface roughness of the SiN film 16 due to migration of deposited species on the surface of the SiO 2 film 15 at the initial deposition stage is suppressed during the subsequent deposition of the SiN film 16. As a result, a more uniform SiN film 16 having a more uniform film quality can be formed, and the memory retention characteristics can be further improved.
[0022]
In the first and second embodiments described above, as shown in FIG. 1, only the single-layer SiO 2 film 15 is included between the SiN films 14 and 16, but the SiN film and the SiO2 film are not included. A plurality of SiO 2 films may be included between the SiN films in a state where the two films are alternately stacked.
[0023]
In the first and second embodiments described above, the SiN films 14 and 16 and the SiO 2 films 13 and 15 on the SiO 2 film 11 are all formed by deposition. For example, the surface of the SiN film 14 is thermally oxidized. Thus, the SiO 2 film 15 may be formed, or the SiO 2 film 15 may be formed by performing heat treatment after ion implantation of a large amount of oxygen into the SiN films 14 and 16.
[0024]
Further, when oxygen is ion-implanted into the SiN films 14 and 16, if the ion implantation is not performed on the entire surface of the SiN films 14 and 16, but is performed in a dot-like manner, the interface with the SiN films 14 and 16 is followed. Since the SiO 2 film 15 spreading discretely can be formed, even if the amount of oxygen to be ion-implanted is the same, the area of the interface between the SiN films 14 and 16 and the SiO 2 film 15 can be further increased, and the trap charge can be increased. The amount can be increased further.
[0025]
【The invention's effect】
In the nonvolatile semiconductor memory device according to the present invention, the amount of trapped charges is large compared with the same planar area, and the trapped charges are not easily released spontaneously, so that the memory retention characteristics are excellent even when miniaturized. Yes.
[0026]
Further, the oxide film of the nitride film is not spread discretely along their interface, since the amount of trapped charge more often, memory retention characteristics are more excellent.
[0027]
In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the amount of trapped charges can be increased compared to the same planar area, and the trapped charges can be made difficult to be spontaneously released. Even if manufactured, a nonvolatile semiconductor memory device having excellent memory retention characteristics can be manufactured.
[0028]
Furthermore, by ion implantation of oxygen into a point-like on the nitride film during the formation of the oxide film on the nitride film, it is possible to further increase the trapped charge amount, the non-volatile semiconductor memory retention characteristics are more excellent A storage device can be manufactured.
[Brief description of the drawings]
FIG. 1 is a side sectional view of an essential part of first and second embodiments of the present invention.
FIG. 2 is a side cross-sectional view of a main part of a conventional example of the present invention.
[Explanation of symbols]
11, 13, 15 SiO 2 film 14, 16 SiN film

Claims (2)

窒化膜と酸化膜との界面における捕獲準位に電荷を捕獲することによって情報を記憶する不揮発性半導体記憶装置において、
前記窒化膜中に酸化膜が含まれており、
この酸化膜が前記界面に沿って離散的に広がっていることを特徴とする不揮発性半導体記憶装置。
In a nonvolatile semiconductor memory device that stores information by trapping charges at a trap level at the interface between a nitride film and an oxide film,
The nitride film includes an oxide film ,
A non-volatile semiconductor memory device characterized in that the oxide film spreads discretely along the interface .
窒化膜と酸化膜との界面における捕獲準位に電荷を捕獲することによって情報を記憶する不揮発性半導体記憶装置の製造方法において、
前記窒化膜中に点状にイオン注入した酸素によって前記窒化膜中に酸化膜を形成することを特徴とする不揮発性半導体記憶装置の製造方法。
In a method for manufacturing a nonvolatile semiconductor memory device that stores information by trapping charges at a trap level at an interface between a nitride film and an oxide film,
A method of manufacturing a nonvolatile semiconductor memory device, comprising forming an oxide film in the nitride film by oxygen ion-implanted in the form of dots in the nitride film .
JP29336396A 1996-10-15 1996-10-15 Nonvolatile semiconductor memory device and manufacturing method thereof Expired - Fee Related JP3818402B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29336396A JP3818402B2 (en) 1996-10-15 1996-10-15 Nonvolatile semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29336396A JP3818402B2 (en) 1996-10-15 1996-10-15 Nonvolatile semiconductor memory device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH10125813A JPH10125813A (en) 1998-05-15
JP3818402B2 true JP3818402B2 (en) 2006-09-06

Family

ID=17793826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29336396A Expired - Fee Related JP3818402B2 (en) 1996-10-15 1996-10-15 Nonvolatile semiconductor memory device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3818402B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222876A (en) * 2001-01-25 2002-08-09 Sony Corp Non-volatile semiconductor memory device and method of manufacturing the same
JP4590744B2 (en) * 2001-01-25 2010-12-01 ソニー株式会社 Nonvolatile semiconductor memory device and manufacturing method thereof
KR101086497B1 (en) 2006-06-29 2011-11-25 주식회사 하이닉스반도체 Non volatile memory device and method for manufacturing the same
JP2009289823A (en) * 2008-05-27 2009-12-10 Renesas Technology Corp Nonvolatile semiconductor storage device

Also Published As

Publication number Publication date
JPH10125813A (en) 1998-05-15

Similar Documents

Publication Publication Date Title
JP5032056B2 (en) Method for manufacturing nonvolatile semiconductor memory device
JP4617574B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
JPH10135207A (en) Formation of thin film by using n2o gas
JP2007043147A (en) Method of forming silicon-rich nanocrystal structure using atomic layer deposition process and method of manufacturing nonvolatile semiconductor device using the same
JP3818402B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
US20070202645A1 (en) Method for forming a deposited oxide layer
KR101107398B1 (en) Semiconductor device and method for manufacturing the same
US6913976B2 (en) Method of manufacturing semiconductor device
US6162684A (en) Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices
TWI245347B (en) Method of fabricating a semiconductor structure
JP3256059B2 (en) Method for manufacturing semiconductor device
US7919371B2 (en) Method for fabricating non-volatile memory device with charge trapping layer
JP3802945B2 (en) Method for manufacturing nonvolatile semiconductor memory device
JP3041065B2 (en) Insulating film forming method
JP4590744B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
KR100304980B1 (en) Method for forming tunnelling oxide and method for manufacturing nonvolatile memory device using the same
JPS6170763A (en) Manufacture of semiconductor memory storage
JPH08130259A (en) Semiconductor memory element
KR20080010514A (en) Method of forming a dielectric layer structure and method of forming a non-volatile memory device using the same
JPH0422031B2 (en)
JPH03227069A (en) Manufacture of semiconductor memory device
JPH0665232B2 (en) Method of manufacturing semiconductor memory device
JP2004014711A (en) Semiconductor device and method for manufacturing the same
JPS58212180A (en) Nonvolatile memory device and manufacture thereof
JPH05343703A (en) Manufacture of nonvolatile memory

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060405

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060428

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060525

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060607

LAPS Cancellation because of no payment of annual fees