JP3789445B2 - Optical packet transmitter, optical packet receiver, and optical packet transmission system - Google Patents

Description

  The present invention relates to an optical packet transmitter, an optical packet receiver, and an optical packet transmission system, and can be applied to, for example, an optical packet transmission system that uses optical carrier phase information as a destination.

  In a conventional single packet switch by electricity, there is a limit to the number of packets per unit time that can be handled due to the operation speed of the element, signal transmission delay, heat generation, and the like.

  Therefore, research and development aiming at improvement of throughput using an optical packet switch that can handle a signal that is essentially faster than electricity has been conducted. As a technique related to this, for example, a technique described in Non-Patent Document 1 is available. is there.

The technology described in Non-Patent Document 1 converts an input optical packet sequence to which a unique 4-bit preamble is applied into an optical packet sequence of a plurality of wavelength components using a semiconductor laser and a semiconductor optical amplifier. After that, different delays are given depending on the wavelength components, and correlations between a plurality of wavelength components are continuously obtained, and the preamble period is recognized according to the correlation value to separate the optical packets.
MCCardakli et.al., 'Optical packet and bit synchronization of a switching node using FBG optical correlators', OFC, TuW2,2001

  However, in Non-Patent Document 1, a new preamble must be added to the conventional format, and a semiconductor laser, a semiconductor optical amplifier, or the like must be used for conversion into an optical packet sequence of each wavelength component. There are issues such as.

  Therefore, there is no need to add a specific bit to separate the optical packet, and the optical packet can be separated with a small delay time (including switching), an optical packet transmitter, an optical packet receiver, and an optical packet. There is a need for a transmission system.

  The optical packet transmission apparatus of the present invention includes (1) an electrical / optical conversion means for converting a serial electrical transmission signal in which packets of different destinations are mixed into an optical transmission signal, and (2) a phase of a carrier wave of the optical transmission signal. (3) phase control means for adding destination information to the phase of the carrier wave of each packet in accordance with the destination of each packet in the optical transmission signal; And a phase control means for forming a signal.

  The optical packet receiving apparatus of the present invention is (1) a serial optical transmission signal in which packets of different destinations are mixed and the phase of a carrier wave is changed in accordance with the destination information is input, and in accordance with a given gate control signal And the same number of gate means as the number of destinations that pass and do not pass the optical transmission signal, and (2) the optical transmission signal and a delayed optical transmission signal obtained by delaying the optical transmission signal by a predetermined time. And interferometer means for generating an intensity change portion due to the phase change portion of the carrier wave, and (3) determining a packet destination in the optical transmission signal based on the intensity change portion in the output signal of the interferometer means, And a gate control signal forming unit that represents the passage of only the gate control signal to the gate unit corresponding to the determined destination.

  The optical packet transmission system of the present invention includes the optical packet transmitter of the present invention and the optical packet receiver of the present invention.

  According to the optical packet transmitting apparatus of the present invention, it is possible to provide destination information using the carrier phase of the optical packet signal without inserting a new bit for discrimination. According to the optical packet receiving apparatus of the present invention, after branching a part of the input signal, it is delayed by a predetermined time and combined to generate an intensity change part due to the phase change part of the carrier wave. Since the destination of the packet in the optical transmission signal is determined, even the signal from the optical packet transmission apparatus of the present invention in which a new bit for discrimination is not inserted can be appropriately discriminated. According to the optical packet transmission system of the present invention, the optical packet transmission system is configured by the optical packet transmission apparatus of the present invention and the optical packet reception apparatus of the present invention, so that the optical packet signal is appropriately transmitted without inserting a new bit for discrimination. Can be distributed to destinations.

(A) First Embodiment First, a first embodiment of the present invention will be described with reference to the drawings. The first embodiment is an embodiment of an optical packet transmission apparatus according to the present invention.

(A-1) Configuration of First Embodiment FIG. 1 is a block diagram illustrating a schematic configuration of an optical packet transmission device according to the first embodiment.

  In FIG. 1, an optical packet transmission apparatus 100 according to the first embodiment includes an optical processing system and an electrical processing system, an input interface is electricity, and an output interface is light.

  The electrical processing system includes a buffer 101 and a coder 104, and the optical processing system includes an electrical / optical converter (hereinafter referred to as an e / o converter) 102, a phase modulator 103, a driver 105, and a delay unit 106. .

  In the case of the first embodiment, the buffer 101 buffers two systems of packets with different destinations and outputs them alternatively.

  The coder 104 monitors the destination part in the packet output from the buffer 101, and outputs different codes (for example, “H” and “L” because there are two systems here) for each change in destination. is there.

  The e / o converter 102 converts a packet composed of an electrical signal output from the buffer 101 into an optical signal having a predetermined wavelength.

  The driver 105 drives the phase modulator 103 so that the output phase from the phase modulator 103 becomes a phase corresponding to the output of the coder 104.

  The phase modulator 103 performs phase modulation on the optical packet that has passed through the delay unit 106 under the control of the driver 105.

  The delay unit 106 delays the optical packet from the e / o converter 102 so that the processing timing of the phase modulator 103 becomes appropriate also by the processing delay of the coder 104 or the like. Note that such timing compensation may be performed on packets in the electrical signal stage.

(A-2) Operation of the First Embodiment Next, the operation of the optical packet transmission apparatus of the first embodiment will be described with reference to FIGS. 2 and 3 in addition to FIG.

  Packets with different destinations a and b input from the two systems are accumulated in the buffer 101 and then sequentially output from the buffer 101. The packet (electric signal) S101 output from the buffer 101 is branched into two, and each branch packet is input to the e / o converter 102 and the coder 104.

  The packet given to the e / o converter 102 is converted into an optical signal (optical packet) having a predetermined wavelength, and then given a predetermined delay by the delay unit 106 and is incident on the phase modulator 103. The optical packet from the e / o converter 102 is intensity-modulated in accordance with “1” and “0” in the packet composed of the input electric signal.

  On the other hand, the coder 104 outputs a code S104 representing the destination according to the destination of the input packet. In the first embodiment, since the destinations are two systems a and b, the coder 104 outputs, for example, “L” when the destination is a and “H” when the destination is b. Is output.

  FIG. 2 shows an output packet S101 from the buffer 101, and is an example of Gigabit Ethernet (GbE). In the gigabit ether packet, there are 10 32-bit strings to indicate the head of the packet.

  In the coder 104, the code consisting of “L” or “H” is discharged in synchronization with the preamble period. Such a code from the coder 104 is input to the driver 105 and becomes a signal for driving the phase modulator 103.

  The intensity modulated optical packet output from the e / o converter 102 and given a delay by the delay unit 106 is subjected to phase modulation according to the output code of the coder 104 by the phase modulator 103.

  FIG. 3 is an explanatory diagram of the phase modulation operation in the phase modulator 103 according to the first embodiment.

  As shown in FIG. 3, the output voltage of the driver 105 (the voltage applied to the phase modulator 103) becomes the voltage VL or VH depending on the output of the coder 104. The phase modulator 103 changes the phase of the output optical packet in accordance with the applied voltage. For example, when the applied voltage is the voltage VL, the phase of the output packet is 0, and when the applied voltage is the voltage VH, the phase of the output packet is π.

  Thus, the optical packet output from the optical packet transmitting apparatus 100 has a phase of 0 when the destination is a and a phase of π when the destination is b.

(A-3) Effect of First Embodiment According to the first embodiment, information indicating two destinations is output to an output optical packet using the phase of the optical packet without inserting a specific destination bit. Can be added.

(B) Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. Here, the second embodiment is an embodiment of an optical packet receiving apparatus according to the present invention. The optical packet receiving apparatus according to the second embodiment may be provided in an apparatus that accommodates two communication terminals, or may be provided in an optical packet switch as a relay station. The optical packet transmitting apparatus having the configuration has a function of performing switching (separation for each destination) in an optical signal state.

  The optical packet transmission system including the optical packet transmission device of the first embodiment and the optical packet reception device of the second embodiment is an embodiment of the optical packet transmission system of the present invention.

(B-1) Configuration of Second Embodiment FIG. 4 is a block diagram illustrating a schematic main configuration of an optical packet reception device according to the second embodiment.

  In the optical packet receiving apparatus 300 of the second embodiment, the interface is light for both input and output, and the optical packet receiving apparatus 300 is generally configured by an optical processing system, and only a part is configured by an electrical processing system.

  The optical processing system includes an input terminal 301, a first coupler 302, an interferometer 303, an optical / electrical converter (hereinafter referred to as an o / e converter) 304, a clock extractor 306, an optical switch 308, and a second coupler. 311, a delay device 312, and two output terminals 309 and 310. The optical switch 308 includes a third optical coupler 3081 and two gates 3082 and 3083.

  On the other hand, the electric processing system includes a toggle flip-flop 305 and two drivers 313 and 314.

  The first coupler 302 divides the optical signal from the input terminal 301 into two and supplies it to the delay device 312 and the second coupler 311.

  The second coupler 311 splits the input optical signal into two and supplies it to the interferometer 303 and the clock extractor 306.

  The interferometer 303 divides the input optical signal into two parts and synthesizes them with a predetermined time difference, and may interfere during synthesis. That is, an input optical signal and an optical signal obtained by shifting the optical signal by a predetermined phase are combined (interfered) to extract a phase change in a period before and after.

  For example, the interferometer 303 having the configuration shown in FIG. 5 can be applied. That is, the interferometer 303 includes an input end 730, a circulator 720, a PLC (planar waveguide) section 710, and an output end 740. The PLC section 710 includes a common waveguide 711, a Y branch waveguide 712, and two arm guides. A waveguide composed of waveguides 713 and 714 and two reflecting surfaces 715 and 716 can be applied. The functions of the components of the interferometer 303 will be clarified in the operation description.

  The o / e converter 304 converts the optical signal subjected to the interference processing by the interferometer 303 into an electric signal and supplies it to the toggle flip-flop 305.

  The clock extractor 306 extracts a clock related to the optical signal (optical packet) from the optical signal from the second coupler 311, and supplies the clock that is an electric signal to the toggle flip-flop 305.

  The toggle flip-flop 305 performs a toggle operation in response to the pulse output from the o / e converter 304, and performs the toggle operation in synchronization with the clock from the clock extractor 306.

  The first driver 313 controls to pass through the first gate 3082 when one output (Q output) of the toggle flip-flop 305 is at a significant level, and the second driver 314 controls the toggle flip-flop. When the other output of the group 305 (Q / output: “/” means inversion) is at a significant level, the second gate 3083 is controlled to pass.

  The delay device 312 delays the optical signal from the second optical coupler 302 by a predetermined time and supplies the optical signal to the third optical coupler 3081.

  The third optical coupler 3081 splits the input optical signal into two and supplies it to the first gate 3082 and the second gate 3083.

  The first gate 3082 and the second gate 3083 respectively pass or block the input optical signal under the control of the corresponding first driver 313 and second driver 314 and pass the optical signal ( Destination optical packet) is provided to the corresponding output terminals 310 and 309. The first gate 3082 and the second gate 3083 can be realized by using, for example, an EA (Electro-Absorption) modulator.

(B-2) Operation of Second Embodiment Next, the operation of the optical packet receiving apparatus of the second embodiment will be described with reference to FIG. 6 in addition to FIG. 4 and FIG.

Optical signal input from the input terminal 301 is input to the second coupler 311 is partially branched by the first coupler 302, it is further bifurcated by a second coupler 311, and their respective interferometer 303, clock An extractor 306 is input. Note that the remaining branched optical signal from the first coupler 302 is input to the delay unit 312.

  In the interferometer 303, as shown in FIG. 5, the input optical signal is input to the circulator 720, output from the PLC side input / output port 721, and input to the PLC unit 710. In the PLC unit 710, the input optical signal passes through the common waveguide 711 and then is branched into two by the Y branching waveguide 712. One branched optical signal travels through the first arm waveguide 713, is reflected by the first reflecting surface 715, and travels through the first arm waveguide 713 toward the Y branch waveguide 712. The other branched optical signal travels through the second arm waveguide 714, is reflected by the second reflecting surface 716, and travels through the second arm waveguide 714 toward the Y branch waveguide 712. . The two reflected light signals are recombined in the Y branch waveguide 712. Since the two optical signals are set so as to receive a 2-bit delay after being branched by the Y-branch waveguide 712 and then recombined, the PLC unit 710 receives an optical signal that is shifted by 2 bits. Output as sum. An output signal from the PLC unit 710 is input to the circulator 720 again from the PLC side input / output port 721 and output from the o / e converter side output port 722.

  On the other hand, the clock is extracted by the clock extractor 306 from the optical signal branched by the second coupler 311 and input to the clock extractor 306, and becomes a clock for synchronizing the electric processing system.

  The optical signal output from the interferometer 303 is converted into an electrical signal by the o / e converter 304 and input to the toggle flip-flop 305. In the toggle flip-flop 305, every time a signal on a pulse is input from the o / e converter 304, the “1” level and the “0” level are switched in synchronization with the clock. The two output signals (Q output and Q / output) of the toggle flip-flop 305 are amplified by the corresponding first driver 313 and second driver 314, respectively, and the first gate 3082 and the second gate 3083 are passed through. To drive.

  On the other hand, the main signal that has passed through the first coupler 302 is input to the optical switch 308 via the delay unit 312.

  In the optical switch 308, the input optical signal is branched into two by the third coupler 3081 and input to the first gate 3082 and the second gate 3083, respectively. In the first gate 3082 and the second gate 3083, the optical output is turned on / off by an electric signal (control signal) from the corresponding first driver 313 and second driver 314.

  Note that since the input signals to the first driver 313 and the second driver 314 are complementary signals, ON / OFF of the optical output by the first gate 3082 and the second gate 3083 is also a complementary operation.

  The optical signal input to the optical switch 308 is set by a delay time by the delay device 312 (or may be an adjustable variable delay device), so that the electric signal from the first driver 313 and the second driver 314 is output. Signals (control signals) and timing can be taken.

  The operation will be described with reference to FIG. Here, it is assumed that the input optical signal (optical packet signal) conforms to Gigabit Ethernet.

  The input optical packet signal S301 has a phase π or 0 given by the destination of the packet. Part of the input optical packet signal S301 is output by the interferometer 303 after phase comparison with the signal two bits before. When the phase difference between the current phase of the optical packet signal S301 and the phase two bits before is shifted by π from the interferometer 303, a signal indicating significance is output, and the current phase of the optical packet signal S301 is output. If the phase difference from the previous two bits is 0, a signal S303 indicating insignificance is output.

  In the case of gigabit ether, since there is a 32-bit preamble (10 stations) at the beginning of the packet, a 1-bit signal representing significance is given to the beginning of the packet by comparing with the signal two bits before. S303 is output. By using this 1-bit signal S303, it is possible to determine the head of the packet in the state of the optical signal.

  In the second embodiment, the 1-bit signal (optical signal) S303 is converted into an electric signal and latched by the toggle flip-flop 305 in synchronization with the extraction clock S306. The signal (Q output) S3051 latched by the toggle flip-flop 303 changes from “H” level to “L” level and from “L” level to “H” level every time the packet changes. By supplying this signal S3051 to the first driver 313 and driving the first optical gate 3082, the state of the optical signal can be maintained and the packet S3082 having the same destination can be extracted. Further, an inverted output signal (Q / output) S3052 of the toggle flip-flop 305 is given to the second driver 314 to drive the second optical gate 3083, thereby maintaining the state of the optical signal. The same packet S3083 of two destinations can be extracted.

(B-3) Effect of Second Embodiment According to the second embodiment, the inter-packet phase difference information of the optical packet signal can be used without inserting a new destination discrimination bit. Packet switching can be provided in a state, and high-speed packet switching can be realized.

(C) Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings. The third embodiment is also an embodiment of the optical packet transmitter according to the present invention.

  The optical packet transmitter of the first embodiment described above is an optical packet transmitter that assigns two destinations to a packet according to the phase of light, but the optical packet transmitter of the third embodiment is an optical packet transmitter. This is an optical packet transmission device that assigns three destinations according to the phase of. Note that the technical idea of the optical packet transmission apparatus according to the third embodiment can be extended to an optical packet transmission apparatus that assigns four or more destinations according to the phase of light.

(C-1) Configuration of Third Embodiment FIG. 7 is a block diagram illustrating a schematic configuration of an optical packet transmission device according to the third embodiment.

  In FIG. 7, the optical packet transmission device 900 of the third embodiment also has a buffer 901 and a coder 904 as an electrical processing system, almost the same as the optical packet transmission device 100 of the first embodiment. As an e / o converter 902, a phase modulator 903, a driver 905, and a delay 906.

  The difference from the first embodiment is mainly that the buffer 901 buffers and sequentially outputs three types of destination packet signals, and the coder 904 outputs three types of destination-specific codes.

(C-2) Operation of Third Embodiment Next, the operation of the optical packet transmission apparatus of the third embodiment will be described with reference to FIGS. 8 and 9 in addition to FIG.

  Packets with different destinations a, b, and c input from the three systems are accumulated in the buffer 901 and then sequentially output from the buffer 901 as shown in FIG. The packet (electrical signal) S901 output from the buffer 901 is branched into two, and each branched packet is input to the e / o converter 902 and the coder 904. The packet supplied to the e / o converter 902 is converted into an optical signal (optical packet) having a predetermined wavelength, and then given a predetermined delay by the delay unit 906 and made incident on the phase modulator 903.

  On the other hand, the coder 904 outputs a code S904 representing the destination according to the destination of the input packet. The coder 904 has three packet destinations, a, b, and c. For example, when the destination is a, the “L” level, and when the destination is b, the “M (intermediate value)” level, When “c” is “c”, “H” level is output.

  It is assumed that the third embodiment also conforms to Gigabit Ethernet. In the gigabit ether packet, there are 10 32-bit sequences to indicate the head of the packet, and the coder 904 sends an “L”, “M” or “H” level signal in time with this preamble. Discharge.

  An output signal from the coder 904 is input to the driver 905 and becomes a signal for driving the phase modulator 903. For example, the output signal from the coder 904 is amplified by the driver 905 to the voltage VL, VM, or VH corresponding to the “L”, “M”, or “H” level, and drives the phase modulator 903.

  In the phase modulator 903, as shown in FIG. 9, with respect to the output voltages VL, VM, and VH from the driver 905, the phase at the destination a is a reference (0), the phase at the destination b is π / 3, and at the destination c The phase π is given.

  The delay of the output signal of the coder 904 is corrected by the delay unit 906, and the phase modulation timing by the phase modulator 903 is set so as to coincide with the packet changing timing.

(C-3) Effect of Third Embodiment According to the third embodiment, three (or three or more) destinations of an optical packet signal can be obtained without inserting new destination discrimination bits. An optical phase signal can be provided.

(D) Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to the drawings. Here, the fourth embodiment is an embodiment of the optical packet receiver according to the present invention, and corresponds to the optical packet transmitter of the third embodiment. The optical packet receiving apparatus of the fourth embodiment may be provided in an apparatus that accommodates three communication terminals, or may be provided in an optical packet switch as a relay station. The optical packet transmitting apparatus having the configuration has a function of performing switching (separation for each destination) in an optical signal state.

  An optical packet transmission system including the optical packet transmission apparatus of the third embodiment and the optical packet reception apparatus of the fourth embodiment is an embodiment of the optical packet transmission system of the present invention.

(D-1) Configuration of Fourth Embodiment FIG. 10 is a block diagram showing a schematic configuration of a main part of an optical packet receiving device of the fourth embodiment.

  In the optical packet receiving device 200 of the fourth embodiment, both the input signal and the output signal are optical signals, and the processing system includes an optical processing system and an electrical processing system.

  The optical processing system includes a first coupler 201, an interferometer 202, an e / o converter 203, a clock extractor 207, three gates 210 to 212, a delay device 216, and second and third couplers 217 and 218. The electric processing system includes three phase shift amount separation circuits 204, 205, 206, a destination determination circuit 208, a decoder 209, and three drivers 220, 221, 222.

  Here, the component having the same name as that of the second embodiment exhibits the same function as the component of the second embodiment.

  Each of the phase shift amount separation circuits 204, 205, and 206 is composed of, for example, a comparator that compares the input voltage level with a threshold level assigned to itself, and a latch circuit that latches the output thereof. It is determined whether the phase change (phase shift amount) is larger than the phase shift amount corresponding to the threshold level on a one-to-one basis, and latched in synchronization with the clock. The phase shift amount separation circuit 204 is selected to have a threshold level that is determined to be significant when the phase shift amount (absolute value) is at least π / 3 or more, and the phase shift amount separation circuit 205 has a phase shift amount (absolute value). The threshold level is determined to be significant when it is at least 2π / 3 or more, and the phase shift amount separation circuit 206 is selected to be threshold level that is determined to be significant when the phase shift amount (absolute value) is at least π. Has been.

  The destination determination circuit 208 uses the output signals from the phase shift amount separation circuits 204, 205, and 206 and the output signal two bits before from its own circuit 208 (consisting of 2 bits) to define the packet destination of 2 bits. The signal is output. FIG. 11 is a chart showing a truth table of determination processing by the destination determination circuit 208, which will be clarified in an operation description to be described later.

  The decoder 209 decodes the 2-bit signal that defines the destination of the packet output from the destination determination circuit 208, and outputs a significant signal only to the output line related to the destination among the three output lines.

  The decoder 209 can be composed of, for example, four AND circuits 20903, 20904, 20905, and 20906 and three latch flip-flops 20907, 20908, and 20909 as shown in FIG.

(D-2) Operation of the Fourth Embodiment Next, the operation of the optical packet reception device of the fourth embodiment will be described with reference to FIG. 13 in addition to FIG. 10 and FIG. FIG. 13 is a timing chart of each part of the optical packet receiver according to the fourth embodiment.

  The optical packet signal S219 input from the input terminal 219 is transmitted by the optical packet transmission device of the third embodiment. As shown in FIG. The destination c has an optical phase signal of π. The input optical packet signal S 219 is partially branched by the first coupler 201 and further branched by the second coupler 217 and then input to the interferometer 202 and the clock extractor 207.

  The interferometer 202 has the same configuration as that of the interferometer 303 of the second embodiment (see FIG. 5), and the interferometer 202 compares the phase of the input optical signal with the optical signal two bits before. For this reason, as shown in FIG. 13, the output signal S202 from the interferometer 202 outputs a 1-bit wide signal every time the packet destination changes.

  More specifically, when the destination of the packet in the input optical signal changes from a to b, or from b to a, the phase difference (phase change; phase shift amount) is 1 / 3π, and the destination of the packet is a The phase difference is π when changing from c to c, or from c to a, and the phase difference is 2 / 3π when the packet destination changes from b to c or from c to b.

  FIG. 14 shows the output level of the interferometer 202 with respect to the phase difference at the timing when the optical signal is shifted by 2 bits. As shown in FIG. 14, since the output level corresponds to the phase difference, when there is no phase difference (phase difference 0), the VL level is output, and the VM1 level with respect to the phase difference of 1 / 3π. Is output, the VM2 level is output for a phase difference of 2 / 3π, and the VH level is output for a phase difference of π.

  The output signal S202 (see FIG. 13) from the interferometer 202 is converted into an electrical signal by the o / e converter 203, and then branched into three, and input to the phase shift amount separation circuits 204, 205, and 206, respectively.

  The first phase shift amount separation circuit 204 latches the value greater than the value Vth1 (value between VL and VM1) shown in FIG. 13 in synchronization with the clock, and outputs a signal S204 of “1” level. . In the second phase shift amount dividing circuit 205, a value equal to or higher than the threshold value Vth2 (value between VM1 and VM2) shown in FIG. 13 is latched in synchronization with the clock and a signal S205 of “1” level is output. . The third phase shift amount separation circuit 206 latches the value equal to or higher than the threshold value Vth3 (value between VM2 and VH) shown in FIG. 13 in synchronization with the clock, and outputs a signal S206 of “1” level. .

  Next, these signals S204 to S206 are input to the destination determination circuit 208. The output signals S2081 and S2082 of the destination determination circuit 208 are delayed by 2 bits and input again to the destination determination circuit 208.

  The destination determination circuit 208 forms and outputs output signals S2081 and S2082 in accordance with the truth value chart shown in FIG. In the fourth embodiment, “00” is assigned as the signals S2081 and S2082 to the destination a, “01” is assigned as the signals S2081 and S2082 to the destination b, and the destination c is assigned to the destination c. Thus, “11” is assigned as the signals S2081 and S2082.

  For example, when the destination b is changed to the destination c, since the phase difference is 2 / 3π, the output signals S204 to S206 from the phase shift amount separation circuits 204 to 206 are “110”, and the destination determination circuit 208 Since the output signals S2081 and S2082 up to that point are “01” representing the destination b, the destination determination circuit 208 changes the output signals S2081 and S2082 to “11” representing the destination c according to FIG. As is apparent from FIG. 11, the destination determination circuit 208 maintains the contents of the output signals S2081 and S2082 when there is no phase change.

  Output signals S2081 and S2082 from the destination determination circuit 208 are input to the decoder 209. When the input signals S2081 and S2082 are “00”, the decoder 209 sets only the output level of the output signal S2091 to “H”, and when the input signals S2081 and S2082 are “01”, only the output level of the output signal S2092 is “ When the input signals S2081 and S2082 are “11”, only the output level of the output signal S2093 is set to “H”. The respective output signals S2091 to S2093 are latched by flip-flops.

  These signals S2091 to S2093 are amplified by the corresponding drivers 220, 221, and 222 and input to the corresponding gates 210, 211, and 212 as gate control signals.

  The optical packet signal that has passed through the first coupler 201 is given a predetermined delay by the delay unit 216, and then is branched into three by the third coupler 218 and input to the gates 210, 211, and 212.

  Each of the gates 210, 211, 212 passes the input signal when the corresponding signal S2091, S2092, S2093 is at “H” level. As a result, the output signals S210, S211 from the gates 210, 211, 212 are passed. , S212 is obtained by separating and extracting only a packet signal of a predetermined destination.

  The delay unit 216 synchronizes the timing of the optical packet signal input to each of the gates 210, 211, and 212 with the gate control signals S2091, S2092, and S2093.

(D-3) Effect of Fourth Embodiment As described above, according to the fourth embodiment, even when there are a plurality (three or more) of destinations, a new destination discrimination bit is not inserted. The packet switching can be provided in the state of the optical signal using the inter-packet phase difference information of the optical packet signal, and the packet switching can be speeded up.

(E) Fifth Embodiment Next, a fifth embodiment of the present invention will be described with reference to the drawings. Here, the fifth embodiment is also an embodiment of the optical packet transmitter according to the present invention.

  The optical packet transmitter of the first embodiment and the optical packet receiver of the second embodiment, the optical packet transmitter of the third embodiment, and the optical packet receiver of the fourth embodiment described above are optical packets. The entire phase is changed for each destination. However, this is effective when the number of destinations is small due to sensitivity limitations of the interferometer.

  The fifth embodiment embodies the technical idea of an optical packet transmission apparatus that can handle a large number of destinations, and will be described below in the case of two destinations for the sake of simplicity.

(E-1) Configuration of Fifth Embodiment FIG. 15 is a block diagram illustrating a schematic configuration of an optical packet transmission device of the fifth embodiment.

15, the optical packet transmission device 400 of the fifth embodiment is composed of the optical processing system and an electric processing system, and an electric processing system, a buffer 401, coder 408, latch circuit 403, XOR (exclusive Or) a circuit 404 and a driver 405, and an e / o converter 402, a phase modulator 406, and a delay 407 as an optical processing system.

  A component having the same name as that of the first embodiment exhibits the same function as the component of the first embodiment.

  The latch circuit 403 latches the code indicating the destination output from the coder 408.

  The XOR circuit 404 performs matching / mismatch determination between the output signal from the coder 408 and the output signal from the latch circuit 403, and detects a destination change.

(E-2) Operation of Fifth Embodiment Next, the operation of the optical packet transmission apparatus of the fifth embodiment will be described with reference to FIG. 16 in addition to FIG.

  Packet signals input from the two systems are accumulated in the buffer 401 and sequentially output. The signal output from the buffer 401 is converted into an optical signal by the e / o converter 402 and then provided to the phase modulator 406 via the delay unit 407.

  Further, the signal output from the buffer 401 is partly branched and input to the coder 408. The coder 408 discharges “0” if the destination of the packet is a, and “1” if the destination is b.

  This code is input to the latch circuit 403. The signal latched by the latch circuit 403 is then held until the latch signal changes (until the destination changes) and is input to the XOR circuit 404.

  The output code of the coder 408 is also input to the XOR circuit 404 and compared with the output of the latch circuit 403 one bit before. The output signal from the XOR circuit 404 takes “1” when the destination changes, and takes “0” when the destination does not change.

  The “1” level output signal from the XOR circuit 404 is amplified by the driver 405 and then input to the phase modulator 406.

  As a result, the optical packet signal input to the phase modulator 405 is subjected to phase modulation different from other periods only during the period when the output signal from the XOR circuit 404 is at the “1” level. Here, the output signal from the driver 405 has a voltage necessary to change the phase of the optical packet signal by π. The delay of the electric signal generated from the coder 408 to the XOR circuit 405 is absorbed by the delay unit 407.

  The optical packet transmitting apparatus according to the fifth embodiment is applicable to a gigabit ether signal. For example, as shown in FIG. 16, an optical packet having one phase modulation bit in the third bit of the preamble. Output a signal.

(E-3) Effect of Fifth Embodiment According to the fifth embodiment, the destination is changed without assigning an optical phase and adding a new destination distinguishing bit for each destination. A phase modulation bit characterizing this can be added to the optical packet signal.

(F) Sixth Embodiment Next, a sixth embodiment of the present invention will be described with reference to the drawings. Here, the sixth embodiment is an embodiment of the optical packet receiver according to the present invention, and corresponds to the optical packet transmitter of the fifth embodiment. The optical packet receiving apparatus of the sixth embodiment may be provided in an apparatus that accommodates two communication terminals, or may be provided in an optical packet switch as a relay station. The optical packet transmitting apparatus having the configuration has a function of performing switching (separation for each destination) in an optical signal state.

  An optical packet transmission system including the optical packet transmitter of the fifth embodiment and the optical packet receiver of the sixth embodiment is an embodiment of the optical packet transmission system of the present invention.

(F-1) Configuration of Sixth Embodiment FIG. 17 is a block diagram illustrating a schematic configuration of main parts of an optical packet reception device according to the sixth embodiment.

  In the optical packet receiving device 1400 of the sixth embodiment, both the input signal and the output signal are optical signals, and the processing system includes an optical processing system and an electrical processing system. The optical processing system includes a first coupler 1402, an interferometer 1403, an o / e converter 1404, a clock extractor 1406, an optical switch 1408, a second coupler 1411, and a delay device 1412. The electrical processing system is a toggle. A flip-flop 1405, an AND circuit 1407, a 2-bit delay device 1413, a first driver 1414, and a second driver 1415 are included. The optical switch 1408 includes a third coupler 14081, a first gate 14082, and a second gate 14083.

  Here, the component having the same name as that of the second embodiment exhibits the same function as the component of the second embodiment.

  The 2-bit delay unit 1413 delays the output signal of the o / e converter 1404 by a 2-bit period.

  The AND circuit 1407 performs an AND (logical product) operation of the output signal of the o / e converter 1404 and the bit delay unit 1413.

(F-2) Operation of Sixth Embodiment Next, the operation of the optical packet receiving apparatus of the sixth embodiment will be described with reference to FIG. 18 in addition to FIG. FIG. 18 is a timing chart of each part of the optical packet receiver according to the sixth embodiment.

  The input optical signal S1401 is partially branched by the first coupler 1402 and input to the clock extractor 1406 and the interferometer 1403.

  The clock extractor 1406 extracts a necessary clock component from the received optical signal and supplies it to each unit in order to synchronize within the receiving apparatus.

  The interferometer 1403 compares the optical phase of the input optical signal with two bits before the input optical signal, and “0” is obtained when the phases are matched and “1” when the phases are not matched. A signal S1403 is output.

  As described above, the input optical signal S1401 to the optical packet receiver is output by the optical packet transmitter of the fifth embodiment. When the destination changes, the third bit from the head of the packet is changed. In addition, phase modulation indicating change of destination is given. Therefore, in the output signal S1403 from the interferometer 1403, when the destination of the optical packet is changed, “1” is generated in the third bit and the fifth bit of the preamble period.

  This signal S1403 is converted into an electric signal by the o / e converter 1404 and then branched into two. One branch signal is delayed by a 2-bit period via a 2-bit delay device 1413 and input to the AND circuit 1407. The other branch signal is directly input to the AND circuit 1407.

  Accordingly, the output signal S1407 from the AND circuit 1407 becomes “1” in the fifth bit of the preamble period. This signal S1407 is input to the toggle flip-flop 1405. Every time "1" occurs in the signal S1407, output signals S14051 (Q output) and S14052 (Q / output) from the toggle flip-flop 1405 are Invert the logic level.

  Output signals S14051 (Q output) and S14052 (Q / output) from the toggle flip-flop 1405 are respectively amplified by the corresponding drivers 1414 and 1415 and then input to the corresponding gates 14082 and 14083 as gate control signals. .

  The optical packet signal that has passed through the first coupler 1402 is given a predetermined delay via the delay device 1412, and then branched into two by the third coupler 14081 and input to the gates 14082 and 14083.

  The gates 14082 and 14083 respectively control the input optical signal according to the gate control signals S14051 and S14052. As a result, the optical packet signals S14082 and S14083 separated from the gates 14082 and 14083 for each of the destinations a and b, respectively. Is output.

(F-3) Effect of Sixth Embodiment According to the sixth embodiment, one phase modulation bit attached to the leading bit of the optical packet signal is identified, and when the destination changes, the optical Switching (separation and extraction of destination-specific packets) can be performed while maintaining the signal state.

(G) Seventh Embodiment Next, a seventh embodiment of the present invention will be described with reference to the drawings. Here, the seventh embodiment is also an embodiment of the optical packet transmitter according to the present invention.

  The optical packet transmission apparatus according to the seventh embodiment is also based on the same technical idea as that of the fifth embodiment, and is an embodiment when the destination is 3 or more (hereinafter, 3 will be described as an example).

(G-1) Configuration of Seventh Embodiment FIG. 19 is a block diagram illustrating a schematic configuration of an optical packet transmission device according to the seventh embodiment.

  In FIG. 19, an optical packet transmission apparatus 1600 according to the seventh embodiment includes an optical processing system and an electrical processing system. As the electrical processing system, a buffer 1601, a latch circuit 1603, a first coder 1608, a second It has a coder 1604, a driver 1605, and a delay device (electric delay device) 1609, and an e / o converter 1602, a phase modulator 1606, and a delay device (optical delay device) 1607 as an optical processing system.

  The driver 1605, the buffer 1601, the e / o converter 1602, the phase modulator 1606, and the delay unit 1607 perform the same functions as the corresponding elements of the first embodiment.

  The first coder 1608 outputs a code corresponding to the destinations of the packets sequentially output from the buffer 1601 (2 bits because there are three destinations).

  The latch circuit 1603 latches the destination code output from the first coder 1608.

  The delay unit 1609 delays the destination code output from the first coder 1608 by a predetermined time.

  The second coder 1604 outputs a code having a timing pattern corresponding to the change amount of the destination from the latch destination code by the latch circuit 1603 and the destination code from the delay unit 1609. Here, if the destinations are a, b, c, and the cyclic direction of a → b → c → a... Is changed, the destination changes to the next element in the cyclic direction, that is, a → b, b → c, and so on. , C → a is the same destination change amount (first destination change amount), and destination change to the next element skipped by one in the cyclic direction, that is, a → c, b → a, and c → b Are the same destination change amount (second destination change amount), and the second coder 1604 outputs a code (code pattern) corresponding to such a destination change amount.

(G-2) Operation of Seventh Embodiment Next, the operation of the optical packet transmission apparatus of the seventh embodiment will be described with reference to FIG. 20 in addition to FIG.

  Packet signals input from the three systems are accumulated in the buffer 1601 and sequentially output. The signal output from the buffer 1601 is converted into an optical signal by the e / o converter 1602, then delayed through the delay unit 1607, and supplied to the phase modulator 1606.

  In addition, the signal output from the buffer 1601 is partially branched and input to the first coder 1608. The first coder 1608 outputs a 2-bit signal depending on the destination of the packet. For example, “00” is output if the destination is a, “01” is output if the destination is b, and “11” is output if the destination is c.

  Such a 2-bit signal is branched into two, and one branched 2-bit signal is input to the latch circuit 1603 and latched, and the latch output is input to the second coder 1604. The other branched 2-bit signal is delayed by one bit period of the packet by the delay unit 1609 and then input to the second coder 1604.

  The second coder 1604 compares the destination with the previous packet, synchronizes with the preamble of the packet, and a 3-bit signal S1604 (S16041, S16042, S16043) according to the timing of the third bit to the fifth bit of the preamble. ) Is output serially.

  It is assumed that the seventh embodiment also conforms to gigabit ether and has destinations a, b, and c. The second coder 1604 serially outputs “000” when the destination does not change in successive packets, and the destination changes by one step such as a → b, b → c, c → a in successive packets. Sometimes “100” is serially output, and “101” is serially output when the destination changes in two stages such as a → c, b → a, and c → b in successive packets.

  The output signal from the second coder 1604 is amplified by the driver 1605 and input to the phase modulator 1606.

  The packet signal converted into an optical signal by the e / o converter 1602 is input to the phase modulator 1606 via the delay unit 1607 and is subjected to phase modulation by the signal amplified by the driver 1605. The output signal from the driver 1605 has a voltage necessary for changing the phase of the optical signal by π.

  The electrical processing delay that occurs from the first coder 1608 to the second coder 1604 is absorbed by the function of the delay device 1607 described above.

  As described above, the optical packet transmitting apparatus according to the seventh embodiment outputs an optical signal having 3 phase modulation bits defining the destination at the third, fourth, and fifth bits of the preamble.

(G-3) Effect of Seventh Embodiment According to the seventh embodiment, for each destination, an optical packet signal is obtained by assigning 3 phase modulation bits characterizing that the destination has changed without assigning an optical phase to the destination. Can be granted.

  If the method shown in the seventh embodiment is expanded, an optical packet transmitter capable of providing a larger number of destinations can be easily realized.

(H) Eighth Embodiment Next, an eighth embodiment of the present invention will be described with reference to the drawings. Here, the eighth embodiment is an embodiment of the optical packet receiving apparatus according to the present invention, and corresponds to the optical packet transmitting apparatus of the seventh embodiment. The optical packet receiving apparatus according to the eighth embodiment may be provided in an apparatus that accommodates three communication terminals, or may be provided in an optical packet switch as a relay station. The optical packet transmitting apparatus having the configuration has a function of performing switching (separation for each destination) in an optical signal state.

  An optical packet transmission system including the optical packet transmission device of the seventh embodiment and the optical packet reception device of the eighth embodiment is an embodiment of the optical packet transmission system of the present invention.

(H-1) Configuration of Eighth Embodiment FIG. 21 is a block diagram illustrating a schematic main configuration of an optical packet reception device according to the eighth embodiment.

  The optical packet receiving apparatus of the eighth embodiment is an optical signal for both input and output, and is composed of an optical processing system and an electrical processing system. The optical processing system includes a first coupler 1902, an interferometer 1903, an o / e converter 1904, a clock extractor 1906, an optical switch 1908, a second coupler 1915, and a delay device 1914. The electric processing system includes an XOR circuit 1907, a 2-bit delay device 1905, a counter 1909, a function generator 1910, a first driver 1916, a second driver 1917, and a third driver 1918. The optical switch 1908 includes a third coupler 19081, a first gate 19082, a second gate 19083, and a third gate 19084.

  Here, the component having the same name as that of the sixth embodiment exhibits the same function as the component of the sixth embodiment.

  The XOR circuit 1907 determines whether or not the logic levels of the output signal of the o / e converter 1904 and the output signal of the 2-bit delay device 1905 match.

  The counter 1909 counts the coincidence output from the XOR circuit 1907 during the preamble period of a new packet. The counter 1909 is a binary counter, for example, and outputs a carry and resets every two input pulses.

  The function generator 1910 determines the destination of the new packet from the previous destination and the count value from the counter 1909, and sends the output “1” only to the output line for the determined destination among the three output lines. Is.

(H-2) Operation of Eighth Embodiment Next, the operation of the optical packet receiving apparatus of the eighth embodiment will be described with reference to FIGS. 22 and 23 in addition to FIG. 22 and 23 are timing charts of each part of the optical packet receiving apparatus according to the eighth embodiment.

  The input signal S 1901 is input to the clock extractor 1906 and the interferometer 1903 after branching by the first coupler 1902 and the second coupler 1915.

  The clock extractor 1906 extracts a necessary clock component from the input signal in order to synchronize within the receiving apparatus.

  The interferometer 1903 compares the optical phase with the previous two bits, and outputs “0” when the phases are matched and “1” when the phases are not matched.

  The signal S1901 output from the optical packet transmitter of the seventh embodiment is the third bit from the beginning of the packet when the destination is shifted by one such as a → b, b → c, c → a. When phase modulation indicating packet change is added and the destination is shifted by 2 such as a → c, b → a, c → b, the packet is changed to the 3rd and 5th bits from the beginning. Is given phase modulation. Therefore, when the destination of the optical packet signal is changed, the output signal S1903 of the interferometer 1903 is when the destination is shifted by one, when the destination is shifted by one, and when the destination is shifted by the third bit and the fifth bit. Causes “1” in the third and seventh bits.

  This signal S1903 is converted into an electrical signal by the o / e converter 1404 and then branched into two, and one branch signal is delayed by a 2-bit period via the 2-bit delay device 1403 and input to the XOR circuit 1907. The other branch signal is directly input to the XOR circuit 1907. As a result, the output signal S1907 from the XOR circuit 1407 is “1” in the third and seventh bits when the destination is shifted by one, and when the destination is shifted by two, The third bit, the fifth bit, the seventh bit, and the ninth bit are “1”.

  An output signal S1907 from the XOR circuit 1407 is input to the counter 1909. The counter 1909 outputs a signal each time two “1” s in the output signal S1907 are counted. Accordingly, the counter 1909 outputs a signal once when the destination is shifted by one in the preamble period, and outputs a signal twice when the destination is shifted by two.

  The function generator 1910 sets a destination that has been shifted in the destination circulation direction by the number of signals (1 or 2) from the counter 1909 from the previous destination as a new destination, and a new destination among the gate control signals S19101 to S19103. Only signals corresponding to are considered significant.

  Gate control signals S19101 to S19103 are amplified by corresponding drivers 1916, 1917, and 1918, respectively, and then input to corresponding gates 14082, 14083, and 14084.

  On the other hand, the main signal S1901 that has passed through the first coupler 1902 is branched into three by the third coupler 19081 and input to the gates 14082, 14083, and 14084.

  The input optical signal passes through the first gate 19082, the second gate 19083, and the third gate 19084 in accordance with the gate control signals S19101 to S19103, respectively. Therefore, the first gate 19082 is the optical packet signal S19082 of the destination a. The second gate 19083 outputs the optical packet signal S19083 of the destination b, and the third gate 19084 outputs the optical packet signal S19084 of the destination c.

(H-3) Effect of Eighth Embodiment According to the eighth embodiment, even when there are a plurality of destinations, packet switching is performed in the state of the optical signal using the inter-packet phase difference information of the optical packet signal. It is possible to provide high-speed packet switching.

  If the method shown in the eighth embodiment is expanded, an optical packet receiving apparatus capable of switching for a larger number of destinations can be configured.

(I) Other Embodiments In each of the above embodiments of the optical packet receiver, the interferometer shown in FIG. 5 is shown, but it is needless to say that other configurations may be applied. For example, it may be one that does not use reflection such as a branched optical coupler, a delay device, and a coupled optical coupler as shown in FIG. Note that the time delay for interference processing is not limited to a 2-bit period.

  Of course, the configuration for converting the phase signal obtained by the interferometer into the gate control signal is not limited to that in the above embodiments.

  Furthermore, in the third and fourth embodiments, an example in which three phases of 0, π / 3, and π are used is shown. Of course, a single phase may be applied.

  Furthermore, the gate for separating the optical packet signal is not limited to the EA modulator, and any other element can be used as long as it can control passage and non-passage by an electrical gate control signal. There may be.

  Further, as described above, the number of destinations (signal types) is not limited to two or three.

  Furthermore, since the fifth to eighth embodiments change the phase in accordance with the amount of change in the destination, it is necessary that the destination at the initial stage of communication be clear. The packet transmitting device and the optical packet receiving device may grasp the initial communication destination, and the initial communication destination is fixed to a certain destination a (if there is no communication data, a dummy packet is used). You may do it.

  In the seventh and eighth embodiments, the number of phase modulation bits is changed according to the amount of change in the destination. However, the phase modulation bit is fixed to the third bit, and the phase is changed to the destination. It may be changed to 0, π / 3, π in accordance with the amount of change. In this case, the discrimination of 0, π / 3, and π on the receiving side may be executed as in the fourth embodiment.

  In the fifth to eighth embodiments, the phase of the phase modulation bit position is changed according to the change amount of the destination. However, the entire period (or almost all) of the optical packet is changed according to the change amount of the destination. The phase of all periods may be changed.

  In the first to fourth embodiments, the phase of the entire period of the optical packet is changed according to the destination, but only the phase of the phase modulation bit position is changed according to the destination. Also good.

It is a block diagram which shows schematic structure of the optical packet transmitter of 1st Embodiment. It is each part timing chart of 1st Embodiment. It is explanatory drawing of operation | movement of the phase modulator of 1st Embodiment. It is a block diagram which shows schematic structure of the optical packet receiver of 2nd Embodiment. It is a block diagram which shows the detailed structural example of the interferometer of 2nd Embodiment. It is each part timing chart of 2nd Embodiment. It is a block diagram which shows schematic structure of the optical packet transmitter of 3rd Embodiment. It is each part timing chart of 3rd Embodiment. It is explanatory drawing of operation | movement of the phase modulator of 3rd Embodiment. It is a block diagram which shows schematic structure of the optical packet receiver of 4th Embodiment. It is a truth table showing the input / output relationship of the destination determination circuit of the fourth embodiment. It is a block diagram which shows the example of an internal structure of the decoder of 4th Embodiment. It is each part timing chart of 4th Embodiment. It is explanatory drawing of the output of the interferometer of 4th Embodiment. It is a block diagram which shows schematic structure of the optical packet transmitter of 5th Embodiment. It is each part timing chart of 5th Embodiment. It is a block diagram which shows schematic structure of the optical packet receiver of 6th Embodiment. It is each part timing chart of 6th Embodiment. It is a block diagram which shows schematic structure of the optical packet transmitter of 7th Embodiment. It is each part timing chart of 7th Embodiment. It is a block diagram which shows schematic structure of the optical packet receiver of 8th Embodiment. It is each part timing chart (1) of 8th Embodiment. It is each part timing chart (2) of 8th Embodiment. It is explanatory drawing which shows the other structural example of an interferometer.

Explanation of symbols

100, 400, 900, 1600 ... optical packet transmitter,
101, 401, 901, 1601 ... buffer,
102, 402, 902, 1602 ... e / o converter,
103, 406, 903, 1606 ... phase modulator,
104, 408, 904, 1604, 1608 ... coder,
200, 300, 1400, 1900 ... optical packet receiver,
202, 303, 1403, 1903 ... interferometer,
203, 304, 1404, 1904 ... o / e converter,
204 to 206 ... phase shift amount separation circuit,
207, 306, 1406, 1906 ... clock extractor,
208... Destination determination circuit,
209 ... Decoder,
210-212, 3082, 3083, 14082, 14083, 19082-19084 ... gate,
305, 1405 ... Toggle flip-flop,
403, 1603 ... latch circuit,
404, 1907 ... XOR circuit,
1407 AND circuit,
1413, 1609, 1905 ... delay devices,
1909 counter,
1910: Function generator.

Claims (12)

An electrical / optical conversion means for converting a serial electrical transmission signal in which packets of different destinations are mixed into an optical transmission signal;
Phase modulation means for making the phase of the carrier wave of the optical transmission signal correspond to a given phase control signal;
An optical packet transmission apparatus comprising: phase control means for forming the phase control signal to add destination information to the phase of the carrier wave of each packet according to the destination of each packet in the optical transmission signal. The optical packet transmission device according to claim 1,
An optical packet transmission apparatus characterized in that the phase of a carrier wave of each packet that is given and controlled as destination information by the phase control means corresponds to the destination of the packet on a one-to-one basis. The optical packet transmission device according to claim 1,
When considering a virtual circle in which the cyclic direction in which all the destinations are arranged cyclically is determined, the phase of each carrier wave that is assigned and controlled as the destination information by the phase control means is the phase of the packet immediately before it. An optical packet transmitter characterized by corresponding to the destination change amount on the virtual circle from the destination to the destination of the current packet. In the optical packet transmitter according to claim 3,
The optical packet transmission apparatus, wherein the phase control means forms a phase control signal to be supplied to the phase modulation means by an electrical hard logic circuit. In the optical packet transmitter according to any one of claims 1 to 4 ,
An optical packet transmitting apparatus characterized in that a phase of a carrier wave that is controlled to be given as destination information by the phase control means is given to the entire period of each packet. In the optical packet transmitter according to any one of claims 1 to 4 ,
An optical packet transmitting apparatus characterized in that a phase of a carrier wave that is controlled to be added as destination information by the phase control means is added to a position on the head side of each packet. The optical packet transmitter according to claim 6 , wherein
An optical packet transmitting apparatus, wherein a 1-bit period is used as a position on the head side of each packet, and the phase control means controls the phase of a carrier wave in the 1-bit period according to destination information. The optical packet transmitter according to claim 6 , wherein
An optical packet transmission characterized in that a plurality of bit periods are used as a position on the head side of each packet, and the phase control means controls a combination of carrier phases in the plurality of bit periods according to destination information. apparatus. A serial optical transmission signal in which the packets of different destinations are mixed and the phase of the carrier wave is changed according to the destination information is input, and the optical transmission signal is passed or not passed according to the given gate control signal. Performing as many gate means as the number of destinations;
Interferometer means for combining the optical transmission signal and a delayed optical transmission signal obtained by delaying the optical transmission signal by a predetermined time to generate an intensity change portion due to a phase change portion of the carrier;
Based on the intensity change part in the output signal of the interferometer means, the destination of the packet in the optical transmission signal is determined, and only the gate control signal to the gate means corresponding to the determined destination is represented as passing An optical packet receiving apparatus comprising: a control signal forming unit. The optical packet receiver according to claim 9 , wherein
The optical packet receiving apparatus characterized in that the gate control signal forming means obtains the phase change amount of the carrier wave based on the level of the intensity change portion in the output signal of the interferometer means and determines the destination of the packet. The optical packet receiver according to claim 9 , wherein
The optical packet receiving apparatus, wherein the gate control signal forming means determines a packet destination based on an appearance pattern of an intensity change portion in an output signal of the interferometer means within a predetermined short time. And optical packet transmission device according to claim 1, the optical packet transmission system which comprises an optical packet receiving apparatus according to claim 9.

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