JP3774449B2 - Synchronous multiplexed frame generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a synchronous multiplexing frame generator for testing the operation of a device used in a synchronous transmission system such as SDH or SONET, and performs an operation test of the device against various changes of a pointer inserted in a frame header. It relates to a technique for performing efficiently.
[0002]
[Prior art and problems to be solved]
In synchronous transmission systems such as SDH and SONET, multi-channel processing is performed in multiple stages, in which low-order frame data is multiplexed for multiple channels, stored in the payload, and a header is added to the payload to generate a high-order frame. Are generated and transmitted.
[0003]
When such a multiplexing process is performed, the storage position of the low-order frame in the high-order frame is timed due to an error in the bit rate of the low-order frame data to be multiplexed or a delay in the data signal path. The phenomenon that shifts with the progress of.
[0004]
In the synchronous transmission system, even if there is a shift in the storage position of such a low-order frame, it is stored in the payload at a predetermined position of the header of the high-order frame so that the low-order frame can be correctly extracted on the receiving side. A pointer value indicating the storage start position of the low-order frame of each channel and pointer information including information such as its change history are inserted for each channel, and the pointer value is increased or decreased according to the shift of the storage position. The low-order frame data of a required channel can be extracted from the position indicated by the pointer value corresponding to the channel. Note that the change of pointer information including the increase / decrease of the pointer value and the change of the storage position are called justification.
[0005]
Therefore, a device that receives a multiplexed data signal in a synchronous transmission system needs to be able to correctly extract a data signal of a desired channel from the multiplexed data signal even when pointer information changes.
[0006]
In order to evaluate the reception capability of the device for this justification, a multiplexed frame in which the pointer information and the storage position can be arbitrarily changed is required.
[0007]
As this type of multiplexed frame generator, there has conventionally been a device for changing the pointer value with respect to a fixed channel, as in Japanese Patent Application Laid-Open No. 2004-260, but in this case, an operation test for all channels is efficiently performed. In addition, there is a problem that various delays and frequency deviations occurring in an actual transmission system cannot be reproduced.
[0008]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 6-216872
An object of the present invention is to provide an apparatus for generating a synchronous multiplex frame which can improve this point and can efficiently perform an operation test of a device with respect to a change in pointer information in a state close to an actual environment. It is said.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a synchronous multiplexed frame generator according to claim 1 of the present invention comprises:
Low-order frame data generating means (21a to 21c) for generating low-order frame data for a plurality of channels to be stored in the payload portion of the high-order frame based on designated pointer information;
Pointer information storage means (22) for storing pointer information for each channel;
Each pointer information stored in the pointer information storage means is designated for each low-order frame data generation means, and the low-order frame data output from each low-order frame data generation means for the designated pointer information Pointer information designating means (23a-23c) for adding each pointer information to the frame data and outputting it;
Each low-order frame data and the pointer information are received, each pointer information is inserted into the header portion of the high-order frame, and each low-order frame data is indicated by the pointer value of the pointer information in the payload portion of the high-order frame Multiplexing means (24) for storing the position as a head position and generating higher-order frame data;
Among the pointer information stored in the pointer information storage means, the pointer information of the designated channel is changed, and the storage position of the lower order frame data stored in the payload part of the higher order frame data and the header part Justification means (25) for changing pointer information;
A channel change designating unit (26) for designating a channel for which pointer information is variable with respect to the justification unit, and sequentially changing the designated channel;
Increase / decrease change designating means (27) for instructing the justification means to increase, decrease or not change the pointer value for the channel designated by the channel change designation means and to sequentially change the increase / decrease designation. And have.
[0011]
According to a second aspect of the present invention, there is provided the synchronous multiplexing frame generator according to the first aspect of the present invention.
At least one of the channel change designation means and the increase / decrease change designation means performs channel change designation or pointer value increase / decrease change designation according to a pseudo-random pattern.
[0012]
According to a third aspect of the present invention, there is provided the synchronous multiplexed frame generator according to the first aspect of the present invention.
The operation of the channel designation change unit or the increase / decrease change designation unit is regulated so that the difference between the maximum value and the minimum value of the pointer value of the pointer information of each channel stored in each pointer information storage unit is equal to or less than a predetermined value. A channel phase difference limiting means (30) is provided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the case where the higher-order synchronous multiplexing frame is STM-1 which is the basic unit of SDH multiplexing will be described.
[0014]
As shown in FIG. 1, an STM-1 frame, which is a basic unit of SDH multiplexing, is composed of a 9 × 9 byte SOH (section overhead) and a 261 × 9 byte payload portion. Note that “higher order” and “lower order” in this specification simply indicate a relative relationship, and are similarly applied to the generation of higher order STM-4, STM-16, and STM-64. It shall be possible.
[0015]
In the payload portion of the STM-1 frame, for example, three-channel low-order frame data D1, D2, and D3 (these low-order frames are called virtual containers VC-3) are multiplexed and stored. In the fourth row, pointer information H1 _{1 to} H3 ₁ , H1 _{2 to} H3 ₂ , and H1 _{3 to} H3 ₃ for each low-order frame data is inserted.
[0016]
The pointer information H1 _{1 to} H3 ₁ includes a pointer value p1 indicating the storage head position in the payload portion of the low-order frame data D1 of the channel 1 and information related to the change of the pointer value (whether or not justification of the past several frames has occurred) The pointer information H1 _{2 to} H3 ₂ includes the pointer value p2 indicating the storage head position of the low-order frame data D2 of the channel 2 and information related to the change of the pointer value. Information H1 _{3 to} H3 ₃ includes a pointer value p3 representing the storage head position in the payload portion of the low-order frame data D3 of channel 3 and information related to the change of the pointer value.
[0017]
In the following description, pointer information for channel 1 is collectively referred to as h1, pointer information for channel 2 is collectively referred to as h2, and pointer information for channel 3 is collectively referred to as h3. Note that the notation in FIG. 1 is schematic, and the pointer information is also multiplexed and stored in the SOH.
[0018]
Further, in the case of STM-1, the storage area of each low-order frame data in the payload portion is set every third column in units of 1-byte width columns along the vertical direction as shown in FIG. ing.
[0019]
That is, the first column, the fourth column, the seventh column,..., The 259th column are the storage areas of the low-order frame data D1 of the first channel, the second column, the fifth column, the eighth column, The column,..., The 260th column is the storage area of the low-order frame data D2 of the second channel, the third column, the sixth column, the ninth column,..., The 261st column is the low of the third channel. This is a storage area for the next frame data D3.
[0020]
The pointer values p1 to p3 of the pointer information take values of 0 to 782 (= 9 × 261 / 3-1) in units of 1 × 1 byte storage areas for each channel, and the pointer value “ The position indicated by “0” is the first position of the fourth row in the payload portion that is continuous with the pointer information storage area of the SOH, and the tail end of the ninth row of the payload portion is the location indicated by the pointer value “521”, the payload The beginning of the first line of the part is the position indicated by the pointer value “522”, and the last position of the third line of the payload part is the position indicated by the pointer value “782”.
[0021]
As shown in FIG. 3, the synchronous multiplexed frame generator 20 for generating the multiplexed higher-order frame data (STM-1) stores the lower-order frame data D1 to D3 of each channel as shown in FIG. Each has low-order frame data generating means 21a, 21b, and 21c to be generated.
[0022]
Each low-order frame data generation means 21a to 21c generates low-order frame data D1, D2, and D3 for three channels to be stored in the payload portion of the high-order frame based on the designated pointer information h1 to h3. Generate each.
[0023]
These low-order frame data D1 to D3 are obtained by adding a POH (path overhead) necessary for error detection and alarm monitoring to a data signal of a predetermined pattern, and are designated by pointer information designation means 23a to 23c described later. Are output at a phase determined by the pointer information h1, h2, and h3.
[0024]
The pointer information storage means 22 stores pointer information h1 to h3 including information such as the current pointer value p1 for each channel and the presence / absence of justification occurrence in the past several frames.
[0025]
The pointer information designating means 23a to 23c designate the pointer information h1 to h3 stored in the pointer information storage means 22 for the low-order frame data generating means 21a to 21c, and for the designated pointer information. Then, the pointer information h1 to h3 is added to the low order frame data D1 to D3 output from the low order frame data generating means 21a to 21c, respectively, and output to the multiplexing means 24. In SDH, a combination of the low-order frame data and pointer information is called AU management data, and this pointer information is called an AU pointer.
[0026]
The multiplexing unit 24 receives the low-order frame data D1 to D3 and the pointer information h1 to h3, and inserts the pointer information h1 to h3 at a predetermined position in the header portion (SOH) of the high-order frame. The frame data D1 to D3 are respectively stored as the start positions of the low-order frame by storing the positions indicated by the pointer values p1 to p3 included in the pointer information h1 to h3 of the payload portion of the high-order frame, and the high-order frame data DA is generated. And output.
[0027]
Further, the justification unit 25 increases or decreases the pointer value of the designated channel among the pointer information h1 to h3 of each channel stored in the pointer information storage unit 22 based on the designated increase / decrease information. Thus, the storage positions of the low-order frame data D1 to D3 stored in the payload part of the high-order frame data DA and the pointer information h1 to h3 in the header part are sequentially changed.
[0028]
The channel change designation unit 26 designates a channel for which pointer information is to be changed with respect to the justification unit 25 and sequentially changes the designated channel.
[0029]
Further, the increase / decrease change designation means 27 designates the justification means 25 to increase, decrease or not change the pointer value for the channel designated by the channel change designation means 26, and sequentially designate the increase / decrease. change.
[0030]
The channel change designation means 26 and the increase / decrease change designation means 27 can be configured, for example, as shown in FIG.
[0031]
That is, as described above, when the number of channels of low-order frame data to be multiplexed is 3, there are eight patterns for designating channels (000) to (111), and these eight patterns are designated as channel change designation means. 26 and memory 26a, 27b of the increase / decrease change designation means 27.
[0032]
In the case of the channel change designation means 26, the address designation circuit 26b designates the read address for the memory 26a in synchronization with the clock signal C, and the pattern signal read from the designated address is justified as the channel designation signal. To the fiction means 25. In this case, for example, a channel whose pattern output is “1” is designated, and a channel whose “0” is not designated.
[0033]
On the other hand, in the case of the increase / decrease change designation means 27, the address designation circuit 27b designates the read address for the memory 27a in synchronization with the clock signal C, and the pattern signal read from the designated address and the channel change designation. A logical operation with the pattern signal read from the memory 26a on the means 26 side (here, an example of logical product is shown, but exclusive logic may be used) is performed for each bit in each of the logic circuits 27c to 27e, The logical operation output is output to the justification means 25 as an increase / decrease designation signal. In this case, for example, an increase is instructed when the logical operation output is “1”, and a decrease is instructed when the logical operation output is “0”.
[0034]
Here, when the address designating circuit 26b, 27b is composed of an octal counter that counts the clock signal C, and the address is designated by the count result, the number of combinations of channel and increase / decrease is limited to eight. However, for example, the addressing circuit 26b is composed of an octal counter, and the addressing circuit 27b is composed of a decimal counter, and 8 bits of the 9-bit count output. If the address is designated by the above, all 64 combinations can be obtained by 72 clock inputs.
[0035]
In addition, when addressing is performed with the counter output as described above, the address value changes regularly. At least one of the addressing circuits 26b and 27b is replaced with an 8-bit random pattern signal as a clock signal. If it is configured to output in synchronization with C, the total number of combinations does not change, but the channel and increase / decrease designation can be performed irregularly, and the same pattern channel designation can be continuous, It is possible to reproduce a state that occurs in an actual synchronous transmission system, such as continuous increase / decrease designation.
[0036]
The above-described configurations of the channel change designation unit 26 and the increase / decrease change designation unit 27 are merely examples. For example, without using the memories 26a and 27a, a counter of 6 bits or more that simply counts the clock signal C or 6 bits or more. May be used, and 3 bits of the output thereof may be used as a channel designation signal, and the remaining 3 bits may be used as an increase / decrease designation signal.
[0037]
The channel phase difference limiting unit 30 is configured to change the channel designation changing unit 26 so that the difference Δp between the maximum value and the minimum value of the pointer values p1 to p3 of each channel stored in the pointer information storage unit 22 is equal to or less than a predetermined value. Alternatively, the operation of the increase / decrease change designating unit 27 is restricted to limit the phase difference between channels within a predetermined value.
[0038]
For example, when the difference Δp between the maximum value and the minimum value of the pointer value approaches a predetermined value, the restriction by the channel phase difference limiting unit 30 is an increase designation for the channel having the maximum value and the minimum value. The difference Δp between the two is reduced by performing processing such as inverting the reduction designation for the channel.
[0039]
Next, the operation of the synchronous multiplexing frame generator 20 will be described.
For example, if the initial values of the pointer values p1 to p3 of the pointer information h1 to h3 stored in the pointer information storage means 22 are both “0”, the low order frame data generation means 21a to 21a that have received the pointer information. From 21c, as shown in FIG. 5, among the data for the first frame (87 × 9 bytes) to be transmitted, an amount (87 × 9) that can be stored after the fourth row of the payload portion of the higher-order frame 9 bytes) of data D1a, D1b, and D1c are output. Here, J1a to J1c indicate the head data of the POH of each low-order frame, and the remaining data D1b to D3b are output at the next multiplexing timing.
[0040]
These low-order frame data D1 to D3 are input to the multiplexing means 24 together with the pointer information h1 to h3.
[0041]
Therefore, as shown in FIG. 6, each of the pointer information h1 to h3 is inserted in the fourth row of the SOH from the multiplexing means 24, and the payload portion “0” in the payload portion continuous to the pointer information storage position is inserted. High-order frame data DA (STM-1) in which the low-order frame data D1 to D3 are stored starting from the position is generated and output in time series.
[0042]
For example, before the next multiplexing timing (which may be a multiplexing timing after a plurality of times), for example, the second channel and the third channel are designated by the channel change designation unit 26, and the increase / decrease change designation unit 27 When the increase of the pointer value p2 is designated for the second channel and the decrease of the pointer value p3 is designated for the third channel, the justification means 25 causes the pointer of the second channel of the pointer information storage means 22 to be designated. The value p2 is increased and updated by 1 to “1”, and the pointer value p3 of the third channel is decreased and updated by 1 to “782”.
[0043]
When the pointer information h1 to h3 whose pointer values are changed in this way is designated by the pointer information designation means 23a to 23c, as shown in FIG. 7, the lower order frame data generation means 21a outputs the previous time. Low-order frame data D1 composed of the remaining data D1b and 87 × 9 bytes of data D1a ′ of the second frame is output.
[0044]
The low-order frame data generating means 21b outputs low-order frame data D2 composed of the remaining data D2b of the previously output data and the data D2a ′ for 87 × 9-1 bytes of the next frame.
[0045]
The low-order frame data generating means 21c outputs low-order frame data D3 composed of the remaining data D3b of the previously output data and data D3a ′ for 87 × 9 + 1 bytes of the next frame.
[0046]
Therefore, as shown in FIG. 8, each pointer information H1 to H3 is inserted from the multiplexing unit 24 at a predetermined position of the SOH, and the remaining data D1b of the previous frame of the lower frame data D1 of the first channel is stored in the payload portion. The next frame data D1a ′ is stored in order starting from the head position “522”, and the payload portion “0” is stored at the head in the same manner as described above.
[0047]
Further, the remaining data D2b of the previous frame of the low-order frame data D2 of the second channel is sequentially stored from the beginning position “522” of the payload portion, and the data D2a ′ of the next frame starts from the position “1” of the payload portion. Stored.
[0048]
Further, the remaining data D3b of the previous frame of the low-order frame data D3 of the third channel is sequentially stored from the beginning position “522” of the payload portion, and the data D3a ′ of the next frame starts from the payload portion position “782”. Stored.
[0049]
In the same manner, the channel specification of the pointer information variable target and the pointer value increase / decrease specification are sequentially changed, and the storage start position and pointer information of each low-order frame data stored in the high-order frame according to the specification. Are automatically changed in sequence and output.
[0050]
Therefore, by inputting this high-order frame data DA to the device to be measured and performing error measurement or the like on the data of the channel received by the device, whether or not the device operates correctly with respect to the change of the pointer information. It can be determined efficiently.
[0051]
Further, as described above, when the variable target channel of pointer information or increase / decrease designation is performed at random, the device can be measured in a state closer to the actual data output from the actual synchronous transmission system.
[0052]
When the low-order frame data extracted from each high-order frame is stored in the internal memory on the measurement target device side and reconstructed as a series of channel data, the pointer is as described above on the transmission side. If the difference Δp between the maximum value and the minimum value of the pointer values p1 to p3 of each channel exceeds a predetermined value while repeating the information changing operation, the memory may overflow on the measurement target device side. .
[0053]
However, in the synchronous multiplexing frame generator 20 of this embodiment, as described above, the channel phase difference limiting unit 30 sets the maximum values of the pointer values p1 to p3 of each channel stored in the pointer information storage unit 22. Since the operation of the channel designation changing means 26 or the increase / decrease change designating means 27 is restricted so that the difference Δp from the minimum value is equal to or less than a predetermined value, the phase difference between channels is limited to a predetermined value or more. Thus, it is possible to prevent the overflow of the memory on the device side to be measured, and to perform the measurement smoothly.
[0054]
In the above description, the case where the pointer information is changed at each multiplexing timing, that is, every higher-order frame data generation cycle has been described. However, the pointer information change cycle is arbitrary, and the higher-order frame data A period that is a multiple of the generation period may be used.
[0055]
In addition, the change period of this pointer information may be changed regularly or irregularly, and if the change period is changed in this way, it can be brought closer to the synchronous diversion frame actually output by the synchronous transmission system, In addition, you can conduct tests in accordance with actual conditions.
[0056]
【The invention's effect】
As described above, the synchronous multiplexing frame generator of the present invention specifies the variable target channel of pointer information indicating each storage position of low-order frame data of a plurality of channels with respect to the payload of the high-order frame and the increase / decrease of the pointer value. Is specified sequentially.
[0057]
For this reason, the receiving capability of the apparatus with respect to the change of pointer information can be grasped efficiently.
[0058]
In addition, if the pointer information variable target channel or the increase / decrease designation is irregular, the data actually output by the synchronous transmission system can be reproduced, and the more practical operation of the measurement target device can be grasped.
[0059]
In addition, in order to limit the variable information channel of pointer information or increase / decrease designation so that the difference between the maximum value and the minimum value of the pointer value for each channel is not more than a predetermined value, Can be limited to a predetermined value or less, an overflow of the memory on the measurement target device side can be prevented, and smooth measurement can be performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a format of high-order frame data. FIG. 2 is a diagram showing a storage area of low-order frame data for a payload. FIG. 3 is a diagram showing a configuration of an embodiment of the invention. FIG. 5 is an operation explanatory diagram of the embodiment. FIG. 6 is an operation explanatory diagram of the embodiment. FIG. 7 is an operation explanatory diagram of the embodiment. Explanation of symbols]
20... Synchronous multiplexed frame generating device, 21 a to 21 c... Low-order frame data generating means, 22... Pointer information storage means, 23 a to 23 c. Justification means, 26 …… Channel change designation means, 27 …… Increase / decrease change designation means, 30 …… Channel phase difference limiting means

Claims (3)

Low-order frame data generating means (21a to 21c) for generating low-order frame data for a plurality of channels to be stored in the payload portion of the high-order frame based on designated pointer information;
Pointer information storage means (22) for storing pointer information for each channel;
Each pointer information stored in the pointer information storage means is designated for each low-order frame data generation means, and the low-order frame data output from each low-order frame data generation means for the designated pointer information Pointer information designating means (23a-23c) for adding each pointer information to the frame data and outputting it;
Each low-order frame data and the pointer information are received, each pointer information is inserted into the header portion of the high-order frame, and each low-order frame data is indicated by the pointer value of the pointer information in the payload portion of the high-order frame Multiplexing means (24) for storing the position as a head position and generating higher-order frame data;
Among the pointer information stored in the pointer information storage means, the pointer information of the designated channel is changed, and the storage position of the lower order frame data stored in the payload part of the higher order frame data and the header part Justification means (25) for changing pointer information;
A channel change designating unit (26) for designating a channel for which pointer information is variable with respect to the justification unit, and sequentially changing the designated channel;
Increase / decrease change designating means (27) for instructing the justification means to increase, decrease or not change the pointer value for the channel designated by the channel change designation means and to sequentially change the increase / decrease designation. A synchronous multiplexed frame generator. 2. The synchronous multiplexed frame generating apparatus according to claim 1, wherein at least one of the channel change designation means and the increase / decrease change designation means performs channel change designation or pointer value increase / decrease change designation according to a pseudo-random pattern. . The operation of the channel designation change means or the increase / decrease change designation means is regulated so that the difference between the maximum value and the minimum value of the pointer value of the pointer information of each channel stored in each pointer information storage means is not more than a predetermined value. 3. The synchronous multiplexing frame generator according to claim 1, further comprising a channel phase difference limiting means (30) for performing the processing.

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