CN113285852A - Method for realizing multi-path E1 signal synchronous test - Google Patents
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Abstract
The invention discloses a method for realizing multi-path E1 signal synchronous test, which comprises the following steps: loading a plurality of test signals E1 with the transmission rate of 2048kbit/s into a container of C-12, adjusting the code speed of a test signal E1, adding a plurality of test signals E1 subjected to code speed adjustment into low-order channel overhead LPOH to form a low-order virtual container VC-12 signal, adding the low-order virtual container VC-12 signal into a branch unit pointer TU-12PTR corresponding to VC-12 to form a branch unit TU-12 signal, and combining the branch unit TU-12 signals according to byte interpolation to form a first branch unit TUG-2 signal.
Description
Technical Field
The invention relates to the technical field of network element testing, in particular to a method for realizing synchronous testing of multiple paths of E1 signals.
Background
E1 is a telecommunications standard, and china adopts the E1 standard in europe. One time division multiplexing frame (with the length of T =125 us) of E1 is divided into 32 equal time slots, and the number of the time slots is CH 0-CH 31. The time slot CH0 is used for frame synchronization, the time slot CH16 is used for signaling, and 30 time slots of the rest of CH 1-CH 15 and CH 17-CH 31 are used for 30 speech channels. Each slot carries 8 bits and therefore shares 256 bits. 8000 frames per second are transmitted, so the data rate of the PCM sub-group E1 is 2.048 Mbit/s.
At present, most SDH/PDH instruments are single E1 signal interfaces, each instrument can only support two network element cascades due to the limitation of the cascade connection, the test efficiency is low, although the current E1 channel can also adopt a daisy chain connection mode similar to the Ethernet to test, because the E1 channel is mainly used for circuit simulation service (CES), the TDM service has higher requirement on time delay, when designing the daisy chain test of the E1 port, too many E1 ports are not suitable to be cascaded, and the circuit time delay is increased due to the too much cascade connection to cause frequency offset.
Disclosure of Invention
This section is for the purpose of summarizing some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. In this section, as well as in the abstract and the title of the invention of this application, simplifications or omissions may be made to avoid obscuring the purpose of the section, the abstract and the title, and such simplifications or omissions are not intended to limit the scope of the invention.
The present invention has been made in view of the above and/or problems with the prior art E1 signal.
Therefore, an object of the present invention is to provide a method for implementing a synchronous test of multiple paths of E1 signals, which can test multiple network elements synchronously, improve test efficiency, and avoid the problem of frequency offset.
To solve the above technical problem, according to an aspect of the present invention, the present invention provides the following technical solutions:
a method for realizing multi-path E1 signal synchronous test comprises the following steps:
s1, loading a plurality of test signals E1 with the transmission rate of 2048kbit/S into a container of C-12, and adjusting the code rate of the test signals E1;
s2, adding the test signals E1 after code rate adjustment into low-order channel overhead LPOH to form a low-order virtual container VC-12 signal;
s3, adding the low-order virtual container VC-12 signal into a tributary unit pointer TU-12PTR corresponding to VC-12 to form a tributary unit TU-12 signal;
s4, forming first branch unit TUG-2 signals by interleaving and combining the branch unit TU-12 signals according to bytes, wherein each first branch unit TUG-2 signal consists of three branch unit TU-12 signals;
s5, forming second branch unit group TUG-3 signals by byte interleaving and combining the first branch unit group TUG-2 signals, wherein each second branch unit group TUG-3 signal consists of seven first branch unit group TUG-2 signals;
s6, combining the second branch unit group TUG-2 signals by byte interpolation and adding the combined signals into a high-order channel overhead HPOH to form high-order virtual container VC-4 signals, wherein each high-order virtual container VC-4 signal consists of three second branch unit group TUG-2 signals and one high-order channel overhead HPOH;
s7, adding the VC-4 signal of the high-order virtual container into the AU-4PTR corresponding to VC-4 to form an AU-4 signal of a management unit;
s8, combining the AU-4 signals according to byte interpolation to form an AUG signal, wherein one AUG signal corresponds to one AU-4 signal;
s9, multiplexing each AUG signal according to the interleave synchronization and adding section overhead to form an STM-1 signal;
and S10, decomposing the STM-1 signal into 63 paths of E1 signals, and respectively sending the decomposed 63 paths of E1 signals to the tested network elements which are connected with the 63 ports in a one-to-one correspondence manner.
As a preferable scheme of the method for implementing the multi-path E1 signal synchronization test according to the present invention, in step S10, each tested cell is connected to a port on the switch in a one-to-one correspondence manner, and the decomposed 63 paths of E1 signals are transmitted to the tested cell through the switch in a one-to-one correspondence manner.
As a preferable scheme of the method for implementing the synchronous test of the multiple paths of E1 signals, in step S10, the specific steps of decomposing the STM-1 signal into 63 paths of E1 signals are as follows:
s101, transmitting an STM-1 signal to a cross matrix disc through an STM-1 signal port;
s102, the TM-1 signal is decomposed into 63 paths of E1 signals by the cross matrix disc.
As a preferable scheme of the method for realizing the synchronous test of the multi-path E1 signal, the cross matrix disc is constructed by a 1662SMC synchronous multiplexer.
Compared with the prior art, the invention has the beneficial effects that: each low-order virtual container VC-12 signal represents one path of E1, STM-1 signals of virtual containers containing 63 VC-12 are constructed through multiplexing mapping, the signals are sent to a cross matrix disc through STM-1 signal ports, the STM-1 signals are decomposed into 63 paths of E1 signals by the cross matrix disc and are respectively sent to 63 ports, tested network elements connected with the 63 ports in a one-to-one correspondence mode are tested, 63 synchronous network element synchronous tests are achieved, test efficiency is greatly improved, equipment investment cost is saved, and the problem of frequency deviation is avoided.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail with reference to the accompanying drawings and detailed embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise. Wherein:
FIG. 1 is a flow chart of a method for implementing a synchronous test of multiple E1 signals according to the present invention;
fig. 2 is a multiplexing mapping structure diagram constructed by a method for implementing synchronous testing of multiple E1 signals according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Next, the present invention will be described in detail with reference to the drawings, wherein for convenience of illustration, the cross-sectional view of the device structure is not enlarged partially according to the general scale, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The invention provides a method for realizing the synchronous test of multi-path E1 signals, which can synchronously test a plurality of network elements, improve the test efficiency and avoid the problem of frequency deviation.
The method for realizing the multi-path E1 signal synchronous test firstly builds a multiplexing mapping structure and a cross matrix disc as shown in FIG. 2 through hardware. Specifically, in this embodiment, a multiplexing mapping structure is constructed by using the ONT503 analyzer of a single DSU, and a 1662SMC synchronous multiplexer is selected to construct the cross matrix disk.
A method for implementing the multi-path E1 signal synchronization test is described in detail below with reference to fig. 1-2.
S1, loading a plurality of test signals E1 with the transmission rate of 2048kbit/S into a container of C-12, and adjusting the code rate of the test signals E1;
s2, adding the test signals E1 after code rate adjustment into low-order channel overhead LPOH to form a low-order virtual container VC-12 signal;
s3, adding the low-order virtual container VC-12 signal into a tributary unit pointer TU-12PTR corresponding to VC-12 to form a tributary unit TU-12 signal;
s4, forming first branch unit TUG-2 signals by interleaving and combining the branch unit TU-12 signals according to bytes, wherein each first branch unit TUG-2 signal consists of three branch unit TU-12 signals;
s5, forming second branch unit group TUG-3 signals by byte interleaving and combining the first branch unit group TUG-2 signals, wherein each second branch unit group TUG-3 signal consists of seven first branch unit group TUG-2 signals;
s6, combining the second branch unit group TUG-2 signals by byte interpolation and adding the combined signals into a high-order channel overhead HPOH to form high-order virtual container VC-4 signals, wherein each high-order virtual container VC-4 signal consists of three second branch unit group TUG-2 signals and one high-order channel overhead HPOH;
s7, adding the VC-4 signal of the high-order virtual container into the AU-4PTR corresponding to VC-4 to form an AU-4 signal of a management unit;
s8, combining the AU-4 signals according to byte interpolation to form an AUG signal, wherein one AUG signal corresponds to one AU-4 signal;
s9, multiplexing each AUG signal according to the interleave synchronization and adding section overhead to form an STM-1 signal;
and S10, decomposing the STM-1 signal into 63 paths of E1 signals, respectively sending the decomposed 63 paths of E1 signals to the tested network elements which are connected with 63 ports in a one-to-one correspondence manner, wherein each tested network element is connected with a port on the switch in a one-to-one correspondence manner, and the decomposed 63 paths of E1 signals are correspondingly transmitted to the tested network elements through output ports of the switch in a one-to-one correspondence manner. And the specific steps of decomposing the STM-1 signal into 63 paths of E1 signals are as follows: s101, transmitting an STM-1 signal to a cross matrix disc through an STM-1 signal port; s102, the TM-1 signal is decomposed into 63 paths of E1 signals by the cross matrix disc.
As shown in fig. 2, the above steps S1-S9 are performed in the multiplexing mapping structure constructed by the ONT503 analyzer, and 63 low-order virtual containers VC-12 signals are multiplexed and mapped into one STM-1 signal, wherein one E1 is mapped into one VC12, packaged into TU12 and specified by ITU-T, TU12 × 3= TUG2, TUG2 × 7= TUG3, and TUG3 × 3= AU4, so that one STM-1 can be divided into 3 × 7 × 3=63 VC12, that is, 63E 1.
Step S10 decomposes the STM-1 signal into 63 paths of E1 signals, so that each path of E1 signal can be synchronously transmitted to 63 network elements to be tested that are connected to 63 ports in a one-to-one correspondence, and the 63 network elements to be tested are synchronously tested.
The method for realizing the synchronous test of the multi-path E1 signals comprises the steps that each low-order virtual container VC-12 signal represents one path of E1, STM-1 signals of virtual containers containing 63 VC-12 are constructed through multiplexing mapping and are sent into a cross matrix disc constructed by a 1662SMC synchronous multiplexer through an STM-1 signal port, the STM-1 signals are decomposed into 63 paths of E1 signals by the cross matrix disc and are respectively sent to 63 ports, tested network elements connected with the 63 ports in a one-to-one correspondence mode are tested, the synchronous test of 63 synchronous network elements is realized, the test efficiency is greatly improved, the equipment investment cost is saved, and the problem of frequency deviation is also avoided.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein. A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display.
As used in this application, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being: a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of example, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
While the invention has been described above with reference to an embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the various features of the disclosed embodiments of the invention may be used in any combination, provided that no structural conflict exists, and the combinations are not exhaustively described in this specification merely for the sake of brevity and resource conservation. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (4)
1. A method for realizing multi-path E1 signal synchronous test is characterized by comprising the following steps:
s1, loading a plurality of test signals E1 with the transmission rate of 2048kbit/S into a container of C-12, and adjusting the code rate of the test signals E1;
s2, adding the test signals E1 after code rate adjustment into low-order channel overhead LPOH to form a low-order virtual container VC-12 signal;
s3, adding the low-order virtual container VC-12 signal into a tributary unit pointer TU-12PTR corresponding to VC-12 to form a tributary unit TU-12 signal;
s4, forming first branch unit TUG-2 signals by interleaving and combining the branch unit TU-12 signals according to bytes, wherein each first branch unit TUG-2 signal consists of three branch unit TU-12 signals;
s5, forming second branch unit group TUG-3 signals by byte interleaving and combining the first branch unit group TUG-2 signals, wherein each second branch unit group TUG-3 signal consists of seven first branch unit group TUG-2 signals;
s6, combining the second branch unit group TUG-2 signals by byte interpolation and adding the combined signals into a high-order channel overhead HPOH to form high-order virtual container VC-4 signals, wherein each high-order virtual container VC-4 signal consists of three second branch unit group TUG-2 signals and one high-order channel overhead HPOH;
s7, adding the VC-4 signal of the high-order virtual container into the AU-4PTR corresponding to VC-4 to form an AU-4 signal of a management unit;
s8, combining the AU-4 signals according to byte interpolation to form an AUG signal, wherein one AUG signal corresponds to one AU-4 signal;
s9, multiplexing each AUG signal according to the interleave synchronization and adding section overhead to form an STM-1 signal;
and S10, decomposing the STM-1 signal into 63 paths of E1 signals, and respectively sending the decomposed 63 paths of E1 signals to the tested network elements which are connected with the 63 ports in a one-to-one correspondence manner.
2. The method according to claim 1, wherein in step S10, each tested cell is connected to a port on the switch in a one-to-one correspondence manner, and the decomposed 63 paths of E1 signals are transmitted to the tested cell through the switch in a one-to-one correspondence manner.
3. The method for realizing the synchronous test of the multiple E1 signals according to claim 1, wherein in the step S10, the specific steps of decomposing the STM-1 signal into 63E 1 signals are as follows:
s101, transmitting an STM-1 signal to a cross matrix disc through an STM-1 signal port;
s102, the TM-1 signal is decomposed into 63 paths of E1 signals by the cross matrix disc.
4. The method of claim 3 wherein the cross matrix disk is constructed from a 1662SMC synchronous multiplexer.
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