WO2003063396A1

WO2003063396A1 - Method and apparatus for measuring differential delay in a sonet/sdh-system using virtual concatenation

Info

Publication number: WO2003063396A1
Application number: PCT/GB2003/000092
Authority: WO
Inventors: Atanu Nag; Mark Rhodes; Kjell Inge Johnsen
Original assignee: Agilent Technologies, Inc.
Priority date: 2002-01-16
Filing date: 2003-01-13
Publication date: 2003-07-31
Also published as: GB0200918D0

Abstract

Differential delay affecting data communicated through a communications system is measured by generating a test data signal simulating differential delay. The test data signal traverses communications equipment under test, and the data signal is monitored as it is output from the communications equipment to derive an indication of differential delay.

Description

Method and Apparatus for Measuring Differential Delay in a SONET/ SDH - system using virtual concatenation

Technical Field

[0001] This invention relates to methods and apparatus for measuring differential delay affecting data transferred through communications equipment, such as a communications network using SONET/SDH technology.

Background Art

[0002] SONET/SDH virtual concatenation links are subj ect to differential delays as virtual containers are routed through different network paths. One of the most challenging aspects of a virtual concatenation data transport system is the re-assembly of containers at the path terminating equipment, which have been subject to differential delay as they traversed different network paths. [0003] Concatenation can be used to transport payloads that do not fit efficiently into the standard set of SONET/SDH VCs (virtual containers). It is a procedure whereby a multiplicity of virtual containers is associated with one another with the result that their combined capacity can be used as a single container across which bit sequence integrity is maintained. [0004] Two types of concatenation are defined: contiguous (VC-n-Xc) and virtual (VC-n-Xv). Both of them provide the same concatenated bandwidth (X times the container-n size) at the path termination, but the method of transportation over the intermediate network is different. Contiguous concatenation maintains the bandwidth throughout the whole transport, which means that the intermediate network between the path terminating equipment must support this bandwidth. [0005] Virtual concatenation segments the contiguous bandwidth into standard SONET/SDH VCs (higher order VC-3/4 or lower order VC-1/2), transports the individual VCs and re-combines them to a contiguous bandwidth at the receiving node (path terminating equipment - PTE). So virtual concatenation groups X STS-1 s/VC-3s or STS-3cs/VC-4s into a single 'virtually concatenated' tributary and enables the creation of "right-sized" pipes in 51 Mbps and 155 Mbps granularity. This means that virtual concatenation-compatible equipment can be installed into the current infrastructure without major modifications and is compatible with legacy SONET equipment which can handle only VC-3 and VC-4 containers and cannot handle the larger contiguously concatenated payloads such as VC-4-4c/16c/64c. Virtual concatenation takes advantage of the ability of an existing SONET/SDH network to transport STS1/VC-3 or STS-3c/VC-4 signals, and builds higher capacity payloads by logically grouping individual VC-3s or VC-4s, which are transmitted individually and realigned at the receiver. The intermediate nodes in the network do not need to know that they are carrying a virtually concatenated payload and hence, it makes it easy to add virtual concatenation features to an existing SONET/SDH network by replacing only the source and sink nodes.

[0006] The virtual concatenation capable transmitter needs to provide each Synchronous Payload Envelope (SPEVVC with information about its concatenated group identity and its position/sequence within the group. It also needs to give each SPE/VC its own path overhead (POH), which allows the individual processing in the intermediate network.

[0007] As all the virtual containers within a virtually concatenated group are routed individually through the network, there is a possibility that virtual containers belonging to the same frame will arrive at different times at the receiving PTE. The transport delay among the virtual containers within a virtual concatenated group is known as differential delay. The differential delay can be classified as:

- Delays less than 125 μs due to pointer adjustments (0 to 782 pointers in a SONET frame);

- Delays greater than 125 μs due to network routing delays (up to 4096 frame delay as allowed by the 12-bits of multi-frame indicator in the H4 byte).

[0008] Unlike contiguous concatenation (where all the n STS- 1 SPEs forming the STS-Nc are transported and switched as one entity and there is a need for only one STS pointer to be processed), in virtual concatenation there is individual pointer processing for all the n STS-1 SPE's/VC-3s in an STS-l-nv/VC-3-Xv. Since the individual STS-ls/VC-3s are not locked to each other as in an STS-Nc, the STS-1 s/VC-3s are allowed to float with respect to each other within the OC-N/STM-N frame. Therefore receivers supporting virtual concatenation are required to incorporate some amount of buffer space to accommodate differential delays among the arriving STS-ls. The receivers need to store the incoming data until the latest SPE/VC arrives, when re-alignment can be performed to extract the payload embedded in the STS-l-Xv structure. [0009] The receiver re-aligns the virtual containers based on the information of the H4 byte carried within the POH section of each VC. The H4 byte has the multi-frame and sequence number information. When a multi-frame has been successfully received, the multi-frame indicator (MFI1 and MFI2 fields in the H4 byte) is used to realign the individual channels, and then the sequence indicator (SQ) is used to sequence the channels. A total of 12 bits are reserved for the MFI1 and MFL2 fields which amounts to 4096 frames. So with a 12-bit multi-frame indicator, a delay of 4096 frame time => 4096 x 125μs = 512 ms => +/- 256 ms can be detected by the receiver. Thus a virtual-concatenation capable receiver can possibly detect a maximum delay of +/- 256 ms (as allowed by the standard) among the virtual containers and buffer and perform re-alignment of the delayed VCs. It is understood that a challenging aspect of the receiver design will be to perform re-construction of the containers delayed by up to +/- 256 ms.

[0010] So for a virtual concatenation test system one of the things to test is the virtual container re-alignment capability of the receiver.

[0011] A Virtual Concatenation test system needs to generate delayed virtual containers in order to test the re-alignment functionality of a receiver. One way of introducing delay would be to buffer the transmit data in a memory and read out the data for a channel from the memory after the delayed period. This is shown in Figure 1.

[0012] The memory is more like a multi-channel buffer/FIFO. If channel X is to be delayed, then channel X data is accumulates in the Channel X buffer area until the delay period elapses and then the data is read out from the channel X buffer.

[0013] The complexity of the problem associated with generating delayed virtual containers can be appreciated if we see the buffer requirements for the various delays. Table 1 below shows the minimum buffer-size needed per channel when that channel is to be delayed by T ms with respect to the other virtual containers of a VC-3-Xv virtually concatenated group. A maximum differential delay of +/- 256 ms corresponds to a delay of 512 ms. Considering an STS-1 SPE/VC-3 having 9 rows and 87 columns (3 columns of SOH), a VC-3 container has 783 bytes of payload.

Table 1

( Formula used: ( (9 rows*87columns* (delay/0.125) ) / 1024) )

[0014] So if a single VC-3 container is to be delayed by 512 ms (differential delay of 256 ms), there is a buffer requirement of 3 MB for that channel. For n channels delayed within the VC-3-Xv group, the buffer requirement is n*3 MB. So, considering 20 channels in a

VC-3-21 v group (Gigabit Ethernet - GbE - data) being delayed by 512 ms, a huge memory of 20*3 MB = 60 MB (approx.) would be required. If we consider other data sources higher than GbE rate, the memory requirement is further increased.

[0015] In a typical application, Ethernet is carried over SONET using a VC-3-21v virtual concatenation mapping. Implementation using the method above, allowing independent control of each individual channel's differential delay up to 512 ms, requires a memory of 3 MB per channel. So to allow the flexibility of any channel being delayed there is the need for 21 * 3 = 63 MB of buffer space. Apart from the huge memory requirements, there is also the need for memory throughput to be at least twice the SONET/SDH line rate as we would have to read and write from the memory simultaneously. STM-16 rates would require at least 5 Gb/s of memory bandwidth and for STM-64, 20 Gb/s! The memory control and buffer management logic requirements in this type of implementation also present a significant challenge.

[0016] This invention provides a simple method and apparatus for generating differential delay among different containers in order to stress test a communications link. This method of differential delay generation has applications in other communications devices, equipment and systems and is not specifically limited to virtual concatenation which is presented solely by way of an application example.

Disclosure of Invention [0017] According to one aspect of this invention there is provided a method of measuring differential delay affecting data communicated through a communications system, comprising the steps of: generating a test data signal simulating differential delay; causing the test data signal to traverse communications equipment; and monitoring the data signal as it is output from the communications equipment and deriving an indication of differential delay therefrom.

[0018] According to another aspect of this invention there is provided an apparatus for measuring differential delay affecting data communicated through a communications system, comprising the steps of: a signal generator for generating a test data signal simulating differential delay; an interface for causing the test data signal to traverse communications equipment; and a monitor for monitoring the data signal as it is output from the communications equipment and deriving an indication of differential delay therefrom. [0019] According to a further aspect of the invention a SONET/SDH payload signal (for example) is synthesised such that each data channel consists of a repeating pattern of bytes.

This simplifies the implementation of simulated differential delay between SONET/SDH payload containers.

[0020] The inventors hereof have realised that there exist specific cases where a valid payload can consist of an identical repeating frame. For example, the size of this repeating frame can be constructed such that it begins on channel 1 of a VC-3-Xv virtual concatenation and ends on channel X. A payload frame of this specific size also results in a repeating pattern of bytes in each channel. Calculation of the byte sequence for an individual channel for any point in time then becomes a trivial matter. In an instrument based on this principle, the channel buffer size required for differential delay simulation is only dependent on the length of the repeating byte sequence and is independent of the differential delay being simulated. [0021] The benefits are particularly apparent when applied to the simulation of differential delay in Virtual Concatenation for communications test systems but are not limited to this application.

Brief Description of Drawings [0022] A method and apparatus in accordance with this invention, for measuring differential delay, will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows the use of memory to buffer transmit data, to be read out for a channel after a delay period; Figure 2 shows apparatus for implementing the present invention;

Figure 3 shows how a 72-byte Generic Framing Procedure (GFP) frame can be byte split between twelve different channel RAMs for a VC-3-12v mapping;

Figure 4 shows a test data transmission frame without differential delay; and Figure 5 shows a test data transmission frame with channel 11 delayed by one byte.

Best Mode for Carrying Out the Invention, & Industrial Applicability

[0023] It has been found that a simple repeating pattern can be used to generate delayed virtual containers. Such a repeating pattern will significantly reduce the amount of buffering needed to generate delayed virtual containers during virtual concatenation differential delay test. The idea is to store a predetermined pattern in each channel and continuously transmit the pattern. This means that there will be no need for additional buffering to delay a channel as the contents of a channel are already known and one needs to just stop transmitting the pattern during the delay period.

[0024] One of the applications of the above scheme is for Ethernet over SONET applications where Ethernet frames are encapsulated in GFP frames before being virtually concatenated onto a SONET link. Let us consider the following virtual concatenation mappings: - VC-3-Xv, where X = 2 to 21 ; - VC-4-Xv, where X = 2 to 7.

[0025] The repeating pattern will be a valid Ethernet frame encapsulated in a frame-mapped GFP frame. It is assumed that the Ethernet frame has a fixed overhead of 22 bytes and the GFP frame has a standard header of 8 bytes. By ensuring that the predetermined GFP frame has a frame size that is divisible by the number of provisioned channels (value of X in VC-3-Xv/VC-4-Xv), i.e.2 to 21, the memory requirement will be greatly reduced as only one GFP frame needs to be stored. In other words, the predetermined GFP frame will be split (byte interleaved) among the provisioned channels such that the first byte of the GFP frame will always be transmitted in the same channel during the transmission of the pattern. [0026] It is desirable to keep the GFP frame as small as possible to keep the buffer associated with each channel as small as possible.

[0027] Valid GFP frame size is 42- 1500 bytes of payload + Ethernet and GFP overhead (30 bytes). This means that the minimum valid GFP frame will be 72 bytes, while the maximum GFP frame will be 1530 bytes. Table 2 shows the minimum valid GFP frame size, which can be repeated for each of the different mappings (VC-3-Xv and VC-4-Xv). Notice that the buffer size will never exceed 36 bytes per channel (72 bytes/2 channels).

Table 2

[0028] Table 3 shows that it is possible to reduce the number of patterns from 8 to 6 by increasing the frame size. Note that the buffer requirement is unchanged.

Table 3 [0029] As seen in the previous section, using the repeating pattern of GFP frames, the buffer requirement is 36 bytes per channel -i 36 x 21 = 756 bytes for generating any differential delay among the virtual containers. This is significantly less than the ~63 Mbytes of buffer requirement (for differential delays up to +/- 256 ms) for the case when a stream of GFP encapsulated Ethernet data is to be delayed/buffered and sent.

[0030] Once the pattern has been split up and stored in the memory, any channel can be delayed for any period of time by delaying the transmission of the data stored in the memory associated with that channel. Figure 2 shows how the pattern is split between X different channel RAMs. The delay function indicated in the figure can be realised in practice by simply not transmitting the data stored in the memory, so no extra buffering or delay circuitry is needed.

[0031] A repeating pattern of GFP frames such as frame 10 is passed through a byte-wide de-multiplexer 12 where the number of output ports of the de-multiplexer corresponds to the number of channels within the virtually concatenated group (parameter X in VC-3-Xv or VC-4-Xv). Each byte stream from the de-multiplexer maps to each of the individual channels within the group. This division into channels is necessary as individual VC-3 channels are time-division multiplexed in a SONET/SDH frame and we need to be able to introduce differential delay on a per-channel basis. The channelized data are then fed to respective dual-port RAM blocks 14 (which could be implemented in field programmable gate array (FPGA) block RAMs) for each of the data streams. The data from each of the RAMs 14 are read out simultaneously (for the zero-delay case) and passed through a byte- wide multiplexer 16 to re-assemble the original pattern of frames. For each channel to which a delay is to be applied, the data from the respective RAM is effectively delayed as indicated functionally at 18, by suspending reading out of that RAM's contents for the desired period of the delay affecting that channel. So any combination of channels can be delayed for any period of time by simply not reading the corresponding channel RAM(s) during that period. [0032] Figure 3 shows an example of how a 72-byte GFP frame will be byte split between the 12 different channel RAMs for a VC-3-12v mapping. In other words this figure shows how the frame is split and stored in the individual channel memory. [0033] Figure 4 shows data transmission without any differential delay. Notice the repeating byte sequence in each channel.

[0034] Figure 5 shows how the data are transmitted when channel 11 has been delayed by one byte, i.e. no data is transmitted from memory for that channel during the first clock cycle.

Claims

1. A method of measuring differential delay affecting data communicated through a communications system, comprising the steps of: generating a test data signal simulating differential delay; causing the test data signal to traverse communications equipment; and monitoring the data signal as it is output from the communications equipment and deriving an indication of differential delay therefrom.

2. The method of claim 1, wherein the test data signal contains a plurality of data channels and is generated such that each data channel consists of a repeating pattern of bytes.

3. Apparatus for measuring differential delay affecting data communicated through a communications system, comprising the steps of: a signal generator for generating a test data signal simulating differential delay; an interface for causing the test data signal to traverse communications equipment; and a monitor for monitoring the data signal as it is output from the communications equipment and deriving an indication of differential delay therefrom.

4. A method of generating a test data signal simulating differential delay, wherein the test data signal contains a plurality of data channels and is generated such that each data channel consists of a repeating pattern of bytes.