JP2022515844A - Signal delay device and simulator device that simulates the spatial distance in an electromagnetic wave-based distance measuring device - Google Patents

Abstract

The present invention relates to a signal delay device (4) that simulates a spatial distance in an electromagnetic wave-based distance measuring device (8). The underlying problem of the present invention is to improve the distance resolution. This task is one demultiplexer (11), D delay devices (12a-12d), D additional delay devices (13a-13d), one multiplexer (14), and one control device. It is solved by the signal delay device (4) having (15) and. The demultiplexer (11) has one demultiplexer input unit (16) and D demultiplexer output units (17a to 17d). Each of the D delay devices (12a-12d) has one delay input section (18a-18d) and one delay output section (19a-19d). Each of the D additional delay devices (13a to 13d) has one additional delay input unit (20a to 20d) and one additional delay output unit (21a to 21d). The multiplexer (14) has 2 × D multiplexer input units (22a to 22h) and one multiplexer output unit (23). In each of the D delay devices (12a to 12d), on the one hand, one delay input unit (18a to 18d) and one of the D demultiplexer output units (17a to 17d) are provided in the supply signal path (17a to 17d). 24a to 24d) are connected to each other, and on the other hand, one delay output unit (19a to 19d) and one of 2 × D multiplexer input units (22a to 22h) are connected to each other via a delay signal path (22a to 22h). They are connected to each other via 25a to 25d). In each of the D additional delay devices (13a to 13d), one additional delay input unit (20a to 20d) and one of the delay signal paths (25a to 25d) are connected to each other, and the other. One additional delay output unit (21a to 21d) and one of 2 × D multiplexer input units (22a to 22h) are connected to each other via an additional delay signal path (26a to 26d). In the demultiplexer (11), input data word streams having a data word and having an external transmission rate of S at the demultiplexer input unit (16) are interleaved with each other, each having an internal transmission rate of P = S / D. It is divided into D parallel data word streams, and these are configured to be output to D demultiplexer output units (17a to 17d). The transfer delay coefficient m can be set in advance for each of the D delay devices (12a to 12d), and each of the D delay devices (12a to 12d) is in the delay input unit (18a to 18d). Each data word in the parallel data word stream is delayed by the transfer delay time Δtm = m / P, and the delayed data word is output to the delay output unit (19a to 19d). Each of the D additional delay devices (13a to 13d) delays each data word in the delayed parallel data word stream in the additional delay input unit (20a to 20d) by the additional delay time Δts = 1 / P. It is configured to output the additionally delayed data word to the additional delay output unit (21a to 21d). The output delay coefficient n can be set in advance in the control device (15). The control device (15) determines a transfer delay coefficient m from a preset output delay coefficient n, sets this in advance for D delay devices (12a to 12d), and drives and controls the multiplexer (14). As a result, the output data word stream corresponding to the input data word stream having a time delay of Δt = n / S is configured to be output to the multiplexer output unit (23).

Description

The present invention relates, on the one hand, to a signal delay device that simulates a spatial distance in an electromagnetic wave-based distance measuring device, and, on the other hand, to a simulator device for that purpose.

The distance measuring device is said to be electromagnetically based because the distance measuring device emits a measurement signal in the form of an electromagnetic wave in order to identify the spatial object distance between the distance measuring device and the target body. , The reflection of the emitted measurement signal on the object is received as an echo signal, and the object distance is specified from the characteristics of the emitted measurement signal and the received echo signal. One such characteristic is, for example, the total travel time of the signal, thus the travel time of the measurement signal from the distance measuring device to the object and the travel time of the echo signal from the object to the distance measurement device. Is the total of. The object distance is specified by the evaluation device in the distance measuring device. In many cases, the distance measuring device is not only configured to specify the object distance between the distance measuring device and the object, but also, for example, the size of the object and the distance measuring device and the object. The relative speed between and is also configured to be specified from such signals. Relative velocity identification is usually done by assessing the Doppler effect on signals such as these.

The electromagnetic wave-based distance measuring device is, for example, a radar distance measuring device and a rider distance measuring device. The radar distance measuring device is electromagnetic wave based in the high frequency region, and the lidar distance measuring device is electromagnetic wave based in the laser frequency.

Distance measuring devices are often used in automobiles. The object is the surrounding environment, and especially other road users in the surrounding environment. The general frequency range of electromagnetic waves of a radar distance measuring device in an automobile is near a frequency of 77 GHz.

Distance measuring equipment and especially its evaluation equipment will of course be tested during development. The goal of this test is to ensure that the object distance identified by the distance measuring device is the same as the actual object distance. This test can be performed in a realistic or simulated environment. Testing in a realistic environment must, of course, be done with a real object. This test is time consuming, costly, and the reproducibility of the measurement is often compromised by interference from the surrounding environment. Testing in the simulated environment must be done in the simulator and, of course, the object must also be simulated. Simulated ambient testing saves time, is more advantageous, and is better reproducible than real ambient testing.

The simulator also requires a simulator device that simulates the spatial distance. The simulator device includes a receiver, an analog-to-digital converter, a signal delay device, a digital-to-analog converter, and a transmitter. The receiver is configured to receive a measurement signal in the form of a first electromagnetic wave radiated by a distance measuring device, down-convert it, and supply it to an analog-to-digital converter. The analog-to-digital converter is configured to convert the down-converted measurement signal into a data word stream and supply it to the signal delay device. The signal delay device is configured to delay the data word stream and supply the delayed data word stream to the digital-to-analog converter. By configuring the signal delay device to delay the data word stream, the signal delay device is configured to simulate a spatial distance. The digital-to-analog converter is configured to convert the delayed data word stream into an echo signal and supply it to the transmitter. The transmitter is configured to up-convert the echo signal, radiate it in the form of a second electromagnetic wave, and return it to the distance measuring device. Down-conversions and up-conversions are usually complementary to each other. Down-conversion is usually done by a down-converter, and up-conversion is done by an up-converter.

Therefore, the simulator device generates an echo signal having a delay from the measurement signal radiated and received by the distance measuring device, and radiates this echo signal to return it to the distance measuring device. The echo signal is received by the distance measuring device, and when the measured signal and the echo signal are evaluated by the evaluation device of the distance measuring device, the delay added by the signal delay device of the simulator device increases the total travel time. Be done. A simulator having such a simulator device is called an OTA device, and the OTA represents and clearly indicates that the distance measuring device is supplied with a realistic electromagnetic wave as an echo signal. For example, the evaluation device of the distance measuring device is not supplied with the simulated echo signal.

The delay Δt, which is always generated by the signal delay device and means a time delay, is visible to the distance measuring device as a traveling time, and therefore, by setting the delay, the distance measuring device and the object simulated. And, the distance Δd between and can be set. Since the total travel time is not given only by the delay Δt, the distance Δd due to the delay Δt is generally different from the object distance. Since the electromagnetic wave propagates at the speed of light c≈3 × ¹⁰⁸ m / s, the distance is half the product of the speed of light and the delay, and therefore Δd = 0.5 × c × Δt. The simulator device and especially the delay device are real-time devices, and various requirements are made from the propagation speed of the electromagnetic wave.

When testing a distance measuring device in a simulator, the distance should be arbitrarily preset by delay. For this, the signal delay device must be able to generate any delay. From the prior art, a digital signal delay device having a digital delay line is known. The present invention relates only to digital signal delay devices and not to analog signal delay devices. Digital delay lines are implemented, for example, by different types of ICs. One type of IC is, for example, an FPGA. According to FPGA, not only a digital delay line but also another element of a signal delay device can be realized, and a simulator device can also be realized in many cases, so FPGA is particularly suitable. In addition, FPGAs are cheaper and reconfigurable than other types of ICs. However, the drawback of FPGAs is that they have a lower operating cycle _fA than other types of ICs. For example, if a delay line is implemented in the FPGA that delays the data word stream by one operating cycle of the FPGA, and the FPGA has an operating cycle of f _A = 625 MHz, the distance resolution is Δd = 0.5 × c ×. (1 / f _A ) = 24 cm. This means that the minimum distance generated by the signal delay device between the distance measuring device and the simulated object is 24 cm and can only be a multiple of 24 cm. This distance is an additional distance.

An object of the present invention is to provide a signal delay device having at least the drawbacks shown in the prior art and a simulator device having such a signal delay device, and for this purpose, it is particularly necessary to improve the distance resolution. Is.

This problem is solved by the signal delay device according to claim 1 in the first option.

This signal delay device according to the present invention, which simulates a spatial distance in an electromagnetic wave-based distance measuring device, includes one demultiplexer, D delay devices, D additional delay devices, and one multiplexer. It has one control device. Therefore, D is an integer of 1 or more.

The demultiplexer has one demultiplexer input unit and D demultiplexer output units. Each of the D delay devices has one delay input unit and one delay output unit. Each of the D additional delay devices has one additional delay input unit and one additional delay output unit. The multiplexer has 2 × D multiplexer inputs and one multiplexer output. Therefore, the number of multiplexer input units is twice the number of multiplexer output units.

In each of the D delay devices, on the one hand, one delay input unit and one of the D demultiplexer output units are connected to each other via a supply signal path, and on the other hand, one delay output unit. And one of the 2 × D multiplexer inputs are connected to each other via a delay signal path. In each of the D additional delay devices, on the one hand, one additional delay input unit and one of the delay signal paths are connected, and on the other hand, one additional delay output unit and 2 × D multiplexer input units are connected. Are connected to each other via an additional delay signal path. The individual supply signal paths are separate from each other and therefore not connected to each other. The same applies to individual delay signal paths as well as additional delay signal paths.

The demultiplexer is an interleaved D parallel data in which input data word streams having data words and having an external transmission rate of S at the demultiplexer input section each have an internal transmission rate of P = S / D. It is divided into word streams, and these are configured to be output to D demultiplexer outputs. Both the data word stream and the input data word stream have data words that are sequentially continuous with each other, or each parallel data word stream has data words that are serially continuous with each other. Therefore, the temporal order of the data words is sequential. Data words generally have one or more bits as an information carrier. For example, one data word has 10 bits. Thus, the transmission of a plurality of data words is carried out sequentially in time, whereas the transmission of a plurality of bits of one data word is usually carried out simultaneously and therefore in parallel. Signal paths such as supply signal paths, delay signal paths, and additional delay signal paths are configured to carry data words correspondingly.

The transfer delay coefficient m can be preset for each of the D delay devices, and each of the D delay devices transfers each data word in each parallel data word stream in the delay input unit to the transfer delay time. It is configured to delay by Δt _m = m / P and output the delayed data word to the delay output unit. Therefore, the delay device delays all the data words in the data word stream that joins the delay input section, so that the delay output section of the delay device has a transfer delay time Δt as compared with the data word stream in the delay input section. A data word stream that is delayed by _m but is otherwise identical is added. The transfer delay time is the same for all D delay devices, where m is an integer greater than or equal to 0.

Each of the D additional delay devices is additionally delayed by delaying each data word in the delayed parallel data word stream in the additional delay input unit by the additional delay time of Δt _z = 1 / P. It is configured to output the data word to the additional delay output unit. Therefore, the additional delay device delays all the data words in the data word stream that joins the additional delay input section, whereby the additional delay output section of the additional delay device has a higher delay output section than the data word stream in the additional delay input section. , A data word stream that is delayed by the additional delay time _Δts , but otherwise identical to this, is added.

The output delay coefficient n can be set in advance in the control device. The control device is further configured to determine a transfer delay coefficient m from a preset output delay coefficient n and preset it to D delay devices. The control device is further configured to drive and control the multiplexer, whereby the output data word stream corresponding to the input data word stream with a time delay of Δt _D = n / S is output to the multiplexer output section. There is. Here, n is an integer of 0 or more. Therefore, the control device is configured to drive and control the multiplexer so that the output data word stream is assembled from the data word stream in the data word stream added to and delayed by the 2 × D multiplexer inputs.

It is said that the signal delay device according to the present invention can increase the distance resolution by D times as compared with the signal delay device known from the prior art while maintaining the operation cycle _fA of the IC in which the delay device and the additional delay device are realized. Has advantages. Only the demultiplexer and multiplexer need be configured for external transmission speeds. Preferably, at least one delay device and / or at least one additional delay device is implemented in the FPGA. Since the FPGA is cost-effective and reconfigurable as compared with other ICs, a signal delay device is realized in the FPGA particularly advantageously. This realization preferably also includes a demultiplexer and a multiplexer.

The external transmission speeds of the number D = 2 and S = 1GS / s are as follows. That is, the signal delay device has two delay devices and two additional delay devices. The demultiplexer has two demultiplexer outputs and the multiplexer has four multiplexer inputs. An external transmission rate of S = 1 GS / s means that a data word stream with 1 billion data words per second is transmitted. The internal transmission speed is P = S / D = (1GS / s) / 2 = 500MS / s. A total of two parallel data word streams are obtained. The internal transmission rate is realized, for example, by an FPGA having an operation cycle of _fA = 500 MHz, whereby an internal transmission rate of P = 500 GS / s is realized.

In one embodiment of the first option of the signal delay device according to the present invention, the control device is configured so that the transfer delay coefficient is determined according to m = n / D. Therefore, m is the largest integer less than or equal to n / D.

In another embodiment of the signal delay device, at least one of the D additional delay devices is configured to have an operation cycle of f _P = S / D. Preferably, the operation cycle f _P corresponds to the operation cycle f _A of the IC.

In another embodiment of the first option, at least one additional delay device is configured to be a delay line.

In another embodiment of the first option, the at least one additional delay device is configured to be a flip-flop, preferably a D flip-flop.

The above problem is solved by the signal delay device according to claim 7 in the second option.

The signal delay device according to the present invention, which simulates a spatial distance in an electromagnetic wave-based distance measuring device, has one demultiplexer, D delay devices, one multiplexer, and one control device. ..

The demultiplexer has one demultiplexer input and D demultiplexer outputs. Each of the D delay devices has one delay input unit and one delay output unit. The multiplexer has D multiplexer inputs and one multiplexer output. Therefore, the number of multiplexer input units is the same as the number of demultiplexer output units.

In each of the D delay devices, on the one hand, one delay input unit and one of the D demultiplexer output units are connected to each other via a supply signal path, and on the other hand, one delay output unit. And one of the D multiplexer inputs are connected to each other via a delay signal path. The individual supply signal paths are separate from each other and therefore not connected to each other. The same applies to individual delay signal paths.

The demultiplexer is an interleaved D parallel data in which input data word streams having data words and having an external transmission rate of S at the demultiplexer input section each have an internal transmission rate of P = S / D. It is divided into word streams, and these are configured to be output to D demultiplexer outputs.

Each of the D delay devices can be preset with a separate transfer delay coefficient m _d , but d ≤ D, and each of the D delay devices is within its own parallel data word stream at the delay input section. Each data word is delayed by a separate transfer delay time Δt _{m, d} = m _d / P, and the delayed data word is output to the delay output unit. Therefore, the transfer delay time may be different among the D delay devices.

The output delay coefficient n can be set in advance in the control device. The control device is further configured to determine separate transfer delay coefficients md from the preset output delay coefficients _n and preset these to D configurable delay devices. The control device is further configured to drive and control the multiplexer, whereby the output data word stream corresponding to the input data word stream with a time delay of Δt _D = n / S is output to the multiplexer output section. There is. Therefore, the control device is configured to drive and control the multiplexer so that the output data word stream is assembled from the data words in the data word stream added to and delayed by the D multiplexer inputs.

This signal delay device according to the present invention also has an advantage that the distance resolution can be increased by D times as compared with the signal delay device known from the prior art while maintaining the operation cycle _fA of the IC in which the delay device is realized. .. Only the demultiplexer and multiplexer need be configured for external transmission speeds. Preferably, at least one delay device is implemented in the FPGA. Since the FPGA is cost-effective and reconfigurable as compared with other ICs, a signal delay device is realized in the FPGA particularly advantageously. This realization preferably also includes a demultiplexer and a multiplexer.

Unlike the first option, the second option does not have an additional delay device, instead the delay device can be preset with different transfer delay coefficients. The advantages of the second option over the first option are the absence of additional delay devices and the halving of the multiplexer input. Disadvantages of the second option over the first option belong to the configuration of the delay device and the control device, which must be able to set different transfer delay coefficients for each of the delay devices. In other respects, the description of the first option applies to the second option and vice versa.

However, the two alternative signal delay devices are based on the same idea. Moreover, while maintaining the operation cycle _fA of the IC in which the delay device and, in some cases, the additional delay device are also realized, the distance resolution is increased by D times as compared with the signal delay device known from the prior art. Only the demultiplexer and multiplexer need be configured for external transmission speeds.

In one embodiment of the second option of the signal delay device according to the invention, the control device is configured such that the separate transfer delay coefficients are specified according to m _d = (n + d-1) / D, where d ≦ D. To do.

In one embodiment of the plurality of signal delay devices according to the present invention, the external transmission speed is configured to be S ≧ 2GS / s, preferably S ≧ 2.5GS / s. In another embodiment, D = 2, preferably D = 8, and particularly preferably D = 4. When the external transmission speed S ≧ 2.5 GS / s and D = 4, the internal transmission speed is P = S / D = (2.5 GS / s) / 4 = 625 MS / s. This internal transmission speed can be realized by an IC operating in an operation cycle of 625 MHz. For example, FPGAs with such operation cycles are available.

In another embodiment, the demultiplexer and / or the multiplexer is configured to have an operating cycle fS corresponding to an external transmission rate _S. When the external transmission rate is S = 2.5 GS / s, the operation cycle of the demultiplexer and / or the multiplexer is f _S = 2.5 GHz.

In another embodiment, at least one of the D delay devices is configured to have an operation cycle of f _P = S / D. Preferably, the operation cycle f _P corresponds to the operation cycle f _A of the IC.

In another embodiment, at least one delay device is configured to be a delay line.

In another embodiment, the signal delay device is configured to simulate a distance in a radar or rider-based distance measuring device.

The above-mentioned problems are further solved by the simulator device according to claim 16.

In this simulator device, the signal delay device of the simulator device is configured as described above.

In the first embodiment of the simulator device according to the invention, the simulator device is configured to have only one antenna for transmission and for reception.

In another embodiment of the simulator device, the simulator device is configured to simulate a distance in a radar or rider-based distance measuring device.

In detail, there are many possibilities for configuring and developing signal delay devices and simulator devices. For this, also refer to the following description related to the drawings of the preferred embodiment of the simulator device having the signal delay device, as well as the claims following claims 1, 7 and 16.

It is a figure which shows the Example of the simulator apparatus. It is a figure which shows the 1st Embodiment of a signal delay apparatus. a to j are diagrams showing the data word stream in the first embodiment for n = 4. a to j are diagrams showing the data word stream in the first embodiment for n = 5. It is a figure which shows the 2nd Embodiment of a signal delay apparatus. a to f are diagrams showing the data word stream in the second embodiment for n = 4. a to f are diagrams showing the data word stream in the second embodiment for n = 5.

FIG. 1 shows an embodiment of the simulator device 1 as a block diagram. The simulator device 1 includes a receiver 2, an analog-to-digital converter 3, a signal delay device 4, a digital-to-analog converter 5, a transmitter 6, and an antenna 7. The simulator device 1 is a part of a simulator (not shown) that tests the distance measuring device 8.

The distance measuring device 8 is a radar distance measuring device that operates with a signal in a frequency domain near a frequency of 77 GHz. The distance measuring device 8 specifies the distance between the distance measuring device 8 and the object from the total traveling time of the signal outside the simulator during operation. The total traveling time of the signal is particularly composed of the traveling time of the measurement signal from the distance measuring device 8 to the object and the traveling time of the echo signal reflected by the object and returned to the distance measuring device 8.

The simulator device 1 has a receiver 2 that receives a measurement signal in the form of a first electromagnetic wave 9 radiated by a distance measuring device 8 via an antenna 7, down-converts it, and supplies it to an analog-to-digital converter 3. It is configured. The analog-to-digital converter 3 is configured to convert the down-converted measurement signal into a data word stream and supply it to the signal delay device 4. The signal delay device 4 is configured to delay the data word stream by Δt and supply the delayed data word stream to the digital-to-analog converter 5. By configuring the signal delay device 4 to delay the data word stream, the signal delay device 4 is configured to simulate a spatial distance. Therefore, the same applies to the simulator device 1. The digital-to-analog converter 5 is configured to convert a delayed data word stream into an echo signal and supply it to the transmitter 6. The transmitter 6 is configured to up-convert the echo signal, radiate it in the form of the second electromagnetic wave 10, and return it to the distance measuring device 8.

Therefore, the simulator device 1 generates an echo signal having a delay Δt from the received measurement signal, which is radiated back to the distance measuring device 8. The echo signal is received by the distance measuring device 8, and when evaluating the measured signal and the echo signal, the distance measuring device 8 increases the total traveling time by the delay Δt added by the signal delay device 4. The delay Δt generated by the signal delay device 4 looks like a travel time to the distance measuring device 8, and therefore, by setting the delay Δt, between the distance measuring device 8 and the simulated object. Distance Δd can be set. By integrating the distance information into the electromagnetic wave 10, the simulator becomes an OTA device.

The signal delay device 4 can be realized in various different ways. FIG. 2 shows a first embodiment of the signal delay device 4, and FIG. 5 shows a second embodiment.

The first embodiment of the signal delay device 4 shown in FIG. 2 includes one demultiplexer 11, four delay devices 12a to 12d, four additional delay devices 13a to 13d, and one multiplexer 14. It has one control device 15. Therefore, in this embodiment, D = 4. The four delay devices 12a to 12d, the four additional delay devices 13a to 13d, and the control device 15 are realized in one FPGA.

The demultiplexer 11 has one demultiplexer input unit 16 and four demultiplexer output units 17a to 17d. Each of the four delay devices 12a to 12d has one delay input unit 18a to 18d and one delay output unit 19a to 19d. Each of the four additional delay devices 13a to 13d has one additional delay input unit 20a to 20d and one additional delay output unit 21a to 21d. The multiplexer 14 has eight multiplexer input units 22a to 22h and one multiplexer output unit 23. Therefore, the number of multiplexer input units 22a to 22h is twice the number of demultiplexer output units 17a to 17d.

In each of the four delay devices 12a to 12d, one delay input unit 18a to 18d and one of the four demultiplexer output units 17a to 17d are connected to each other via supply signal paths 24a to 24d. On the other hand, one delay output unit 19a to 19d and one of the eight multiplexer input units 22a to 22h are connected to each other via a delay signal path 25a to 25d. In each of the four additional delay devices 13a to 13d, on the one hand, the additional delay input units 20a to 20d and one of the delay signal paths 25a to 25d are connected, and on the other hand, one additional delay output unit 21a to 21a to The 21d and one of the eight multiplexer input units 22a to 22h are connected to each other via an additional delay signal path 26a to 26d. The individual supply signal paths 24a-24d are separate from each other and therefore not connected to each other. The same applies to the individual delay signal paths 25a to 25d as well as the additional delay signal paths 26a to 26d.

The demultiplexer 11 has an input data word stream (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a 0, a 1, a 2, a 3, a 4, which has a data word and has an external transmission rate of S = 2.5 GS / s in the demultiplexer input unit 16. a ₅ , a ₆ , a ₇ , a ₈ , a ₉ , a ₁₀ , a ₁₁ , ...) Each have an internal transmission rate of P = S / D = (2.5GS / s) / 4 = 625MS / s. It has four parallel data word streams interleaved with each other (a ₀ , a ₄ , a ₈ , ...), (a ₁ , a ₅ , a ₉ , ...), and (a ₂ , a ₆ , a ₁₀ ). , ...) and (a ₃ , a ₇ , a ₁₁ , ...), Which are configured to be output to the four demultiplexer output units 17a to 17d. In the data word stream, each data word has 10 bits.

A transfer delay coefficient m can be preset for each of the four delay devices 12a to 12d, and each of the four delay devices 12a to 12d is within the respective parallel data word stream in the delay input units 18a to 18d. Each data word is delayed by the transfer delay time Δt _m = m / P = m / (625MS / s) = m × 1.6ns, and the delayed data word is output to the delay output units 19a to 19d. It is configured in. The transfer delay time is the same for all four delay devices 12a-12d.

Each of the four additional delay devices 13a to 13d adds each data word in the delayed parallel data word stream in the additional delay input units 20a to 20d to the additional delay time Δt _z = 1 / P = 1 / (625MS). / S) = 1.6 ns is delayed, and the additionally delayed data word is output to the additional delay output units 21a to 21d.

The output delay coefficient n can be set in advance in the control device 15. The control device is configured to determine a transfer delay coefficient m from a preset output delay coefficient n and preset it to the four delay devices 12a to 12d. The control device further drives and controls the multiplexer 14, thereby outputting data corresponding to an input data word stream with a time delay of Δt = n / S = n / (2.5GS / s) = n × 0.4ns. The word stream is configured to be output to the multiplexer output unit 23. For this purpose, the control device 15 is configured to determine the transfer delay coefficient according to m = n / 4. Therefore, for m, the following can be obtained depending on n.

3a-3j and 4a-4j show a data word stream at a specific location in the signal delay device 4 according to the first embodiment, and drive control of the multiplexer 14 by the control device 15 is described. Therefore, a data word stream delayed by Δt with respect to the data word stream in the demultiplexer input unit 16 is added to the multiplexer output unit 23.

3a-3j show the data word stream over time for n = 4. According to this, m = 1, Δt _m = m / P = 1 / (625MS / s) = 1.6ns and Δt = n / S = 4 × 0.4ns = 1.6ns. The time axes of FIGS. 3a to 3j are synchronized with each other.

3a shows the data word stream in the demultiplexer input unit 16, FIG. 3b shows the data word stream in the multiplexer input unit 22a, FIG. 3c shows the data word stream in the multiplexer input unit 22b, and FIG. 3d shows the data word stream in the multiplexer input unit 22b. 3e shows the data word stream in the multiplexer input unit 22c, FIG. 3e shows the data word stream in the multiplexer input unit 22d, FIG. 3f shows the data word stream in the multiplexer input unit 22e, and FIG. 3g shows the data word stream in the multiplexer input unit 22f. 3h shows the data word stream in the multiplexer input unit 22g, FIG. 3i shows the data word stream in the multiplexer input unit 22h, and FIG. 3j shows the data word stream in the multiplexer output unit 23. It is shown.

In the demultiplexer input unit 16 and the multiplexer output unit 23, the data word stream has an external transmission speed S = 2.5GS / s, whereas the demultiplexer output units 17a to 17d and the multiplexer input units 22a to 22h. Between, the data word stream has an internal transmission rate P = 625 MS / s.

Vertical arrows extending from the data word stream of FIGS. 3b to 3i to the data word stream of FIG. 3j symbolically indicate the drive control of the multiplexer 14 by the control device 15.

4a-4j show a data word stream for n = 5. According to this, Δt = n / S = 5 × 0.4ns = 2.0ns, and further m = 1. The data word stream of FIGS. 4a-4i is the same as that of FIGS. 3a-3i. Only the data word stream shown in FIG. 4j is further delayed by 0.4 ns with respect to the data word stream shown in FIG. 3j. Here, the necessity of additional delay devices 13a to 13d is also shown. The data words _a3 and _a7 are thereby supplied at the correct time. This is because the delay devices 12a-12d have already prepared the _next data words a7 and _a11 .

A second embodiment of the signal delay device 4 shown in FIG. 5 has one demultiplexer 11, four delay devices 12a-12d, one multiplexer 14, and one control device 15. Therefore, in this embodiment, D = 4. The four delay devices 12a to 12d and the control device 15 are realized in one FPGA.

The demultiplexer 11 has one demultiplexer input unit 16 and four demultiplexer output units 17a to 17d. Each of the four delay devices 12a to 12d has one delay input unit 18a to 18d and one delay output unit 19a to 19d. The multiplexer 14 has four multiplexer input units 22a to 22d and one multiplexer output unit 23. Therefore, the number of multiplexer input units 22a to 22d is the same as the number of demultiplexer output units 17a to 17d.

In each of the four delay devices 12a to 12d, one delay input unit 18a to 18d and one of the four demultiplexer output units 17a to 17d are connected to each other via supply signal paths 24a to 24d. On the other hand, one delay output unit 19a to 19d and one of the four multiplexer input units 22a to 22d are connected to each other via a delay signal path 25a to 25d. The individual supply signal paths 24a-24d are separate from each other and therefore not connected to each other. The same applies to the individual delay signal paths 25a-25d.

The demultiplexer 11 has an input data word stream (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a 0, a 1, a 2, a 3, a 4, which has a data word and has an external transmission rate of S = 2.5 GS / s in the demultiplexer input unit 16. a ₅ , a ₆ , a ₇ , a ₈ , a ₉ , a ₁₀ , a ₁₁ , ...) Each have an internal transmission rate of P = S / D = (2.5GS / s) / 4 = 625MS / s. It has four parallel data word streams interleaved with each other (a ₀ , a ₄ , a ₈ , ...), (a ₁ , a ₅ , a ₉ , ...), and (a ₂ , a ₆ , a ₁₀ ). , ...) and (a ₃ , a ₇ , a ₁₁ , ...), Which are configured to be output to the four demultiplexer output units 17a to 17d. In the data word stream, each data word has 10 bits.

A separate transfer delay coefficient md, where _d ≦ 4, can be set in advance for each of the four delay devices 12a to 12d, and each of the four delay devices 12a to 12d has a delay input unit 18a to 18a to 12d. Each data word in each parallel data word stream at 18d is delayed by a separate transfer delay time Δtm _{, d} = m _d / P = m _d / (625MS / s) to delay the delayed data word. It is configured to output to the output units 19a to 19d. Therefore, the transfer delay time may be different among the four delay devices 12a to 12d.

The output delay coefficient n can be set in advance in the control device 15. The control device is configured to determine separate transfer delay coefficients md from the preset output delay coefficients _n and preset these to the four configurable delay devices 12a-12d. The control device further drives and controls the multiplexer 14, thereby outputting data corresponding to an input data word stream with a time delay of Δt = n / S = n / (2.5GS / s) = n × 0.4ns. The word stream is configured to be output to the multiplexer output unit 23. For this purpose, the control device is configured to determine the transfer delay factor according to m _d = (n + d-1) / 4, but d ≦ 4.
Therefore, for md, the following can be obtained depending on _n .

6a-6f and 7a-7f show a data word stream at a specific location in the signal delay device 4 according to the second embodiment, and drive control of the multiplexer 14 by the control device 15 is described. Therefore, a data word stream delayed by Δt with respect to the data word stream in the demultiplexer input unit 16 is added to the multiplexer output unit 23.

6a-6f show the data word stream over time for n = 4. According to this, m ₁ = m ₂ = m ₃ = m ₄ = 1, Δt _{m, 1} = Δt _{m, 2} = Δtm _{, 3} = Δt _{m, 4} = 1.6ns and Δt = n / S = 4 × 0.4ns = 1.6ns. The time axes of FIGS. 6a to 6f are synchronized with each other.

6a shows the data word stream in the demultiplexer input unit 16, FIG. 6b shows the data word stream in the multiplexer input unit 22a, FIG. 6c shows the data word stream in the multiplexer input unit 22b, and FIG. 6d shows the data word stream in the multiplexer input unit 22b. The data word stream in the multiplexer input unit 22c is shown, FIG. 6e shows the data word stream in the multiplexer input unit 22d, and FIG. 6f shows the data word stream in the multiplexer output unit 23.

In the demultiplexer input unit 16 and the multiplexer output unit 23, the data word stream has an external transmission speed S = 2.5 GS / s, whereas the demultiplexer output units 17a to 17d and the multiplexer input units 22a to 22d. Between, the data word stream has an internal transmission rate P = 625 MS / s.

The vertical arrows extending from the data word stream of FIGS. 6b to 6e to the data word stream of FIG. 6f symbolically indicate the drive control of the multiplexer 14 by the control device 15.

7a-7f show a data word stream for n = 5. According to this, m ₁ = m ₂ = m ₃ = 1, m ₄ = 2, Δt _{m, 1} = Δt _{m, 2} = Δtm, ₃ = 1.6ns, Δt _{m, 4} = 3.2ns and Δt = n / S = 5 × 0.4ns = 2.0ns. The data word stream in FIGS. 7a to 7d is the same as that in FIGS. 6a to 6d. The data word stream shown in FIG. 6e is further delayed by 1.6 ns so that the data words _a3 and _a7 are supplied at the correct time points. The data word stream shown in FIG. 7f is further delayed by 0.4 ns with respect to the data word stream shown in FIG. 6f.

1 Simulator device 2 Receiver 3 Analog / digital converter 4 Signal delay device 5 Digital / analog converter 6 Transmitter 7 Antenna 8 Distance measuring device 9 First electromagnetic wave 10 Second electromagnetic wave 11 Demultiplexer 12a-12d Delay device 13a-13d Additional delay device 14 Multiplexer 15 Control device 16 Demultiplexer input section 17a to 17d Demultiplexer output section 18a to 18d Delay input section 19a to 19d Delay output section 20a to 20d Additional delay input section 21a to 21d Additional delay output section 22a to 22h multiplexer Input section 23 Multiplexer output section 24a to 24d Supply signal path 25a to 25d Delay signal path 26a to 26d Additional delay signal path

Claims (18)

In the signal delay device (4) that simulates the spatial distance in the electromagnetic wave-based distance measuring device (8),
The signal delay device (4) includes one demultiplexer (11), D delay devices (12a to 12d), D additional delay devices (13a to 13d), and one multiplexer (14). And one control device (15).
The demultiplexer (11) has one demultiplexer input unit (16) and D demultiplexer output units (17a to 17d).
Each of the D delay devices (12a to 12d) has one delay input unit (18a to 18d) and one delay output unit (19a to 19d).
Each of the D additional delay devices (13a to 13d) has one additional delay input unit (20a to 20d) and one additional delay output unit (21a to 21d).
The multiplexer (14) has 2 × D multiplexer input units (22a to 22h) and one multiplexer output unit (23).
In each of the D delay devices (12a to 12d), one of the delay input units (18a to 18d) and one of the D demultiplexer output units (17a to 17d) is supplied. They are connected to each other via signal paths (24a to 24d), and on the other hand, one of the delayed output units (19a to 19d) and one of the 2 × D multiplexer input units (22a to 22h). They are connected to each other via a delay signal path (25a to 25d) and are connected to each other.
In each of the D additional delay devices (13a to 13d), one of the additional delay input units (20a to 20d) and one of the delay signal paths (25a to 25d) are connected to each other. On the other hand, one additional delay output unit (21a to 21d) and one of the 2 × D multiplexer input units (22a to 22h) are connected to each other via an additional delay signal path (26a to 26d). Has been
In the demultiplexer (11), an input data word stream having a data word and having an external transmission rate of S in the demultiplexer input unit (16) has an internal transmission rate of P = S / D, respectively. It is divided into D parallel data word streams interleaved with each other, and the D parallel data word streams are configured to be output to the D multiplexer output units (17a to 17d).
A transfer delay coefficient m can be set in advance for each of the D delay devices (12a to 12d), and each of the D delay devices (12a to 12d) has a delay input unit (18a to 18a). Each data word in each of the parallel data word streams in 18d) is delayed by the transfer delay time Δtm = _m / P, and the delayed data word is output to the delay output unit (19a to 19d). Is configured to
Each of the D additional delay devices (13a to 13d) sets each data word in the delayed parallel data word stream in the additional delay input unit (20a to 20d) to Δt _z = 1 / P. It is configured to delay the additional delay time and output the additionally delayed data word to the additional delay output unit (21a to 21d).
An output delay coefficient n can be preset in the control device (15), and the control device (15) determines the transfer delay coefficient m from the preset output delay coefficient n and determines the transfer delay coefficient m. The coefficients m are preset in the D delay devices (12a-12d) and the multiplexer (14) is driven and controlled, whereby the output corresponding to the input data word stream having a time delay of Δt = n / S. The data word stream is configured to be output to the multiplexer output unit (23).
Signal delay device (4). The signal delay device (4) according to claim 1, wherein the at least one delay device (12a to 12d) and / or at least one additional delay device (13a to 13d) are realized in the FPGA. ). The control device (15) is characterized in that the transfer delay coefficient is configured to be determined by m = n / D.
The signal delay device (4) according to claim 1 or 2. At least one of the D additional delay devices (13a-13d) is characterized by having an operation cycle of f _P = S / D.
The signal delay device (4) according to any one of claims 1 to 3. At least one additional delay device (13a to 13d) is characterized by being a delay line.
The signal delay device (4) according to any one of claims 1 to 4. The at least one additional delay device (13a to 13d) is characterized by being a flip-flop, preferably a D-flip-flop.
The signal delay device (4) according to any one of claims 1 to 5. In the signal delay device (4) that simulates the spatial distance in the electromagnetic wave-based distance measuring device (8),
The signal delay device (4) includes one demultiplexer (11), D delay devices (12a to 12d), one multiplexer (14), and one control device (15). death,
The demultiplexer (11) has one demultiplexer input unit (16) and D demultiplexer output units (17a to 17d).
Each of the D delay devices (12a to 12d) has one delay input unit (18a to 18d) and one delay output unit (19a to 19d).
The multiplexer (14) has D multiplexer input units (22a to 22d) and one multiplexer output unit (23).
In each of the D delay devices (12a to 12d), one of the delay input units (18a to 18d) and one of the D demultiplexer output units (17a to 17d) is supplied. They are connected to each other via a signal path (24a to 24d), and on the other hand, one of the delay output units (19a to 19d) and one of the D multiplexer input units (22a to 22d) are delayed signals. They are connected to each other via roads (25a to 25d) and are connected to each other.
In the demultiplexer (11), an input data word stream having a data word and having an external transmission rate of S in the demultiplexer input unit (16) has an internal transmission rate of P = S / D, respectively. It is divided into D parallel data word streams interleaved with each other, and the D parallel data word streams are configured to be output to the D multiplexer output units (17a to 17d).
A separate transfer delay coefficient md, where _d ≦ D, can be preset for each of the D delay devices (12a to 12d), and each of the D delay devices (12a to 12d) can be set in advance. , Each data word in each parallel data word stream in the delay input unit (18a to 18d) is delayed by a separate transfer delay time Δtm _{, d} = m _d / P, and the delayed data word is delayed. It is configured to output to the delay output unit (19a to 19d).
An output delay coefficient n can be preset in the control device (15), and the control device (15) determines a transfer delay coefficient md from the preset output delay coefficient _n , and the transfer delay coefficient md is determined. The transfer delay coefficient m _d is preset in the D delay devices (12a to 12d) that can be set, and the multiplexer (14) is driven and controlled, whereby the input data having a time delay of Δt = n / S is obtained. The output data word stream corresponding to the word stream is configured to be output to the multiplexer output unit (23).
Signal delay device (4). At least one of the delay devices (12a-12d) is characterized in that it is implemented in an FPGA.
The signal delay device (4) according to claim 7. The control device (15) is characterized in that the separate transfer delay coefficients are configured to be determined by md = (n + _d -1) / D with respect to d ≦ D.
The signal delay device (4) according to claim 7. The external transmission speed is characterized by S ≧ 2GS / s, preferably S ≧ 2.5GS / s.
The signal delay device (4) according to any one of claims 1 to 9. It is characterized in that D = 2, preferably D = 8, and particularly preferably D = 4.
The signal delay device (4) according to any one of claims 1 to 10. The demultiplexer (11) and / or the multiplexer (14) is characterized by having an operation cycle fS corresponding to the external transmission speed _S.
The signal delay device (4) according to any one of claims 1 to 11. At least one of the D delay devices (12a-12d) is characterized by having an operation cycle of f _P = S / D.
The signal delay device (4) according to any one of claims 1 to 12. The delay device (12a-12d) is characterized in that it is a delay line.
The signal delay device (4) according to any one of claims 1 to 13. The signal delay device (4) is characterized in that it is configured to simulate a distance in a radar or rider-based distance measuring device (8).
The signal delay device (4) according to any one of claims 1 to 14. A simulator device (1) that simulates a spatial distance in an electromagnetic wave-based distance measuring device (8).
The simulator device (1) includes a receiver (2), an analog-to-digital converter (3), a signal delay device (4), a digital-to-analog converter (5), and a transmitter (6). Have,
The receiver (2) receives the measurement signal in the form of the first electromagnetic wave (9) radiated by the distance measuring device (8), down-converts it, and transfers it to the analog-to-digital converter (3). It is configured to supply and
The analog-to-digital converter (3) is configured to convert the down-converted measurement signal into a data word stream and supply it to the signal delay device (4).
The signal delay device (4) is configured to delay the data word stream and supply the delayed data word stream to the digital-to-analog converter (5).
The digital-to-analog converter (5) is configured to convert the delayed data word stream into an echo signal and supply it to the transmitter (6).
In the simulator device (1), the transmitter (6) is configured to up-convert the echo signal and radiate it to the distance measuring device (8) in the form of a second electromagnetic wave.
The signal delay device (4) is characterized in that it is configured according to any one of claims 1 to 15.
Simulator device (1). The simulator device (1) is characterized by having only one antenna (7) for transmission and reception.
The simulator device (1) according to claim 16. The simulator device (1) is characterized in that it is configured to simulate a distance in a radar or rider-based distance measuring device (8).
The simulator device (1) according to claim 16 or 17.

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