CN100407724C - Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection - Google Patents
Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection Download PDFInfo
- Publication number
- CN100407724C CN100407724C CN2003101125241A CN200310112524A CN100407724C CN 100407724 C CN100407724 C CN 100407724C CN 2003101125241 A CN2003101125241 A CN 2003101125241A CN 200310112524 A CN200310112524 A CN 200310112524A CN 100407724 C CN100407724 C CN 100407724C
- Authority
- CN
- China
- Prior art keywords
- concatenation
- parts
- adjacent
- conversion
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a device for the mutual conversion of hierarchical virtual cascade connection and adjacent cascade connection and an implementation method thereof. The present invention relates to data service access of synchronous digital hierarchy (SDH) in the communication area. The device comprises a VC-4-4c packaged STM-4 standard optical interface module in adjacent cascade connection, a VC-4-4v packaged STM-4 standard optical interface module in virtual cascade connection, an FPGA programmable logic device with large capacity, an RAM pool externally hung on the FPGA programmable logic device, an alarm indicator light connected to FPGA, and a power source module for supplying power to the device. The power source module is input with-48V direct current, which makes the device become an independent device. The present invention also discloses the method for the mutual conversion of the hierarchical virtual cascade connection and the adjacent cascade connection. The present invention realizes access and transmission of the data service in adjacent cascade connection without the need of fully upgrading an SDH network. The update is easy, and the cost is low.
Description
Technical field
The invention belongs to communication field, the data service that relates to the synchronous digital transmission system SDH system of communication field inserts.
Background technology
Existing a large amount of SDH equipment of operation on the net can only carry the VC-4-4v business, and the business that can not carry VC-4-4c along with the needs of broadband business developments such as IP, ATM, requires SDH equipment must be able to carry the business of VC-4-4c.Existing network will reach this requirement, must change the integrated circuit board of all-network node, has only all network nodes, has all changed the integrated circuit board of supporting the business of VC-4-4c, and whole network could carry the business of VC-4-4c.
GPT Ltd. is in Chinese patents: application number: 98118866 open days: on July 28th, 1999 exercise question: the transfer of data in the SDH network.This patent has been described the core concept of Virtual Concatenation and Adjacent Concatenation conversion, but does not relate to the processing of section overhead and the processing of clock.
In the relevant criterion of ITU-T, also only Virtual Concatenation, Adjacent Concatenation, H4 byte are defined, and point out also to need further research for the detailed description that the network interconnection rule of using dissimilar cascades needs, do not dilate the processing of clock and section overhead yet.
The SDH equipment that has now moved in network can not insert and transmit the data service that is packaged into the VC-4-4c form substantially.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of realization VC4-4 grade Virtual Concatenation and the mutual conversion equipment of Adjacent Concatenation, can insert and transmit the data service that is packaged into the VC-4-4c form, and the method that realizes that VC4-4 grade Virtual Concatenation and Adjacent Concatenation are changed mutually is provided on this basis.
Realization VC4-4 grade Virtual Concatenation among the present invention and the mutual conversion equipment of Adjacent Concatenation comprise:
Parts one: the STM-4 standard light interface module of Adjacent Concatenation VC-4-4c encapsulation;
Parts two: the STM-4 standard light interface module of Virtual Concatenation VC-4-4v encapsulation;
The big capacity programmable logic device of parts three: FPGA;
Parts four: the RAM pond that hangs over parts three outward;
Parts five: be connected on the alarm indicator on the FPGA;
Parts six: modular power source, power to this device; Being input as-the 48V direct current of power module makes this device become an independent device;
Have the professional STM-4 light signal of VC-4-4c, enter parts one, after opto-electronic conversion, send into FPGA, in FPGA, finish the conversion from VC-4-4c to VC-4-4v, through sending this equipment after the conversion of parts two electric light, enter SDH equipment again;
Through the professional light signal of the Virtual Concatenation VC-4-4v after the transmission of SDH network, enter parts two, after opto-electronic conversion, send into FPGA, in FPGA, finish the conversion from VC-4-4v to VC-4-4c, through sending this equipment after the conversion of parts one electric light, enter data equipment again; The conversion of this direction is carried out metadata cache at parts four, tolerates the network delay that different VC-4s never transmit with the path.
In device of the present invention, the light in the described parts one is sent out the light time receiving clock in the clock employing parts two; Light in the described parts two is sent out the light time receiving clock in the clock employing parts one, that is: change from the Adjacent Concatenation to the Virtual Concatenation, and the light of Virtual Concatenation is sent out the light time receiving clock that clock adopts Adjacent Concatenation, in whole translation process, also adopts this clock; The light time receiving clock that clock adopts Virtual Concatenation is sent out in conversion from the Virtual Concatenation to the Adjacent Concatenation, the light of Adjacent Concatenation, also adopts this clock in whole transfer process.
The present invention with outside annexation is, parts one link to each other with data equipment, and parts two link to each other with SDH equipment.
Realize the method for conversion from the Adjacent Concatenation to the Virtual Concatenation in realization VC4-4 grade Virtual Concatenation among the present invention and the mutual conversion equipment of Adjacent Concatenation, comprising:
3.1 frame head detects and descrambling code
The one group of signal that enters FPGA from Adjacent Concatenation light mouth has 8 77M data-signals, 1 77M clock signal, a 77M header signal, at first to detect the correctness of header signal designation data position, provide LOS, the LOF alarm indication signal, and data are carried out descrambling code handle;
3.2 the detection of section overhead and extraction
3.2.1 the detection of B1 error code provides B1 Error detection value and provides B1 error code alarm indication signal;
3.2.2 the B2 Error detection provides B2 error code alarm indication signal;
3.2.3 the extraction of M1, K2 (B6-B8) provides MS-AIS, MS-RDI, MS-REI alarm indication signal;
3.3 pointer interpreter
According to the pointer value of reality, generate the position indicative signal of J1, and, generate corresponding PAYLOAD index signal according to the situation that pointer is adjusted; Between NORM, LOP, these three kinds of states of AIS, shift, and provide corresponding condition indicative signal LOPI and AISI alarm;
3.4 path overhead detects
Comprise that mainly the B3 byte detects; The detection of G1 provides B3 error code alarm indication signal, HP-REI, HP-RDI alarm indication signal;
3.5 path overhead is inserted in the described frame
Adjacent Concatenation is received side and is sent out side J1, C2 to Virtual Concatenation, G1, and F2, F3, K3, the break-through of N1, a side is Adjacent Concatenation J1, C2, and G1, F2, F3, K3, N1 copy in the Virtual Concatenation each independently among the VC-4s;
3.6 the H4 byte is inserted in the described frame, the duplicating of AU-4 pointer
Two sections multiple frame numbers according to the frame sequence coding insert the H4 byte with SQ number coding rule representing the VC-4s order, and the pointer of finishing each VC-4s in the Virtual Concatenation simultaneously duplicates from the Adjacent Concatenation pointer;
3.7 the B3 check code is inserted in the described frame
Send out in the side Virtual Concatenation each VC-4 and carry out independently that the B3 error code generates and insertion, the detected B3 error code of Adjacent Concatenation side will pass to each VC-4s in the Virtual Concatenation;
3.8 section overhead is inserted in the described frame
3.8.1 the Regeneration Treatment of B2 check code, and transmit the B2 error code that Adjacent Concatenation is received side;
3.8.2 the Regeneration Treatment of B1 check code, and transmit the B1 error code that Adjacent Concatenation is received side,
3.8.3 the insertion of data scrambler and A1, A2.
Realize the method for conversion from the Virtual Concatenation to the Adjacent Concatenation in realization VC4-4 grade Virtual Concatenation among the present invention and the mutual conversion equipment of Adjacent Concatenation, comprising:
4.1 frame head detects and descrambling code
The one group of signal that enters FPGA from Virtual Concatenation light mouth has 8 77M data-signals, 1 77M clock signal, a 77M header signal; At first to detect the correctness of header signal designation data position, provide LOS, the LOF alarm indication signal, and data are carried out descrambling code handle;
4.2 the detection of section overhead and extraction
4.2.1 the detection of B1 error code provides B1 Error detection value and provides B1 error code alarm indication signal;
4.2.2 the B2 Error detection provides B2 error code alarm indication signal;
4.2.3 the extraction of M1, K2 (B6-B8) provides MS-AIS, MS-RDI, MS-REI alarm indication signal;
4.3 pointer interpreter
According to the pointer value of reality, generate the position indicative signal of J1, and, generate corresponding PAYLOAD index signal according to the situation that pointer is adjusted, between NORM, LOP, these three kinds of states of AIS, shift, and provide corresponding condition indicative signal LOPI and AISI alarm;
The receipts side of above processing Virtual Concatenation is identical with the receipts side of Adjacent Concatenation;
4.4 the 77M data-signal is to the conversion of 19M data-signal in the frame; The transmission rate of each VC-4s is reduced to 19M, respectively individual processing;
4.5 path overhead detects
Each VC-4s is carried out the B3 byte detect, provide the error performance alarm indication signal that transfinites; The detection of G1 provides HP-REI, the HP-RDI alarm indication signal;
4.6 H4 byte explanation module
H4 byte alarm detection,, H4 multi-frame sequence number and SQ number extraction, and by frame-duplicating serial number with generate the write address of plug-in SRAM for SQ number
4.7 Virtual Concatenation is reset to the formation of Adjacent Concatenation
Comprise plug-in SRAM interface read/write address, data, the generation of control signal; Plug-in RAM sense data is separated the processing of taking
4.8 pointer adjustment
4 VC-4s in the Virtual Concatenation are done unified pointer adjustment handle, do not match to eliminate speed;
4.9 pointer generates
Generate the pointer of VC-4-4c according to the position of J1;
4.10 the 19M data-signal is to the conversion of 77M data-signal
4.11 the B3 check code is inserted in the described frame
Send out the side Adjacent Concatenation and carry out generation of B3 error code and insertion, and transmit the B3 error code that Adjacent Concatenation is received side by the VC-4-4c form;
4.12 section overhead is inserted in the described frame
4.12.1 from receiver side copy all expenses except that pointer byte comprises the H3 byte, because of the Adjacent Concatenation clock originator derives from Virtual Concatenation receiving end clock, therefore need not storage, only simple copy gets final product;
4.12.2 the Regeneration Treatment of B2 check code, and transmit the B2 error code that Adjacent Concatenation is received side;
4.12.3 the Regeneration Treatment of B1 check code, and transmit the B1 error code that Adjacent Concatenation is received side;
4.12.4 the insertion of data scrambler and A1, A2;
Adopt the present invention, need not can realize the access and the transmission of the data service of operation in adjacent cascade connection to full SDH network upgrade, upgrading is easy, and with low cost.This device has been introduced the characteristics of SDH relaying when realizing.Break-through section overhead and path overhead so this device self need not webmaster and CPU, only need provide necessary stand by lamp indication to have or not alarm, look into the details of alarm by the network management system of SDH or data equipment.In the present invention, send out a clock and derive from the time receiving clock, make the simplification of logic, need not the section overhead of need break-through and path overhead is stored and in the insertion of transmitting terminal.Also need not pointer adjustment and pointer and generate, duplicating that the pointer of each VC-4s only carries out that the Adjacent Concatenation pointer duplicates in the Virtual Concatenation gets final product.Stand by lamp device indication alarm maintains easily.
Description of drawings
Conversion device structure schematic diagram among Fig. 1 the present invention;
Adjacent Concatenation among Fig. 2 the present invention is to the Virtual Concatenation flow path switch;
Virtual Concatenation among Fig. 3 the present invention is to the Adjacent Concatenation flow path switch;
Fig. 4 VC-4-4c structure (X=4) figure;
Fig. 5 VC-4-4v structure chart.
The multiple frame number definition of table 1 VC-4-4v SQ number and H4
Embodiment
The present invention realizes conversion mutually between VC-4 grade Virtual Concatenation and the Adjacent Concatenation, and main points are to insert to the H4 byte among each VC-4s of the conversion side of Virtual Concatenation SQ number that represents two sections multiple frame numbers that frame sequence is encoded and represent the VC-4s order at Adjacent Concatenation.Like this, different VC-4s can be by the transmission of different paths in the SDH network.At Virtual Concatenation to the conversion side of Adjacent Concatenation more again according to the sequence arrangement of former sequence number.Transmission delay difference because of the VC-4s through different paths reaches home in order to hold such time-delay, needs very big FIFO that VC-4s is carried out buffer memory, and FIFO in the present invention realizes that by plug-in SSRAM Core Feature realizes in FPGA (Field Programmable Gate Array).
The present invention shown in device among the present invention shown in Fig. 1 and Fig. 2,3 realizes transformation flow, device of the present invention and implementation method is illustrated in the technical scheme part, no longer repeats herein.
To describe the definition of Adjacent Concatenation and Virtual Concatenation below in detail, how frame will be numbered; And the alarming processing when recovering the frame label; Simultaneously, to describe also that clock among the design is handled and the method for overhead processing in detail; The alarm type of stand by lamp indication is described at last.Wherein, the definition of Adjacent Concatenation and Virtual Concatenation, and how frame is numbered part existing clearly definition in standard.
The definition of explanation Adjacent Concatenation and Virtual Concatenation at first, earlier:
In the time of can not fitting within the virtual container (VC-4) of standard effectively for the payload that transmits, can use the VC-4 cascade.Two kinds of Cascading Methods, Adjacent Concatenation and Virtual Concatenations have been defined.Two kinds of methods all are provided at the cascade bandwidth of 4 times of container VC4 of channel end.Difference is the transmission between the channel end.Adjacent Concatenation has kept adjacent bandwidth in whole transmission, and Virtual Concatenation has been broken adjacent bandwidth, enters independently among the VC, transmits independent VC, in the end point of transmission is recombinated these VC to one adjacent bandwidth again.Virtual Concatenation only needs cascade function at channel terminal device, and Adjacent Concatenation all needs cascade function at each network element.
The Adjacent Concatenation of 4 VC-4s (VC-4-4c):
A VC-4-4c provides the payload area of 4 container VC-4, sees Fig. 4.Be positioned at the general whole VC-4-4c (for example: BIP-8 has comprised all 261*4 row of VC-4-4c) that is provided for of a POH of first row.Row 2 to 4 are filled for fixing.
VC-4-4c transmits among 4 adjacent AU-4 in the STM-4 signal.First row of VC-4-4c are positioned at first AU-4 all the time.The pointer of this first AU-4 has been indicated the position of j1 byte among the VC-4-4c.The pointer of AU-4#2 to 4 is set to the cascade indication, indicates the payload of Adjacent Concatenation.AU-4 pointer adjustment for 4 cascades is finished jointly, and has used the 4*3 byte of padding.It is the payload of 599 040kbit/s that a VC-4-4c provides a capacity;
The Virtual Concatenation of 4 VC-4s (VC-4-4v);
VC-4-4v provides one 4 container VC-4 (VC-4-4c) adjacent payload area, and payload size is 599 040kbit/s, sees Fig. 5.Container mappings is advanced 4 independently VC-4, constitutes VC-4-4v.Each VC-4 has the POH of oneself.H4 POH byte is used for the Virtual Concatenation particular sequence, and two sections multi-frames of H4 byte and SQ number definition are seen in the multi-frame demonstrative definition.
The VC-4 of each VC-4-Xv transmits in network independently.Because the propagation delay that VC-4 is different independently will produce the difference time-delay between VC-4.This difference time-delay must be compensated, and each VC-3 must reset when entering payload area.
Secondly, introduce two sections multi-frames of H4 byte and SQ number definition again:
The multi-frame of two sections 512ms is tolerated the difference time-delay of 125 μ s and above (reaching 256ms).First section (The first stage) uses H4 the 5th to 8 bit is 4 bit multi-frames indications (MFI1).MFT1 increases once counting from 0 to 15 during every basic frame.For second section (the second stage) 8 bit multi-frames indication (MFI2), H4 is used for 1 to 4 bit (MFI2 bits 1-4) and 1 frame (MFI2 bits 5-8) (seeing Table 4-1) of first multi-frame, 0 frame.The increase of the every first step multi-frame of MFI2 once counts from 0 to 255.Therefore, all multi-frame be 4096 frame lengths (=512ms).
Constitute the sequence order of the independent VC-4 of adjacent container VC-4-4c among the sequence pointer SQ indication VC-4-4v, see Fig. 5.Each VC-4 of VC-4-4v has fixing unique sequence number, scope from 0 to 3.Transmit first VC-4 of VC-4-4c, its sequence number is 0; Second VC-4, its sequence number are 1; The 3rd VC-4, its sequence number are 2, the four VC-4, and its sequence number is 3.
The sequence number of 8 bits transmits in the 1st to the 4th bit of H4, uses 14 frames (SQbits 1-4) and 15 frames (SQ bits 5-8) of first multi-frame.See Table 1.
Alarming processing when recovering the frame label:
Conversion more complicated from the Virtual Concatenation to the Adjacent Concatenation, needs extract the frame number of H4 byte, simultaneously, also will carry out alarming processing, alarm as follows:
First section multiframe out-of-sync. (OOM1): in the MFI1 sequence number detection, continuous 4 frame mistakes are then thought first section multiframe out-of-sync. (OOM1).
Second section multiframe out-of-sync. (OOM2): in the MFI2 sequence number detection, continuous 4 frame mistakes take place or OOM1, then think second section multiframe out-of-sync. (OOM2).
Lose (DSQM) SQ number: during receive as continuous 4 frames SQ number and expectation inconsistent, report DSQM, when consistent, recover normal, withdraw from the SQ lost condition as continuous 4 frames.
Time-delay is crossed the border (DLOA): when transmitting by different paths, respectively independently VC-4s delay inequality scope transfinites.Enter cross the border (DLOA) that delay time.
Cross the border when alarm when system is in time-delay, show to exceed the system design scope that system can't operate as normal.
Design realizes allowing delay inequality.
The multiple frame number definition of table 1 VC-4-4v SQ number and H4
This device carries out the VC-4 storage with plug-in RAM, and that select for use is 2M byte SSRAM, can store 512 frame VC-4, and the delay inequality maximum of comparing of tolerable per 2 VC-4s is no more than 511 frames, is about 64MS.
Clock is handled:
The light of this device is sent out clock and is adopted the receiving end clock, changes from the Adjacent Concatenation to the Virtual Concatenation, and the light of Virtual Concatenation is sent out the light time receiving clock that clock adopts Adjacent Concatenation, in whole translation process, also adopts this clock.The light time receiving clock that clock adopts Virtual Concatenation is sent out in conversion from the Virtual Concatenation to the Adjacent Concatenation, the light of Adjacent Concatenation, also adopts this clock in whole transfer process.Adopt this clock processing mode, can simplify logical design, save logical block, reduce the expense of FPGA.As the conversion from the Adjacent Concatenation to the Virtual Concatenation, because of the send-receive clock unanimity, then the pointer of the pointer adjustment of 4 VC-4s and Adjacent Concatenation VC-4-4c is adjusted consistent in the Virtual Concatenation, therefore, need not to carry out the pointer adjustment and carry out the generation of pointer value again with FIFO again, the pointer value that the pointer value of 4 VC-4s only need simply be duplicated Adjacent Concatenation VC-4-4c in the Virtual Concatenation gets final product.In addition, section overhead is handled also and is simplified greatly, and because of same clock is used in transmitting-receiving, in the entire process process, STM-4 is by complete transmission, directly finished section overhead and break-through.If send-receive clock is inconsistent, then must carry out the storage of section overhead and insertion again, just can finish the break-through of section overhead.
Overhead processing:
Overhead processing adopts punch through mode, and be divided into the break-through of section overhead and the break-through of path overhead and duplicate, the processing mode of this expense, it is transparent that this device is regarded as, and need not webmaster and safeguard, saves cost.
Section overhead is handled and is comprised B1, B2 overhead processing, the pointer byte overhead processing, and other section overheads are handled.
B1, B2 overhead processing: carry out alarm detection at receiving terminal, carry out B1, the regeneration of B2 error code again, the error code alarm is arranged, then insert error code, thereby finish the error code break-through of B1, B2 at transmitting terminal as receiving terminal at transmitting terminal.Conversion from the Adjacent Concatenation to the Virtual Concatenation, receiving terminal are the receiving ends of Adjacent Concatenation, and transmitting terminal is making a start of Virtual Concatenation.Conversion from the Virtual Concatenation to the Adjacent Concatenation, receiving terminal are the receiving ends of Virtual Concatenation, and transmitting terminal is making a start of Adjacent Concatenation.
The processing of pointer byte expense: pointer byte comprises H1, H2, H3 byte, the conversion from the Adjacent Concatenation to the Virtual Concatenation, and the H1 of 4 VC-4s, H2 byte only need simply be duplicated H1, the H2 byte of Adjacent Concatenation VC-4-4c, the break-through of H3 byte in the Virtual Concatenation.Conversion from the Virtual Concatenation to the Adjacent Concatenation need regenerate H1, H2, H3 byte according to the situation of pointer adjustment.
Other section overhead bytes: break-through fully.Derive from the time receiving clock because of sending out clock, therefore in the entire process process, the STM-4 section overhead be need not to increase the punch-through process that added logic is carried out section overhead by complete reservation.
Path overhead is handled and comprised: the B3 path overhead is handled, H4 byte lane overhead processing, and other path overhead bytes are handled.
The B3 path overhead is handled: carry out alarm detection at receiving terminal, carry out the regeneration of B3 error code again at transmitting terminal, as receiving terminal the error code alarm is arranged, then insert error code at transmitting terminal, thereby finish the error code break-through of B3.Conversion from the Adjacent Concatenation to the Virtual Concatenation, as state's adjacent level be associated with B3 error code alarm then 4 VC-4s in Virtual Concatenation all to insert the B3 error code.Conversion from the Virtual Concatenation to the Adjacent Concatenation as long as there is a VC-4s that the alarm of B3 error code is arranged in the Virtual Concatenation, then will be inserted the B3 error code at Adjacent Concatenation.
H4 byte lane overhead processing: in the conversion side of Adjacent Concatenation to Virtual Concatenation, the H4 byte among each VC-4s is inserted the mark number of frame sequence coding and VC-4.Only finish the extraction of H4 byte and carry out respective handling to the conversion side of Adjacent Concatenation at Virtual Concatenation, the H4 byte need not to regenerate.
Other path overhead bytes are handled: other path overhead bytes comprise J1, C2, G1, F2, F3, K3, N1.In the conversion side of Adjacent Concatenation to Virtual Concatenation, the path overhead byte of 4 VC-4s is duplicated the path overhead byte of Adjacent Concatenation in the Virtual Concatenation.In the conversion side of Virtual Concatenation to Adjacent Concatenation, the path overhead byte of Adjacent Concatenation derives from the path overhead byte of first VC-4s in the Virtual Concatenation.
The alarm type of stand by lamp indication:
This device is provided with stand by lamp, can report history alarm, can remove history alarm and can observe the current alarm that whether has by reset key.Alarm type has: dropout; OOF; LOF; B1, B2, B3 error code; The regenerator section bit interleaves check errors; Multiplex Section AIS; The indication of multiplex section remote bug; The indication of multiplex section Far End Bit Error; Administration unit loss of pointer; Administration unit alarm indication signal; The indication of higher order path Far End Bit Error; The indication of higher order path remote bug; H4 byte Loss Of Multiframe; The H4 byte is lost for SQ number.
Claims (2)
1. grade Virtual Concatenation and the mutual conversion equipment of Adjacent Concatenation comprise:
Parts one: the STM-4 standard light interface module of Adjacent Concatenation VC-4-4c encapsulation;
Parts two: the STM-4 standard light interface module of Virtual Concatenation VC-4-4v encapsulation;
The big capacity programmable logic device of parts three: FPGA;
Parts four: the RAM pond that hangs over parts three outward;
Parts five: be connected on the alarm indicator on the FPGA;
Parts six: modular power source, power to this device;
Have the professional STM-4 light signal of VC-4-4c, enter parts one, after opto-electronic conversion, send into FPGA, in FPGA, finish the conversion from VC-4-4c to VC-4-4v, through sending this equipment after the conversion of parts two electric light, enter SDH equipment again;
Through the professional light signal of the Virtual Concatenation VC-4-4v after the transmission of SDH network, enter parts two, after opto-electronic conversion, send into FPGA, in FPGA, finish the conversion from VC-4-4v to VC-4-4c, through sending this equipment after the conversion of parts one electric light, enter data equipment again; The conversion of this direction is carried out metadata cache at parts four, tolerates the network delay that different VC-4s never transmit with the path.
2. described grade Virtual Concatenation of claim 1 and the mutual conversion equipment of Adjacent Concatenation is characterized in that, the light in the described parts one is sent out the light time receiving clock in the clock employing parts two; Light in the described parts two is sent out the light time receiving clock in the clock employing parts one, that is: change from the Adjacent Concatenation to the Virtual Concatenation, and the light of Virtual Concatenation is sent out the light time receiving clock that clock adopts Adjacent Concatenation, in whole translation process, also adopts this clock; The light time receiving clock that clock adopts Virtual Concatenation is sent out in conversion from the Virtual Concatenation to the Adjacent Concatenation, the light of Adjacent Concatenation, also adopts this clock in whole transfer process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2003101125241A CN100407724C (en) | 2003-12-08 | 2003-12-08 | Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2003101125241A CN100407724C (en) | 2003-12-08 | 2003-12-08 | Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1627751A CN1627751A (en) | 2005-06-15 |
| CN100407724C true CN100407724C (en) | 2008-07-30 |
Family
ID=34759804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2003101125241A Expired - Fee Related CN100407724C (en) | 2003-12-08 | 2003-12-08 | Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100407724C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668270B (en) * | 2009-10-19 | 2012-06-06 | 东方通信股份有限公司 | Method for solving Do not Disturb call based on ways of call interception and external platform hanging and platform |
| CN102811108B (en) * | 2011-06-02 | 2016-06-29 | 中兴通讯股份有限公司 | A kind of method and system optimizing pretection switch performance |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1051057A2 (en) * | 1999-04-29 | 2000-11-08 | Alcatel | Transport of concatenated containers in a synchronous transmission network |
| JP2002232380A (en) * | 2001-01-30 | 2002-08-16 | Nec Corp | Concatenation signal processing method and apparatus |
| WO2003063396A1 (en) * | 2002-01-16 | 2003-07-31 | Agilent Technologies, Inc. | Method and apparatus for measuring differential delay in a sonet/sdh-system using virtual concatenation |
-
2003
- 2003-12-08 CN CN2003101125241A patent/CN100407724C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1051057A2 (en) * | 1999-04-29 | 2000-11-08 | Alcatel | Transport of concatenated containers in a synchronous transmission network |
| JP2002232380A (en) * | 2001-01-30 | 2002-08-16 | Nec Corp | Concatenation signal processing method and apparatus |
| WO2003063396A1 (en) * | 2002-01-16 | 2003-07-31 | Agilent Technologies, Inc. | Method and apparatus for measuring differential delay in a sonet/sdh-system using virtual concatenation |
Non-Patent Citations (4)
| Title |
|---|
| VC-4的相邻级联、虚级联以及互通. 毛谦.现代有线传输，第1期. 2000 |
| VC-4的相邻级联、虚级联以及互通. 毛谦.现代有线传输，第1期. 2000 * |
| 用于千兆以太网数据传输的SDH虚级联技术. 史国炜，刘昭，曾烈光，王松梅，于春水.通讯与电视，第12期. 2002 |
| 用于千兆以太网数据传输的SDH虚级联技术. 史国炜，刘昭，曾烈光，王松梅，于春水.通讯与电视，第12期. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1627751A (en) | 2005-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101160845B (en) | Data transmission method and data interface and equipment of high speed Ethernet to optical transmission network | |
| EP0559091B1 (en) | Apparatus and method for transporting SONET overhead signal information | |
| US6765928B1 (en) | Method and apparatus for transceiving multiple services data simultaneously over SONET/SDH | |
| CN101167281B (en) | Method and apparatus for synchronous switching of optical transport network signals | |
| US20070248119A1 (en) | Transmission system | |
| CN101313507A (en) | Method and apparatus for transmitting service of synchronous digital system in passive optical network | |
| US6839871B2 (en) | Method for transparent multiplexing of SONET/ SDH streams | |
| US7227844B1 (en) | Non-standard concatenation mapping for payloads | |
| CA2472980C (en) | Communications system | |
| CN101243656A (en) | Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET | |
| CA1331639C (en) | Process for coupling and uncoupling signals into and out of the sub-areas of supplementary signals of transport modules of a synchronous digital signal hierarchy | |
| US7353288B1 (en) | SONET/SDH payload re-mapping and cross-connect | |
| JPH0693669B2 (en) | Method for inserting an asynchronous 139264-Kbits / sec-signal into a 155520-K bits / sec-signal | |
| US5457691A (en) | Method and apparatus for intrasystem communication links in a transmission system using synchronous data hierarchy | |
| CN100407724C (en) | Conversion device and implementation method between hierarchical virtual cascade connection and adjacent cascade connection | |
| EP1537694B1 (en) | Synchronous transmission network node | |
| CN100496045C (en) | Method and system for supporting data framing protocol on multi-service transmission node equipment | |
| US7808991B2 (en) | Network-based data transport architecture | |
| US20080101377A1 (en) | Efficient Scalable Implementation of VCAT/LCAS for SDH and PDH Signals | |
| CA2338812A1 (en) | Method and system for improved sonet data communications channel | |
| CN100550716C (en) | Realize professional method and system of intersecting | |
| KR100263382B1 (en) | Unit of arranging tributary unit pointer and administration unit pointer for time slot interchange function in fiber loop carrier system | |
| KR20000021550A (en) | Device for processing au(administrative unit) pointer and tu(tributary unit) pointer for au signal in optical subscriber transmission device | |
| KR100271312B1 (en) | A switching appatus of administative unit | |
| Ho | A novel method for insertion of overhead information into SONET frames |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080730 Termination date: 20171208 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |