CN116915354A - Method for multiplexing multiple low-speed branch signals to STM-N - Google Patents
Method for multiplexing multiple low-speed branch signals to STM-N Download PDFInfo
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- CN116915354A CN116915354A CN202311033406.5A CN202311033406A CN116915354A CN 116915354 A CN116915354 A CN 116915354A CN 202311033406 A CN202311033406 A CN 202311033406A CN 116915354 A CN116915354 A CN 116915354A
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- 238000004891 communication Methods 0.000 abstract description 5
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
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Abstract
The invention relates to a method for multiplexing a plurality of low-speed branch signals to STM-N, belonging to the SDH communication field. The method sequentially maps/transmits the low-speed branch signal to a container C-12, a virtual container VC-12, a branch unit TU-12, a branch unit group TUG-2, a branch unit group TUG-3, a virtual container VC-4, a management unit AU-4 and a management unit group AUG; and finally, adding the overhead parts to the N management unit groups AUG to form an STM-N frame. The mapping and transmission modes provided by the invention can multiplex M low-order services into any N STM time slots. The method solves the problem of multiplexing a plurality of services of a single FPGA, improves the product competitiveness, and has huge market prospect.
Description
Technical Field
The invention relates to a method for multiplexing a plurality of low-speed branch signals to STM-N, belonging to the SDH communication field.
Background
The synchronous digital hierarchy (Synchronous Digital Hierarchy, SDH for short) is a technical system formed by a multiplexing method, a mapping method and a related synchronization method, wherein the synchronous digital hierarchy (Synchronous Digital Hierarchy, SDH for short) is an information structure for providing corresponding grades for transmission of digital signals with different rates. An SDH signal is a synchronously transmitted signal, the inner part of which is a plurality of time slots, into which different services can be multiplexed.
The international union is in ITU-T rec.g.707, which specifies the frame structure of STM-N signals. An STM-N frame is defined to be made up of 9 rows of 270 x N columns of data blocks, where each row contains 9 x N overhead bytes and 261 x N payload bytes. Wherein 261 x N columns are VC4 data, and the overhead area is divided into a segment overhead area (SOH) and a management unit pointer area
At present, multiplexing of a single low-speed branch service is mostly supported based on the mode that the FPGA multiplexes the low-speed branch signals to STM-N. Such boards are single in function and difficult to meet increasingly complex communication requirements. There is a need for a way to meet the product demand for multiple low speed leg traffic communications
Disclosure of Invention
The invention aims to solve the technical problems that: the method for multiplexing the plurality of low-speed branch signals to the STM-N solves the problem that a plurality of low-speed branch services are multiplexed into the time slot of any STM-N at the same time, and meets the requirement of products on the communication of the plurality of low-speed branch services.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: mapping/transmitting each path of low-speed branch signals to a container C-12, a virtual container VC-12, a branch unit TU-12, a branch unit group TUG-2 and a branch unit group TUG-3 in sequence, and then selecting corresponding time slots mapped into the virtual container VC-4, a management unit AU-4 and the management unit group AUG through an external control unit; finally, N management unit groups AUG are added with overhead parts to form STM-N frames through N AUG modules and corresponding gating;
preprocessing the low-speed branch signal, mapping the low-speed branch signal into a container C-12 according to a group of frame formats of 9 rows and 63 columns, and mapping the low-speed branch signal into a virtual container VC-12 after code speed adjustment;
the low-speed tributary signal in the virtual container VC-12 is adapted to the tributary unit TU-12 through pointer adjustment;
the unit TU-12 bytes are interleaved to TUG-2, TUG-2 bytes are interleaved to TUG-3 and then bytes are interleaved to the virtual container VC-4.
The low-speed branch signal in the virtual container VC-4 is adapted to the management unit AU-4 and the management unit group AUG through pointer adjustment;
the further improvement of the scheme is as follows: the low-speed tributary signals are adapted to tributary units TU-12 through pointer adjustment, i.e. the data of the low-speed tributary signals occupy 4 columns of data when mapped into TU12, and each tributary unit group TUG-2 stores the data of three groups of the low-speed tributary signals in a sequence of 4 columns.
The further improvement of the scheme is as follows: the slot data of 3 TU-12 are multiplexed into 1 tributary unit group TUG-2 by byte insertion.
The further improvement of the scheme is as follows: the 7 TUGs-2 are multiplexed into 1 larger tributary unit group TUG-3 by byte-interleaving of 7 bytes.
The further improvement of the scheme is as follows: the 3 TUGs-3 are multiplexed into the virtual container VC-4 by 3 byte interleaving and mapped into corresponding slots of the virtual container VC-4 by an external control unit.
The further improvement of the scheme is as follows: the tributary unit group TUG-3 is larger than the tributary unit group TUG-2.
The beneficial effects of the invention are as follows: the existing products based on the FPGA are all single service multiplexing, and the invention creatively provides a multi-service multiplexing scheme based on a single FPGA. The mapping and transmission modes provided by the invention can multiplex M low-order services into any N STM time slots. The method solves the problem of multiplexing a plurality of services of a single FPGA, improves the product competitiveness, and has huge market prospect.
Drawings
FIG. 1 is a process schematic of an embodiment of the present invention.
Fig. 2 is a schematic diagram of low branch signal data from the branching unit TU-12 to the virtual container VC-4 in the embodiment of the present invention.
Fig. 3 is a schematic diagram of a low-order service assembled into a VC-12 frame format in an embodiment of the present invention.
Detailed Description
In one method of multiplexing a plurality of low-speed tributary signals to STM-N of the present embodiment, as shown in FIG. 1, each low-speed tributary signal is mapped/transmitted to a container C-12, a virtual container VC-12, tributary units TU-12, tributary unit groups TUG-2, tributary unit groups TUG-3 in sequence, and then mapped into corresponding time slots of the virtual container VC-4, the management unit AU-4 and the management unit groups AUG by an external control unit; finally, N management unit groups AUG are added with overhead parts to form STM-N frames through N AUG modules and corresponding gating;
preprocessing the low-speed branch signal, mapping the processed low-speed branch signal into a container C-12 as shown in a group of frame formats of 9 rows and 63 columns in FIG. 3, and mapping the processed low-speed branch signal into a virtual container VC-12 after code rate adjustment.
The low speed tributary signals in said virtual container VC-12 are adapted to the tributary unit TU-12 via pointer adjustment. That is, the data of the low-speed tributary signal occupy 4 columns of data when mapped into the TU12, and each tributary unit group TUG-2 stores data of three groups of the low-speed tributary signals in a group order of 4 columns.
The virtual container VC-12 is subjected to interleaved multiplexing to the virtual container VC-4, namely, time slot data of 3 TU-12 are subjected to byte interleaved multiplexing to form 1 tributary unit group TUG-2; the 7 TUGs-2 are multiplexed into 1 larger tributary unit group TUG-3 by byte interleaving of 7 bytes; the 3 TUGs-3 are multiplexed into the virtual container VC-4 by 3 byte interleaving and mapped into corresponding slots of the virtual container VC-4 by an external control unit.
The low-speed branch signal in the virtual container VC-4 is adapted to the management unit AU-4 and the management unit group AUG through pointer adjustment; i.e. when VC-4 enters AU-4, an AU-4 pointer (AU-4 PTR) should be added, i.e. AU-4 = VC-4+ AU-4PTR, for details reference is made tohttps://www.alloll.com/News/CommunicationIndustry/411.htmlThis is a method specified in accordance with the ITU-T rec.g.707 standard. Where AUG-N is a 9 row N x column plus N x byte frame structure for the fourth row. When n=1, AUG-1 contains only one AU-4 frame. See ITU-T Rec.G.707 at page 18.
The tributary unit group TUG-3 is larger than the tributary unit group TUG-2.
The low-speed branch signal is mapped into a virtual container VC-12 according to a group of frame formats of 9 rows, 63 columns and four groups through code adjustment.
As shown in fig. 2, when the low-order data is mapped into TUs 12, it will occupy 4 columns of data, and according to the red arrow in fig. 1, it can be known that 3 TUs 12 are spliced into one TUG12 of 12 columns, so that the first three data blocks in the first row of fig. 2 are spliced, and at this time, 63 TUs 12 in the first row are spliced into 63/3=21 TUGs 12 (byte interleaving), and the second row is seen.
Since 7 TUGs 12 are spliced into 1 TUG3, see the second row of fig. 2, the first 7 TUGs 12 are spliced into 86 columns of TUGs-3A (valid data column 7x12=84 columns), and since there are 21 TUGs 12 at this time, 21/7=3 TUGs 3 can be spliced in total, namely TUGs-3A, TUGs-3 b, TUGs-3C of the third row. The 3 TUGs 3 are spliced into 1 VC4 according to the byte inserting rule, see the fourth row of fig. 2, and one TUG3 has 84 columns of valid data, so that after the 3 TUGs 3 bytes are spliced, the total of 84 x3=252 columns of valid data is just 63 TUs 12, the total of 63 x4=252 columns of data, and the first 1 column POH and 8 columns of padding data are just 261 columns of data. From the numbers in the columns in fig. 2, it can be known how the 63 TU-12 maps are multiplexed into one STM-1 frame and the positions of the respective TUs-12 in VC-4, after the mapping of the first TU12 block of data in green in the figure, at the 10 th, 73 th, 137 th, 206 th position of VC 4. From column 10 to column 72, which are 63 columns altogether, 63 TUs 12 may be inserted in byte inserts, with the corresponding positions of the lower 3 sets of 63 columns being the corresponding data positions of the remaining TUs 12. Four columns of data corresponding exactly to TU12, so that one VC4 can put 63 TU12 data
As can be seen from fig. 2, each VC-4 virtual container can multiplex up to 63 low order services, and there are N slots in STM-N, so that if M low order services need to be received, there can be up to mxn multiplexing options. How to implement multiplexing of multiple services is a difficult problem.
Firstly, M low-order services are respectively formed into a VC12 format, in the assembling process, the low-order service data are assembled into VC12 data according to the frame format of figure 3, and each 63 time slots are the same data, so that 36 (4 rows and 9 columns) data, namely one frame of VC12 data, are exactly contained.
Then, in the vc12_to_vc4 module, the external control module unit selects the multiplexing time slot, and multiplexes the multiple VCs-12 into the corresponding positions in 63 time slots of the VC-4, because each 63 time slots in the front-end module are the same data, when the selected corresponding time slots are filled with data, the module will put the correct data into the corresponding time slots, so that M services can be multiplexed into one VC4 container at will.
For multiplexing of the back-end STM-N N time slots, we need to instantiate N vc12_to_vc4 modules, the output of which passes through a gating module, which is connected to the following vc4_au-4 module, and adds corresponding pointer units. And finally, the assembled data are interleaved into an STM-N signal according to the bytes. Whether the corresponding strobe is on determines whether the data of the vc12_to_vc4 module is multiplexed into the STM-N slot, thus completing the M x N multiplexing.
Claims (6)
1. A method of multiplexing a plurality of low speed tributary signals to an STM-N, comprising: mapping/transmitting each path of low-speed branch signals to a container C-12, a virtual container VC-12, a branch unit TU-12, a branch unit group TUG-2 and a branch unit group TUG-3 in sequence, and then selecting corresponding time slots mapped into the virtual container VC-4, a management unit AU-4 and the management unit group AUG through an external control unit; finally, N management unit groups AUG are added with overhead parts to form STM-N frames through N AUG modules and corresponding gating;
preprocessing the low-speed branch signal, mapping the low-speed branch signal into a container C-12 according to a group of frame formats of 9 rows and 63 columns, and mapping the low-speed branch signal into a virtual container VC-12 after code speed adjustment;
the low-speed tributary signal in the virtual container VC-12 is adapted to the tributary unit TU-12 through pointer adjustment;
the unit TU-12 bytes are interleaved to TUG-2, TUG-2 bytes are interleaved to TUG-3 and then bytes are interleaved to the virtual container VC-4;
the low-speed tributary signals in the virtual container VC-4 are adapted to the management unit AU-4 and the management unit group AUG via pointer adjustment.
2. A method of multiplexing a plurality of low speed tributary signals to an STM-N according to claim 1, wherein: the low-speed tributary signals are adapted to tributary units TU-12 through pointer adjustment, i.e. the data of the low-speed tributary signals occupy 4 columns of data when mapped into TU12, and each tributary unit group TUG-2 stores the data of three groups of the low-speed tributary signals in a sequence of 4 columns.
3. A method of multiplexing a plurality of low speed tributary signals to an STM-N according to claim 1, wherein: the slot data of 3 TU-12 are multiplexed into 1 tributary unit group TUG-2 by byte insertion.
4. A method of multiplexing a plurality of low speed tributary signals to an STM-N according to claim 1, wherein: the 7 TUGs-2 are multiplexed into 1 larger tributary unit group TUG-3 by byte-interleaving of 7 bytes.
5. A method of multiplexing a plurality of low speed tributary signals to an STM-N according to claim 1, wherein: the 3 TUGs-3 are multiplexed into the virtual container VC-4 by 3 byte interleaving and mapped into corresponding slots of the virtual container VC-4 by an external control unit.
6. A method of multiplexing a plurality of low speed tributary signals to an STM-N according to claim 1, wherein: the N AUGs are composed of N corresponding mapping frames plus a gating module, and finally, the needed content is spliced into an STM-N format.
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| CN202311033406.5A CN116915354A (en) | 2023-08-16 | 2023-08-16 | Method for multiplexing multiple low-speed branch signals to STM-N |
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| CN202311033406.5A CN116915354A (en) | 2023-08-16 | 2023-08-16 | Method for multiplexing multiple low-speed branch signals to STM-N |
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