JP3309161B2 - CID pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for generating a CID pattern in a synchronous transfer mode at a high speed.

[0002]

2. Description of the Related Art STM which is one of data transmission systems
In (synchronous transfer mode), as shown in FIG.
9x9 byte SOH (section overhead) section
One frame consists of a 9 x 261 byte payload
SDH (Synchronous Digital Hierarchy)
In addition to the basic standard called STM-1 that uses signals
In addition, as shown in FIG. 6B, K × 9 × 9 bytes (K is
2 for an integer P greater than or equal to 2 ^pSOH)
(Section overhead) section and K × 9 × 261 bytes
STM-K that constitutes one frame with the payload part of
There is a standard called.

In an apparatus for receiving an SDH signal having such a frame structure, a clock signal is reproduced from an input SDH signal, and a reception process is performed using the reproduced clock signal.

However, if data of 0 or 1 continues for a long time in the SDH signal, the clock cannot be correctly reproduced.

[0005] Therefore, in order to evaluate an apparatus for receiving and processing an SDH signal, it is necessary to examine a clock recovery capability (clock recovery tolerance) for a length of continuous data of 0 or 1.

As a signal pattern for performing this test, the ITU-T (G.958) recommends using a CID (Consecutive Identity Digit) pattern.

[0007] As shown in FIG. 7, this CID pattern is composed of an MOH pattern having an arbitrary byte length of 0 (or 1) in the range of 1 to 100 bytes after one row of the SOH (K × 9 byte length). Subsequently, a pseudo-random signal is inserted into the remaining area following the continuous pattern to form one frame.

FIG. 8 shows a configuration of a conventional CID pattern generator 10 for generating such a CID pattern.

The CID pattern generation device 10 has a SO
An H data generator 11, a continuous pattern generator 12, a continuous pattern length setting means 13, and a pseudo random signal generator 14 are provided.

[0010] The SOH data generation section 11 receives a start signal S and a completion signal E from the pseudo random signal generation section 14.
3, the SOH data of the above-mentioned CID pattern is sequentially output in an 8-bit (1 byte) width in synchronization with the clock signal CK, and when the last 8-bit SOH data is output, the completion signal E1 is output to the continuous pattern. The data is output to the generation unit 12 and the output of the SOH data is stopped.

When receiving the completion signal E1 from the SOH data generating unit 11, the continuous pattern generating unit 12 sequentially converts the 0 or 1 continuous pattern of the byte length M set by the continuous pattern length setting means 13 into a 1-byte width. Then, when the continuous pattern of the last byte is output, the completion signal E2 is output to the pseudo-random signal generator 14, and the output of the continuous pattern is stopped.

When receiving the completion signal E2 from the continuous pattern generation unit 12, the pseudo random signal generation unit 14 changes the total byte length of one frame (K × 9 × 270) to the byte length of SOH data (K × 9). The pseudo-random signals of the remaining bytes J, which are obtained by subtracting the sum of the byte lengths M of the continuous pattern, are sequentially output with a 1-byte width, and when the pseudo-random signal of the last byte is output, the completion signal E3 is sent to the SOH data generator 11. And stops the output of the pseudo-random signal.

Therefore, as shown in FIG. 8, the CID pattern generator 10 generates a K × 9 byte SOH.
CID followed by data, followed by a continuous pattern of 0 (or 1) for M bytes, and a pseudo random signal for J bytes
The pattern is output continuously.

[0014]

However, as described above, in the conventional CID pattern generator 10 configured to output CID pattern data in 1-byte width, even if a high-speed ECL element is used. The bit rate of 2.5 GHz (approximately 312 M / byte) is the limit, and it has been extremely difficult to realize the bit rate of 10 GHz required recently.

To solve this, the output width of the SOH data, the continuous pattern and the pseudo random signal is set to, for example, 4
It is conceivable to increase the output bit rate to 4 times by increasing the number of bytes. In such a case, the byte length of the continuous pattern is set to 4 bytes in order to maintain continuity between frames of the pseudo-random signal. It must be set to an integral multiple, and it will not be possible to test with an arbitrary byte length M.

An object of the present invention is to solve this problem and to provide a CID pattern generator capable of arbitrarily setting the byte length of a continuous pattern and realizing a high output bit rate.

[0017]

In order to achieve the above object, a CID pattern generating apparatus according to the present invention converts UOH bytes of SOH data (U is a multiple of 9) into N in synchronization with a predetermined clock signal. byte width (N is a number represented by ^{2 P} for integer P) SOH data generation portion for outputting in parallel (21)
A continuous pattern length setting means (23) for arbitrarily setting a byte length M of a continuous pattern in which 0s or 1s continue within a predetermined range, and S output from the SOH data generator.
Following the OH data, the N-byte continuous pattern is synchronized with the clock signal a number of times equal to the quotient A when the byte length M set by the continuous pattern length setting means is divided by the output byte width N. And a pseudo-random signal generator that outputs a pseudo-random signal in N-byte width in synchronization with the clock signal following the continuous pattern output from the continuous pattern generator. 24), wherein the SOH data, the M-byte continuous pattern following the SOH data, and the pseudo random signal following the continuous pattern
What is claimed is: 1. A CID pattern generating apparatus for generating a CID pattern constituting a frame with an N-byte width, wherein said pseudo-random signal generator performs an exclusive OR operation on N-byte parallel input data to perform N-byte parallel pseudo-data. A logical operation circuit (25) for generating a random signal, latching of N-byte parallel data, and shifting of the latched data to the lower side in units of 1 byte are enabled, and the logical operation circuit generates A first latch shift circuit (26) for latching an N-byte parallel pseudo-random signal each time a latch signal is received, and inputting the latched data to the logical operation circuit to generate a next-stage pseudo-random signal; A latch of N bytes of parallel data, and one of the latched data
The first latch shift circuit is configured to be able to shift to the lower side in byte units and to be able to shift and input the least significant 1-byte data from the uppermost side of the first latch shift circuit; A second latch shift circuit (29) for latching the N-byte pseudo-random signal latched by the second latch shift circuit each time the latch signal is received, and the N-byte data latched by the second latch shift circuit, A synthesizing circuit (32) for replacing the arbitrary byte data on the upper side with the same data as the continuous pattern generated by the continuous pattern generating unit and outputting the same, and performing the logical operation while the SOH data and the continuous pattern are being output. Stopping the latch operation of the first and second latch shift circuits with respect to a new pseudo-random signal generated by the circuit; When the byte length M that cannot be divided by the output byte width N is set by the turn length setting means, the latch data of the first and second latch shift circuits is shifted by the number of bytes equal to the remainder B, After the continuous pattern is output A times, the S
Until OH data is output, a latch signal synchronized with the clock signal is supplied to the first and second latch shift circuits, and a new pseudo-random signal generated by the logical operation circuit is sequentially generated by the synthesis circuit. And the same data as the continuous pattern is inserted into the upper byte equal to the remainder B in the N-byte pseudo random signal which is first latched by the second latch shift circuit and output to the synthesizing circuit. And a control circuit (35) for outputting the data.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a CID according to an embodiment of the present invention.
1 shows a configuration of a pattern generation device 20.

This CID pattern generation device 20 has a
The SDH signal of the MK CID pattern is output in a width of N bytes (N is a number represented by ^2P with respect to an integer P). Generator 22, continuous pattern length setting means 23,
It has a pseudo-random signal generator 24.

Upon receiving a start signal S from an operation unit (not shown) or an external device and a completion signal E3 from the pseudo random signal generation unit 24, the SOH data generation unit 21 converts the SOH data of the CID pattern into a clock signal CK.
, And outputs the completion signal E1 to the continuous pattern generator 22 when the last N bytes of SOH data are output, and stops the output of SOH data.

Here, if the output byte width N is equal to or less than the value K of the standard STM-K of the SDH signal to be output, the SOH data of the frame can be output with N bytes and a predetermined number of clocks.

That is, STM-4, STM-16, STM
In the case of −64, the amount of SOH data inserted in one frame is 9 × 4 bytes, 9 × 16 bytes, and 9 × 64 bytes, respectively.
Since the value is a value obtained by multiplying a multiple U of 9 by N in bytes, if the output byte width N is 4, STM-4, STM-16,
The amount of SOH data is N for any of the STM-64
9 clocks, 36 clocks, 25 clocks respectively
Output can be made with 6 clocks. Also, when N is 16, the byte amount of SOH data is divisible by N and can be output with 9 clocks and 36 clocks regardless of STM-16 or STM-64. In the case of STM-64, the byte amount of SOH data is divisible by N and can be output with 9 clocks.

When receiving the completion signal E1 from the SOH data generator 21, the continuous pattern generator 22 synchronizes the 0 or 1 continuous pattern of the byte length M set by the continuous pattern length setting means 23 with the clock signal CK. Then N
Output sequentially in byte width.

The continuous pattern generation unit 22 generates N bytes of the number of times equal to the quotient A (including the case where the pattern length M is not divisible) when the pattern length M set by the continuous pattern length setting means 23 is divided by the output byte width N. When the continuous patterns are output in parallel, a completion signal E2 is output to the pseudo-random signal generator 24, and the output of the continuous patterns is stopped.

Upon receiving the completion signal E2 from the continuous pattern generating unit 22, the pseudo random signal generating unit 24 calculates the SOH from the total byte length of one frame (K × 9 × 270 bytes).
A pseudo-random signal of a remaining byte (this remaining byte is also divisible by N) obtained by subtracting the sum of the byte length (K × 9 bytes) of the data and the byte length MB of the continuous pattern after subtracting the remainder B is a clock signal. And outputs the completion signal E3 to the SOH data generator 21 when the pseudo-random signal of the last byte is output, and stops the pseudo-random signal output.

When the continuous pattern length setting means 23 sets a byte length M that is not divisible by N, the pseudo-random signal generating section 24 sets a remainder B at the head of the pseudo-random signal output first in the next frame. The internal data can be shifted in byte units so that a continuous pattern can be inserted to generate N-byte data.

That is, as shown in FIG. 1, the pseudo-random signal generator 24 includes a logical operation circuit 25, a first latch shift circuit 26, a second latch shift circuit 29, a synthesizing circuit 32, and a control circuit 35. It is constituted by.

The logical operation circuit 25 has 8 · N exclusive OR circuits (not shown), and performs an exclusive OR operation on the input N-bit pseudo random signal bit data in a predetermined combination. Each operation is performed, and the operation results are used as the next N-byte pseudo random signals Ra (1) to Ra (N).
Output as

The first latch shift circuit 26 outputs an N-byte pseudo random signal R output from the logical operation circuit 25.
a (1) to Ra (N) are latched in synchronization with the latch signal CK ', and their latch outputs Rb (1) to Rb
(N) is fed back to the logical operation unit 25 to generate the next-stage pseudo-random signal.

The second latch shift circuit 29 includes latch outputs Rb (1) to Rb of the first latch shift circuit 26.
(N) is latched in synchronization with the latch signal CK ', and the latch outputs Rc (1) to Rc (N) are output as pseudo-random signals.

The first latch shift circuit 26 and the second latch shift circuit 29 are configured so that the latched data can be shifted to the lower side in units of one byte, and the lower side of the second latch shift circuit 29 Are connected so that the shift output of the first latch shift circuit 26 is shifted into the upper side.

FIG. 2 shows a configuration example of the first latch shift circuit 26 and the second latch shift circuit 29.
As shown in FIG. 2, the first latch shift circuit 26 receives N selectors 27 (1) to 27 (N) for selectively outputting 1-byte data and a latch signal CK '. And N latch circuits 28 (1) to 28 (N) for latching input data in units of one byte each time. Similarly, the second latch shift circuit 29 selectively outputs one byte of data. N-1 selectors 30 (1) to 2 (2)
7 (N-1) and N latch circuits 31 for latching input data in units of one byte each time a latch signal CK 'is received.
(1) to 31 (N).

The selector 27 (1) has a logic operation circuit 25
Output Ra (1) and the output Rc of the latch circuit 31 (N).
(N) is input to the latch circuit 28 (1).

The selector 27 (2) outputs one of the output Ra (2) of the logical operation circuit 25 and the output Rb (1) of the latch circuit 28 (1) to the latch circuit 28 (2).
, And the selector 27 (3) outputs the signal to the logical operation circuit 25.
Output Ra (3) and the output Rb of the latch circuit 28 (2).
Either side of (2) is input to the latch circuit 28 (3).

Similarly, for m = 4 to N, the selector 27 (m) outputs the output Ra (m) of the logical operation circuit 25.
And the output Rb (m) of the upper latch circuit 28 (m-1).
-1) is input to the latch circuit 28 (m).

Each of the selectors 27 (1) to 27 (N) controls the latch circuits 28 (1) to 28 (N-1) while the shift signal F output from the control circuit 40 is at a high level, for example.
30 (N) is selected, and the output of the logical operation circuit 25 is selected while the shift signal F is at the low level.

On the other hand, the output Rb (1) of the latch circuit 28 (1) is directly input to the latch circuit 31 (1) on the second latch shift circuit 29 side, and the selector 30 (1)
Causes one of the output Rb (2) of the latch circuit 28 (2) and the output Rc (1) of the latch circuit 31 (1) to be input to the latch circuit 31 (2).

The selector 30 (2) is connected to the output Rb (3) of the latch circuit 28 (3) and the latch circuit 31 (2).
Output Rc (2) is connected to the latch circuit 31.
(3), and the selector 30 (3) outputs the output Rb (4) of the latch circuit 28 (4) to the latch circuit 31 (3).
Output Rc (3) is connected to the latch circuit 31
(4).

Similarly, for m = 4 to N-1, the selector 30 (m) outputs the output Rb (m + 1) of the latch circuit 28 (m + 1) and the output Rb (m + 1) of the higher-order latch circuit 31 (m). Rc (m) is connected to the latch circuit 31 (m +
1) Input.

Each of the selectors 30 (1) to 30 (N-1)
Means that while the shift signal F output from the control circuit 40 is, for example, at a high level, the latch circuits 31 (1) to 31 (N−
The output of 1) is selected, and the outputs of the latch circuits 28 (2) to 28 (N) are selected while the shift signal F is at the low level.

Therefore, while the shift signal F is at a low level, the outputs Ra (1) to Ra (N) of the logical operation circuit 25 are kept unchanged each time the latch signal CK 'is input. 28 (N), and outputs Rb (1) to Rb of the latch circuits 28 (1) to 28 (N).
(N) is directly latched by the latch circuits 31 (1) to 31 (N).

While the shift signal F is at the high level,
Each time the latch signal CK 'is input, the latch circuit 28
Outputs Rb (1) to Rb (N) of (1) to 28 (N) and outputs Rc (1) of latch circuits 31 (1) to 31 (N)
~ Rc (N) is shifted to the lower side in byte units.

The output Rc of the second latch shift circuit 29
(1) to Rc (N−1) are output via the synthesis circuit 32.

When the byte length M set by the continuous pattern length setting means 23 cannot be divided by the output byte width N, the synthesizing circuit 32 generates the pseudo random signal generator 24.
This is for inserting the surplus data of the continuous pattern output from the continuous pattern generation unit 22 into the N-byte data output first from the upper side. For example, as shown in FIG. It is composed of N-1 selectors 33 (1) to 33 (N-1) for selecting and outputting.

Each of the selectors 33 (1) to 33 (N-1) has 1-byte data of 0 or 1 and each output Rc (1) to Rc (N-1) of the second latch shift circuit 29. Is input, and data to be selected is designated by the N-1 bit composite signal Q from the control circuit 35.

For example, when the upper H bits of the composite signal Q are 1
When the remaining bits are 0 (low level) at (high level), the upper H selectors 33 (1) to 33 (H) of the selectors 33 (1) to 33 (N-1) are A continuous pattern of 0 or 1 is selected, and the remaining selectors 33 (H
+1) to 33 (N-1) correspond to the second latch shift circuit 29
Of the outputs Rc (H + 1) to Rc (N-1)
A continuous pattern is inserted into the upper H bytes of the byte output data, and N-1 byte data in which a pseudo random signal is inserted in the remaining byte portion is output.

Since a continuous pattern of 0 or 1 is not inserted into the lowest output Rc (N) of the second latch shift circuit 29, it is output as it is.

On the other hand, the control circuit 35 performs control for outputting a pseudo-random signal, shifting, and synthesizing with a continuous pattern.

That is, when the byte length M set by the continuous pattern length setting means 23 is divisible by the output byte width N, the shift signal F is fixed at a low level, and the completion signal E2 is received from the continuous pattern generation unit 22. And then outputs a latch signal CK ′ synchronized with the clock signal CK,
An operation of outputting a pseudo-random signal having a required byte length with an N-byte width, outputting the completion signal E3 when the last pseudo-random signal is output, and stopping the output of the latch signal is repeated.

When the byte length M set by the continuous pattern length setting means 23 cannot be divided by the output byte width N, the shift signal F is set to the high level while the SOH data is being output, and the remainder is set. The latch signal CK 'is output by the number of times equal to B, and the data latched in the first latch shift circuit 26 and the second shift latch circuit 29 is shifted to the lower side by B bytes.

In this case, a composite signal Q for inserting 0 or 1 data generated by the continuous pattern generator 22 into the upper B bytes of the pseudo random signal of N bytes output first is output. .

FIG. 4 shows an example of the configuration of the control circuit 35. In FIG. 4, a setting circuit 36 calculates the number of times G of pseudo-random signal output and the number of shifts B (equal to the remainder) corresponding to the byte length M set by the continuous pattern length setting means 23, and outputs the output gate timer 37. And the shift gate timer 38.

The output gate timer 37 changes its output to a high level from the time when the completion signal E2 is received, and
When K has been input up to the output count G, the output is returned to a low level. The fall of the output gate timer 37 is output to the SOH data generator 21 as a completion signal E3.

The shift gate timer 38 changes its output to a high level when the output of the output gate timer 37 changes from a high level to a low level, and outputs the clock signal C.
When K is input up to the number of shifts H, the output is returned to a low level. The high level output of the shift gate timer 38 is used as the shift signal F as the first latch shift circuit 26,
To the latch shift circuit 29.

The outputs of the output date timer 37 and the shift gate timer 38 are input to an OR circuit 39. The output of the OR circuit 39 is supplied to the AND circuit 40 together with the clock signal CK.
And the clock signal CK input to the AND circuit 40 while the output of the OR circuit 39 is at the high level is output to the first latch shift circuit 26 and the second latch shift circuit 29 as the latch signal CK '. .

When the number of shifts B is not zero, the decoder 41 sets the upper B bits to 1,
An N-1 bit synthesized signal Q with the remaining bits set to 0 is output to the synthesizing circuit 40 for a time corresponding to one cycle of the clock signal CK from the time when the output of the output gate timer 37 goes high.

Next, the operation of the CID pattern generator 20 will be described on the assumption that N = K = 4. Each byte data of the 4-byte pseudo-random signal is represented by D. As shown in FIG. 5A, the 4-byte pseudo-random signal output at the end of the previous frame is represented by D (X + 1), D ( X +
2), D (X + 3) and D (X + 4).

Here, the byte length M set by the continuous pattern length setting means 23 is determined by the output byte width N (= 4).
Assuming that the remainder B obtained by dividing by 2 is 2, for example, when 4 bytes of SOH (1) to (4) are output in parallel at the beginning of the next frame, the second latch shift circuit of the pseudo-random signal generator 24 29 latch data [D (X + 1), D
(X + 2), D (X + 3), D (X + 4)] is shifted to the lower side by one byte, and as shown in FIG.
(X + 1), D (X + 2), D (X + 3)], and the latch data [D (X +
5), D (X + 6), D (X + 7), D (X + 8)]
Is shifted to the lower side by one byte, and as shown in FIG. 5C, [D (X + 4), D (X + 5), D (X + 6), D (X + 6)
(X + 7)].

Here, as the data *, the most significant data D (X +
5) is latched, but the N-byte data including this data * is meaningless data that is replaced by the data of the first latch shift circuit 26 when the pseudo random signal to be inserted into the next frame is output. Yes, all may be indicated by the symbol *, but here, only the byte data input from the upper side at the time of shifting is indicated by the symbol * so that the shift state can be easily understood.

Further, the next 4 bytes of SOH (5)-
When (8) is output, the latch data [*, D (X + 2), D (X +
3), D (X + 4)] is shifted to the lower side by one byte, and as shown in FIG. 5B, [*, *, D (X + 1),
D (X + 2)], and the latch data [D (X + 4), D (X + 5), D (X +
6), D (X + 7) is also shifted down by one byte,
As shown in FIG. 5C, [D (X + 3), D (X +
4), D (X + 5) and D (X + 6).

Thereafter, 36 bytes of SOH data are output, followed by a continuous pattern of 0 (or 1) in M-
Until B bytes are output, the state of the pseudo-random signal generator 24 does not change.

When the continuous pattern is output up to MB bytes and the output timing of the pseudo random signal is reached, the second latch shift circuit 29 supplies the latch data [D (X + 3) of the first latch shift circuit 26 to the second latch shift circuit 29. ), D (X +
4), D (X + 5), D (X + 6)] are latched, and the first latch shift circuit 26 latches the preceding latch data [D (X + 3), D (X + 4), D (X + 5), D (X + 5). X
+6)] and data [D (X + 7), D (X + 8), D]
(X + 9), D (X + 10)] are latched.

At this time, the upper two
Since a 4-bit composite signal Q whose bit is 1 and the remaining 0 are output for one clock cycle, the second latch shift circuit 2
9 [D (X + 3), D (X + 4), D (X
+5) and D (X + 6)], the combining circuit 40 inserts a continuous pattern of 0 (or 1) in place of the data D (X + 3) and D (X + 4) at the position of the upper 2 bytes.

Therefore, as shown in FIG.
The remaining two bytes of the continuous pattern and the data D that is continuous with the last pseudo random data D (X + 4) of the previous frame
With (X + 5) and D (X + 6), 4-byte combined data [0, 0, D (X + 5), D (X + 6)] is output.

Thereafter, the data D (X + 5), D (X
The pseudo random signal following +6) is output every 4 bytes.

The byte length M of the continuous pattern is N = 4.
In this case, the data is not shifted in the pseudo-random signal generator 24, and after a continuous pattern of M bytes is output with a 4-byte width, the pseudo-random signal following the previous frame is sequentially output with a 4-byte width. Will be done.

As described above, even when the length M of the continuous pattern of 0s or 1s is not an integral multiple of the output byte width N, the CID pattern generation device 20 of the embodiment allows the pseudo random signal generation unit 24 to output the SOH data. Is output while the data is shifted to the lower side by the remaining bytes, and a surplus continuous pattern is inserted into the first pseudo random signal output in the next frame and output.

Therefore, a continuous pattern having an arbitrary byte length can be inserted without impairing the continuity between frames of the pseudo-random signal.

As described above, the output byte width N is set to 4
In this case, if the clock signal CK is set to about 312 MHz that can be supported by the conventional device, the output bit rate is set to about 10 G
Hz.

In the above description of the operation, the output byte width N is set to 4. However, if the output byte width N is set to 8 (64 bits) or 16 (128 bits), the operation speed of each unit can be further reduced. it can. For example, if the frequency is 128 bits, the frequency of the clock signal CK is reduced to about 80
Hz, and large power consumption ECL
The circuit can be configured by a CMOS FPGA or ASIC instead of the element, so that the power consumption can be significantly reduced and the development period can be shortened.

[0071]

As described above, when the CID pattern generating apparatus of the present invention generates the CID pattern SDH signal, the length M of the continuous pattern of 0s or 1s inserted into the frame is determined by the output byte width N. When it is not an integral multiple of
Utilizing the period during which the SOH data is being output, the data of the first and second latch shift circuits of the pseudo random signal generation unit 24 are shifted to the lower side by the remaining bytes, and the first data to be output in the next frame is shifted. It is configured to insert a surplus continuous pattern into a pseudo-random signal and output the resulting signal.

For this reason, a CID pattern in which a continuous pattern of an arbitrary byte length is inserted can be output with a wider output byte width than before, without impairing the continuity between frames of the pseudo-random signal, and the bit rate can be significantly increased. Can be higher.

Further, the circuit can be constituted by a CMOS FPGA or ASIC, the power consumption can be greatly reduced, and the development period can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the embodiment.

FIG. 3 is a block diagram showing a configuration of a main part of the embodiment.

FIG. 4 is a block diagram showing a configuration of a main part of the embodiment.

FIG. 5 is a timing chart for explaining the operation of the embodiment;

FIG. 6 is a diagram showing an STM frame;

FIG. 7 shows a frame of a CID pattern.

FIG. 8 is a block diagram showing the configuration of a conventional device.

FIG. 9 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

 Reference Signs List 20 CID pattern generator 21 SOH data generator 22 continuous pattern generator 23 continuous pattern length setting means 24 pseudo-random signal generator 25 logical operation circuit 26 first latch shift circuit 27 selector 28 latch circuit 29 second latch shift circuit Reference Signs List 30 selector 31 latch circuit 32 synthesis circuit 33 selector 35 control circuit 36 setting circuit 37 output gate timer 38 shift gate timer 39 OR circuit 40 AND circuit 41 decoder

────────────────────────────────────────────────── ─── Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 5/22-5/26 H04L 7/00 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A U × N bytes (U is a multiple of 9) parallel to either synchronously N bytes wide and SOH data with a predetermined clock signal (N is the number represented by 2 ^P for integer P) S to output
An OH data generator (21); and a continuous pattern length setting means (2) for arbitrarily setting a byte length M of a continuous pattern in which 0s or 1s are continuous within a predetermined range.
3) and following the SOH data output from the SOH data generator, dividing the continuous pattern of N byte width by the byte length M set by the continuous pattern length setting means by the output byte width N Of the continuous pattern generator (2)
2) and, following the continuous pattern output from the continuous pattern generation unit, a pseudo random signal generation unit (2) that outputs a pseudo random signal in an N-byte width in synchronization with the clock signal.
4) generating a CID pattern having a width of N bytes, wherein one frame is composed of the SOH data, the M-byte continuous pattern following the SOH data, and the pseudo random signal following the continuous pattern. A logic operation circuit (25) for performing an exclusive OR operation on N-byte parallel input data to generate an N-byte parallel pseudo-random signal; It is configured to be able to latch byte-parallel data and shift the latched data to the lower side in units of 1 byte, and each time the N-byte parallel pseudo-random signal generated by the logical operation circuit is received a latch signal. A first latch shift circuit for latching and inputting the latched data to the logical operation circuit to generate a next-stage pseudo-random signal (26), an N-byte parallel data latch, and a shift of the latched data to the lower side in units of 1 byte are possible, and the least significant 1-byte data is stored in the first latch shift circuit. A second latch shift circuit (29) that is connected so as to be able to shift input from the most significant side, and that latches the N-byte pseudo random signal latched by the first latch shift circuit each time the latch signal is received. A synthesizing circuit (32) which replaces the N-byte data latched by the second latch shift circuit with data of an arbitrary upper byte of the data by the same data as the continuous pattern generated by the continuous pattern generator, and outputs the result. ), While the SOH data and the continuous pattern are being output, the second pseudo random signal generated by the logical operation circuit is not generated. When the latch operation of the second latch shift circuit is stopped and a byte length M that cannot be divided by the output byte width N is set by the continuous pattern length setting means, the number of bytes equal to the remainder B is The latch data of the first and second latch shift circuits are shifted, and a latch signal synchronized with the clock signal is output from the continuous pattern being output A times until the SOH data is output. A new pseudo-random signal generated by the logical operation circuit by being applied to first and second latch shift circuits is sequentially output to the synthesizing circuit, and is first latched by the second latch shift circuit and is output to the synthesizing circuit. The same data as the continuous pattern is inserted into the upper byte equal to the remainder B in the N-byte pseudo random signal output to CID pattern generating apparatus characterized by being constituted by a control circuit (35) for outputting Te.