JP3769128B2 - Wire bonding method to pattern wiring of semiconductor device - Google Patents

Wire bonding method to pattern wiring of semiconductor device Download PDF

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Publication number
JP3769128B2
JP3769128B2 JP23869298A JP23869298A JP3769128B2 JP 3769128 B2 JP3769128 B2 JP 3769128B2 JP 23869298 A JP23869298 A JP 23869298A JP 23869298 A JP23869298 A JP 23869298A JP 3769128 B2 JP3769128 B2 JP 3769128B2
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pad
semiconductor device
probe
pattern wiring
circuit
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JP2000068320A (en
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整 久留須
裕之 星
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置、特に半導体装置の電極パッドの構成に関する。
【０００２】
【従来の技術】
図８は、従来の高周波装置で使用される半導体装置１００の機能ブロック図である。半導体装置１００は、高周波信号の入力用のＲＦ入力パッド１０１、ＲＦ入力パッド１０１より入力された高周波信号を処理するＲＦ回路１０２、電源電圧Ｖｃｃの入力用のＤＣパッド１０３、複数のトランジスタで構成されるトランジスタ回路１０５、上記ＤＣパッド１０３より入力される電源電圧Ｖｃｃに対して降圧等の処理を施し、処理後の電源電圧Ｖｃｃを上記トランジスタ回路１０５の各トランジスタのゲートに印加するＤＣ回路１０４、トランジスタ回路１０５から出力される信号に対して所定の処理を施して高周波信号を出力するＲＦ回路１０６、及び、ＲＦ回路１０６より出力される高周波信号の出力用のＲＦ出力パッド１０７で構成される。
【０００３】
上記構成の半導体装置１００は、樹脂封止される前に、テスト装置によって特性テストや動作テストが行われる。上記特性テストや動作テストでは、電源供給用のＤＣパッド１０３や高周波信号の入力用のＲＦ入力パッド１０１に、テスト装置のプローブを接触させ、該プローブより駆動電圧やテストパターン信号等を入力し、対応する電極パッド（例えばＲＦ出力パッド１０７）より検出される電流、電圧又は信号を調べる。
【０００４】
【発明が解決しようとする課題】
図９は、上記半導体装置１００が備えるＲＦ入力パッド１０１、ＤＣパッド１０３、又は、ＲＦ出力パッド１０７に対して、テスト装置１３１のプローブ１３０を接触させた状態を示す図である。テスト装置１３１のプローブ１３０に静電気が帯電していると、該プローブ１３０をＲＦ入力パッド１０１、ＤＣパッド１０３、又は、ＲＦ出力パッド１０７に接触させた瞬間に、半導体装置内の回路に大きな電圧が印加され、トランジスタ等の回路素子が破壊されることがある。
上記の現象は、半導体装置１００をリードフレームにワイヤボンディングする際に、ボンディング装置のキャピラリに静電気が帯電していた場合にも生じる。
【０００５】
本発明の目的は、テスト装置のプローブやボンディング装置のプローブに静電気が帯電している場合であっても、内部の回路に静電気が流れ込むことを防止することのできる構成の電極パッドを備える半導体装置を提供することである。
【０００６】
【課題を解決するための手段】
請求項１に記載の半導体装置のパターン配線へのワイヤボンディング方法は、基板上に、Ａｕで形成されている１以上の電極パッドを備えており、１以上の電極パッドの各々が、パッド部と、該パッド部に接続され、基板上のパターン配線を所定の間隙を保持しつつまたぐエアーブリッジ構成のエアーブリッジ部と、で構成されている、半導体装置のＡｕで形成されているパターン配線へのワイヤボンディング方法であって、他端の接地されたプローブを、１以上の電極パッドの内の１つの電極パッドのパッド部に接触させるステップと、先端から、先端にＡｕボールを有しているＡｕワイヤを出す、ボンディング装置のキャピラリの先端を、プローブを接触させているパッド部を有している電極パッドのエアーブリッジ部に接触させるステップと、キャピラリの先端を基板側に押さえ付けることにより、Ａｕボールと、エアーブリッジ部と、パターン配線と、を接触させ、且つ、溶接するステップと、Ａｕワイヤを出しつつ、キャピラリを基板から引き離すステップと、プローブを、接触させているパッド部から引き離すステップと、からなることを特徴とする。
【００１０】
【発明の実施の形態】
（１）実施の形態１
以下、実施の形態１にかかる半導体装置１の構成について説明する。
図１は、実施の形態１にかかる半導体装置１の機能ブロック図である。半導体装置１は、高周波信号の入力用のＲＦ入力パッド２、該ＲＦ入力パッド２より入力された高周波信号を処理するＲＦ回路３、電源電圧Ｖｃｃの入力用のＤＣパッド４、複数のトランジスタで構成されるトランジスタ回路６、上記ＤＣパッド４より入力される電源電圧Ｖｃｃに対して降圧等の処理を施し、処理後の電源電圧Ｖｃｃを上記トランジスタ回路６の各トランジスタのゲートに印加するＤＣ回路５、トランジスタ回路６から出力される信号に対して所定の処理を施して高周波信号を出力するＲＦ回路７、及び、ＲＦ回路７より出力された高周波信号の出力用のＲＦ出力パッド８で構成される。
【００１１】
図２は、半導体装置１の備えるＤＣパッド４の構成を示す図である。なお、ＲＦ入力パッド２、及び、ＲＦ出力パッド８も同じ構成である。
図２の（ａ）は、基板１０上に設けられるＤＣパッド４の斜視図であり、図２の（ｂ）は、（ａ）に示すＤＣパッド４のａ−ａ’断面図である。
図２の（ａ）に示すように、ＤＣパッド４は、ＤＣ回路５に接続されているパターン配線２１上を所定の間隙を保持しつつまたぐエアーブリッジ構成のエアーブリッジ部２３、及び、パッド部２２からなる。なお、ＤＣパッド４及びパターン配線２１の素材には、金（Ａｕ）を用いる。
【００１２】
図２の（ｂ）に示すパターン配線２１の厚みｂは、約５００Åであり、ＤＣパッド４（エアーブリッジ部２３及びパッド部２２）の厚みｃは、約２μｍであり、該パターン配線２１とエアーブリッジ部２３との間隔ｄは、約１０〜２０μｍである。
【００１３】
以下、図３及び図４を参照しつつ、上記構成のＤＣパッド４に対して、外部処理装置の導電性部材を接触させる方法の一例として、テスト装置のプローブを接触させる方法について説明する。
（ステップ１）図３に示すように、他端の接地されたプローブ３２をパッド部２２に接触させる。
（ステップ２）テスト装置３１に他端が接続され、ＤＣパッド４にテスト用の電源電圧Ｖｃｃを印加するプローブ３０をエアーブリッジ部２３に接触させる。これにより、プローブ３０に帯電していた静電気がプローブ３２を介して放電される。
（ステップ３）プローブ３０を基板１０側に押し付け、図４に示すように、エアーブリッジ部２３をパターン配線２１に接触させる。これにより、プローブ３０とパターン配線２１とが電気的に接続される。
（ステップ４）プローブ３２をパッド部２２より離す。
以上のステップ１〜ステップ４の手順を実行することで、プローブ３０に帯電していた静電気を完全に放電した後に、ＤＣ回路５に接続されているパターン配線２１に接触させることができる。これにより、プローブ３０に帯電していた静電気によって、ＤＣ回路５やトランジスタ回路６内のトランジスタが破壊されるのを防止することができる。
【００１４】
なお、テスト装置３１に接続されるプローブ３０から、テスト用の電源電圧Ｖｃｃの出力を開始した後に、プローブ３２をパッド部２２から引き離すようにしても良い。この場合、テスト装置３１より出力されるテスト用の電源電圧Ｖｃｃのサージ電圧が、半導体装置の回路内に印加されることを防止することができる。
【００１５】
次に、図５及び図６を参照しつつ、上記構成のＤＣパッド４をワイヤボンディングする場合の方法について説明する。
（ステップ１０） 図５に示すように、他端の接地されたプローブ３２をパッド部２２に接触させる。
（ステップ１１） ボンディング装置のキャピラリ４０をエアーブリッジ部２３に接触させる。これにより、キャピラリ４０に帯電していた静電気がプローブ３２を介して放電される。
（ステップ１２） キャピラリ４０を基板１０側に押し下げ、図６の（ａ）に示すように、エアーブリッジ部２３をパターン配線２１に接触させる。キャピラリ４０の先端のＡｕボール４１に熱又は超音波振動を与え、該Ａｕボール４１、エアーブリッジ部２３及びパターン配線２１を溶接する。
（ステップ１３） 図６の（ｂ）に示すように、キャピラリ４０を上に引き上げ、接続するピン（リードフレーム）の方向へ移動させる。Ａｕボール４１はエアーブリッジ部２３に接続されているため、キャピラリ４０の移動に伴いボンディング装置４２内部からＡｕライン４３が引き出される。
（ステップ１４） プローブ３２をパッド部２２より引き離す。
以上のステップ１０〜ステップ１４を実行することで、キャピラリ４０に帯電していた静電気を完全に放電した後に、キャピラリ４０をＤＣ回路５に接続されているパターン配線２１に接触させることができる。これにより、キャピラリ４０に帯電していた静電気が、ＤＣ回路５やトランジスタ回路６を構成するトランジスタ等の回路素子に流れ込み、該回路素子が破壊されることを防止することができる。
【００１６】
（２）実施の形態２
以下、実施の形態２にかかる半導体装置４５の構成について説明する。
半導体装置４５の機能ブロックの構成は、上記実施の形態１にかかる半導体装置１と同じである。半導体装置４５は、半導体装置１とＲＦ入力パッド２、ＤＣパッド、及び、ＲＦ出力パッド８の構成が異なる。
以下、半導体装置４５のＤＣパッド４の構成を説明する。なお、半導体装置４５におけるＲＦ入力パッド２、ＤＣパッド、及び、ＲＦ出力パッド８の構成は、同じである。
【００１７】
図７は、半導体装置４５のＤＣパッド４の構成を示す斜視図である。ＤＣパッド４は、ＤＣ回路５に接続されるパターン配線２１と電気的に接続された状態で設けられた平面のパッド部５１と、基板５０の裏面のＧＮＤ端子に接続されるバイアホールを持つアース端子５３と、パッド部５１及びアース端子５３を電気的に接続する抵抗であって、レーザにより切断可能な抵抗５４より構成される。
【００１８】
以下、上記構成のＤＣパッドをワイヤボンディングする方法について説明する。
（ステップ２０） キャピラリ４０の先端に位置するＡｕボール４１をパッド部５１に接触させる。パッド部４１は、予めアース端子５３に接続されているため、キャピラリ４０に帯電していた静電気は、全てアース端子５３に放電される。
（ステップ２１） キャピラリ４０の先端のＡｕボール４１に熱又は超音波振動を与え、該Ａｕボール４１とパッド部５１を溶接する。
（ステップ２２） キャピラリ４０を引き上げた後、接続するピンの方向へ移動させる。この際、Ａｕボール４１はパッド部５１に接続されているため、ボンディング装置４２内部からＡｕライン４３が引き出される。
（ステップ２３） ワイヤボンディングの終了後、抵抗５４をレーザにより切断する。
以上のステップ２０〜ステップ２３を実行することで、ワイヤボンディングを行う際にキャピラリ４０に帯電していた静電気が半導体装置の内部回路に流れ込むことを防止することができる。これにより、キャピラリ４０に帯電していた静電気によって、ＤＣ回路５やトランジスタ回路６内のトランジスタ等の回路素子が破壊されることを防止することができる。
【００１９】
【発明の効果】
請求項１記載の半導体装置のパターン配線へのワイヤボンディング方法によれば、キャピラリを完全に除電してから、パターン配線へのワイヤボンディングを行うことで、ワイヤボンディングに伴う静電破壊を防止することができる。
【図面の簡単な説明】
【図１】 実施の形態１にかかる半導体装置の機能ブロック図である。
【図２】 実施の形態１にかかる電極パッドの構成を示す図である。
【図３】 実施の形態１にかかる半導体装置をテスト装置によりテストする場合の実施状態を示す図である。
【図４】 実施の形態１にかかる半導体装置のテスト実施状態を示す断面図である。
【図５】 実施の形態１にかかる半導体装置にワイヤボンディングを施す際の状態を示す図である。
【図６】 実施の形態１にかかる半導体装置へのワイヤボンディング実行時における断面図である。
【図７】 実施の形態２にかかる半導体装置にワイヤボンディングを施す際の状態を示す図である。
【図８】 従来の高周波回路用の半導体装置の構成を示す図である。
【図９】 従来の半導体装置の備えるパッドを用いたテスト装置によるテスト実行時の様子を示す図である。
【符号の説明】
１，４５，１００ 半導体装置、２，１０１ ＲＦ入力パッド、３，１０２ ＲＦ回路、４，１０３ ＤＣパッド、５，１０４ ＤＣ回路、６，１０５ トランジスタ回路、７，１０６ ＲＦ回路、８，１０７ ＲＦ出力パッド、２１ パターン配線、２２，５１ パッド部、２３ エアーブリッジ部、３０，３２，１３０ プローブ、３１，１３１ テスト装置、４０ キャピラリ、４１ Ａｕボール、５３ アース端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a configuration of an electrode pad of the semiconductor device.
[0002]
[Prior art]
FIG. 8 is a functional block diagram of a semiconductor device 100 used in a conventional high-frequency device. The semiconductor device 100 includes an RF input pad 101 for inputting a high-frequency signal, an RF circuit 102 for processing a high-frequency signal input from the RF input pad 101, a DC pad 103 for inputting a power supply voltage Vcc, and a plurality of transistors. Transistor circuit 105, a DC circuit 104 for applying a process such as a step-down to the power supply voltage Vcc inputted from the DC pad 103, and applying the processed power supply voltage Vcc to the gate of each transistor of the transistor circuit 105, a transistor An RF circuit 106 that performs predetermined processing on the signal output from the circuit 105 and outputs a high-frequency signal, and an RF output pad 107 for outputting the high-frequency signal output from the RF circuit 106 are configured.
[0003]
The semiconductor device 100 having the above configuration is subjected to a characteristic test and an operation test by a test apparatus before being sealed with resin. In the characteristic test and the operation test, the probe of the test apparatus is brought into contact with the DC pad 103 for supplying power and the RF input pad 101 for inputting a high-frequency signal, and a drive voltage, a test pattern signal, and the like are input from the probe. The current, voltage or signal detected from the corresponding electrode pad (eg, RF output pad 107) is examined.
[0004]
[Problems to be solved by the invention]
FIG. 9 is a diagram illustrating a state in which the probe 130 of the test apparatus 131 is in contact with the RF input pad 101, the DC pad 103, or the RF output pad 107 included in the semiconductor device 100. If the probe 130 of the test apparatus 131 is charged with static electricity, a large voltage is applied to the circuit in the semiconductor device at the moment when the probe 130 is brought into contact with the RF input pad 101, the DC pad 103, or the RF output pad 107. When applied, circuit elements such as transistors may be destroyed.
The above phenomenon also occurs when static electricity is charged in the capillary of the bonding apparatus when wire bonding the semiconductor device 100 to the lead frame.
[0005]
An object of the present invention is to provide a semiconductor device including an electrode pad having a configuration capable of preventing static electricity from flowing into an internal circuit even when static electricity is charged in a probe of a test apparatus or a probe of a bonding apparatus. Is to provide.
[0006]
[Means for Solving the Problems]
The wire bonding method to the pattern wiring of the semiconductor device according to claim 1 includes one or more electrode pads formed of Au on a substrate, and each of the one or more electrode pads includes a pad portion and And an air bridge portion of an air bridge configuration connected to the pad portion and straddling the pattern wiring on the substrate while maintaining a predetermined gap, to the pattern wiring formed of Au of the semiconductor device A wire bonding method comprising: contacting a grounded probe at the other end with a pad portion of one electrode pad of one or more electrode pads; and Au having an Au ball from the tip to the tip A step for bringing the tip of the capillary of the bonding apparatus that brings out the wire into contact with the air bridge portion of the electrode pad having the pad portion that is in contact with the probe. And pressing the tip of the capillary to the substrate side to bring the Au ball, the air bridge portion, and the pattern wiring into contact with each other and welding, and pulling the capillary away from the substrate while pulling out the Au wire And a step of pulling the probe away from the contacting pad portion.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
(1) Embodiment 1
The configuration of the semiconductor device 1 according to the first embodiment will be described below.
FIG. 1 is a functional block diagram of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes an RF input pad 2 for inputting a high-frequency signal, an RF circuit 3 for processing a high-frequency signal input from the RF input pad 2, a DC pad 4 for inputting a power supply voltage Vcc, and a plurality of transistors. A DC circuit 5 that applies a process such as step-down to the power supply voltage Vcc input from the DC pad 4 and applies the processed power supply voltage Vcc to the gate of each transistor of the transistor circuit 6; An RF circuit 7 that performs a predetermined process on the signal output from the transistor circuit 6 and outputs a high-frequency signal, and an RF output pad 8 for outputting the high-frequency signal output from the RF circuit 7 are configured.
[0011]
FIG. 2 is a diagram illustrating a configuration of the DC pad 4 included in the semiconductor device 1. The RF input pad 2 and the RF output pad 8 have the same configuration.
2A is a perspective view of the DC pad 4 provided on the substrate 10, and FIG. 2B is a cross-sectional view taken along the line aa ′ of the DC pad 4 shown in FIG.
As shown in FIG. 2A, the DC pad 4 includes an air bridge portion 23 having an air bridge configuration that straddles the pattern wiring 21 connected to the DC circuit 5 while maintaining a predetermined gap, and a pad portion. 22. Note that gold (Au) is used as a material for the DC pad 4 and the pattern wiring 21.
[0012]
The thickness b of the pattern wiring 21 shown in FIG. 2B is about 500 mm, and the thickness c of the DC pad 4 (the air bridge portion 23 and the pad portion 22) is about 2 μm. The distance d with the bridge portion 23 is about 10 to 20 μm.
[0013]
Hereinafter, as an example of a method of bringing the conductive member of the external processing apparatus into contact with the DC pad 4 having the above configuration, a method of bringing the probe of the test apparatus into contact will be described with reference to FIGS. 3 and 4.
(Step 1) As shown in FIG. 3, the grounded probe 32 at the other end is brought into contact with the pad portion 22.
(Step 2) The other end is connected to the test apparatus 31 and the probe 30 that applies the test power supply voltage Vcc to the DC pad 4 is brought into contact with the air bridge portion 23. Thereby, the static electricity charged in the probe 30 is discharged via the probe 32.
(Step 3) The probe 30 is pressed against the substrate 10 side, and the air bridge portion 23 is brought into contact with the pattern wiring 21 as shown in FIG. Thereby, the probe 30 and the pattern wiring 21 are electrically connected.
(Step 4) The probe 32 is separated from the pad portion 22.
By executing the procedure from Step 1 to Step 4 described above, the static electricity charged in the probe 30 can be completely discharged and then brought into contact with the pattern wiring 21 connected to the DC circuit 5. Thereby, it is possible to prevent the transistors in the DC circuit 5 and the transistor circuit 6 from being destroyed by static electricity charged in the probe 30.
[0014]
The probe 32 may be separated from the pad portion 22 after the output of the test power supply voltage Vcc is started from the probe 30 connected to the test apparatus 31. In this case, the surge voltage of the test power supply voltage Vcc output from the test device 31 can be prevented from being applied to the circuit of the semiconductor device.
[0015]
Next, a method for wire bonding the DC pad 4 having the above configuration will be described with reference to FIGS.
(Step 10) As shown in FIG. 5, the grounded probe 32 at the other end is brought into contact with the pad portion 22.
(Step 11) The capillary 40 of the bonding apparatus is brought into contact with the air bridge portion 23. Thereby, the static electricity charged in the capillary 40 is discharged via the probe 32.
(Step 12) The capillary 40 is pushed down to the substrate 10 side, and the air bridge portion 23 is brought into contact with the pattern wiring 21 as shown in FIG. Heat or ultrasonic vibration is applied to the Au ball 41 at the tip of the capillary 40, and the Au ball 41, the air bridge portion 23, and the pattern wiring 21 are welded.
(Step 13) As shown in FIG. 6B, the capillary 40 is pulled up and moved in the direction of the pin (lead frame) to be connected. Since the Au ball 41 is connected to the air bridge portion 23, the Au line 43 is drawn from the inside of the bonding apparatus 42 as the capillary 40 moves.
(Step 14) The probe 32 is pulled away from the pad portion 22.
By executing the above steps 10 to 14, the capillary 40 can be brought into contact with the pattern wiring 21 connected to the DC circuit 5 after the static electricity charged in the capillary 40 is completely discharged. Thereby, it is possible to prevent static electricity charged in the capillary 40 from flowing into circuit elements such as transistors constituting the DC circuit 5 and the transistor circuit 6 and destroying the circuit elements.
[0016]
(2) Embodiment 2
The configuration of the semiconductor device 45 according to the second embodiment will be described below.
The functional block configuration of the semiconductor device 45 is the same as that of the semiconductor device 1 according to the first embodiment. The semiconductor device 45 is different from the semiconductor device 1 in the configuration of the RF input pad 2, the DC pad, and the RF output pad 8.
Hereinafter, the configuration of the DC pad 4 of the semiconductor device 45 will be described. Note that the configurations of the RF input pad 2, the DC pad, and the RF output pad 8 in the semiconductor device 45 are the same.
[0017]
FIG. 7 is a perspective view showing the configuration of the DC pad 4 of the semiconductor device 45. The DC pad 4 is a ground having a planar pad portion 51 provided in a state of being electrically connected to the pattern wiring 21 connected to the DC circuit 5 and a via hole connected to the GND terminal on the back surface of the substrate 50. The terminal 53 is a resistor that electrically connects the pad portion 51 and the ground terminal 53, and includes a resistor 54 that can be cut by a laser.
[0018]
Hereinafter, a method of wire bonding the DC pad having the above configuration will be described.
(Step 20) The Au ball 41 located at the tip of the capillary 40 is brought into contact with the pad portion 51. Since the pad portion 41 is connected to the ground terminal 53 in advance, all static electricity charged in the capillary 40 is discharged to the ground terminal 53.
(Step 21) Heat or ultrasonic vibration is applied to the Au ball 41 at the tip of the capillary 40, and the Au ball 41 and the pad portion 51 are welded.
(Step 22) After pulling up the capillary 40, it is moved in the direction of the pin to be connected. At this time, since the Au ball 41 is connected to the pad portion 51, the Au line 43 is drawn from the inside of the bonding apparatus 42.
(Step 23) After the wire bonding is completed, the resistor 54 is cut by a laser.
By executing the above steps 20 to 23, it is possible to prevent static electricity charged in the capillary 40 during wire bonding from flowing into the internal circuit of the semiconductor device. Thereby, it is possible to prevent circuit elements such as the transistors in the DC circuit 5 and the transistor circuit 6 from being destroyed by static electricity charged in the capillary 40.
[0019]
【The invention's effect】
According to the wire bonding method to the pattern wiring of the semiconductor device according to claim 1, the electrostatic breakdown accompanying the wire bonding can be prevented by performing the wire bonding to the pattern wiring after the capillary is completely discharged. Can do.
[Brief description of the drawings]
1 is a functional block diagram of a semiconductor device according to a first embodiment;
FIG. 2 is a diagram showing a configuration of an electrode pad according to the first exemplary embodiment.
FIG. 3 is a diagram showing an implementation state when the semiconductor device according to the first embodiment is tested by a test apparatus;
FIG. 4 is a sectional view showing a test execution state of the semiconductor device according to the first embodiment;
FIG. 5 is a diagram showing a state when wire bonding is performed on the semiconductor device according to the first embodiment;
FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment when wire bonding is performed;
FIG. 7 is a diagram illustrating a state when wire bonding is performed on the semiconductor device according to the second embodiment;
FIG. 8 is a diagram showing a configuration of a conventional semiconductor device for a high-frequency circuit.
FIG. 9 is a diagram illustrating a state when a test is performed by a test apparatus using a pad included in a conventional semiconductor device.
[Explanation of symbols]
1,45,100 Semiconductor device, 2,101 RF input pad, 3,102 RF circuit, 4,103 DC pad, 5,104 DC circuit, 6,105 transistor circuit, 7,106 RF circuit, 8,107 RF output Pad, 21 Pattern wiring, 22, 51 Pad part, 23 Air bridge part, 30, 32, 130 Probe, 31, 131 Test device, 40 Capillary, 41 Au ball, 53 Ground terminal

Claims (1)

基板上に、Ａｕで形成されている１以上の電極パッドを備えており、１以上の電極パッドの各々が、パッド部と、該パッド部に接続され、基板上のパターン配線を所定の間隙を保持しつつまたぐエアーブリッジ構成のエアーブリッジ部と、で構成されている、半導体装置のＡｕで形成されているパターン配線へのワイヤボンディング方法であって、One or more electrode pads formed of Au are provided on the substrate, and each of the one or more electrode pads is connected to the pad portion and the pad portion, and the pattern wiring on the substrate is arranged with a predetermined gap. A wire bonding method to a pattern wiring formed of Au of a semiconductor device, comprising an air bridge portion of an air bridge configuration that straddles while holding,
他端の接地されたプローブを、１以上の電極パッドの内の１つの電極パッドのパッド部に接触させるステップと、Contacting the grounded probe at the other end with the pad portion of one of the one or more electrode pads;
先端から、先端にＡｕボールを有しているＡｕワイヤを出す、ボンディング装置のキャピラリの先端を、プローブを接触させているパッド部を有している電極パッドのエアーブリッジ部に接触させるステップと、A step of bringing out an Au wire having an Au ball from the tip, and bringing the tip of the capillary of the bonding apparatus into contact with an air bridge portion of an electrode pad having a pad portion in contact with a probe;
キャピラリの先端を基板側に押さえ付けることにより、Ａｕボールと、エアーブリッジ部と、パターン配線と、を接触させ、且つ、溶接するステップと、A step of contacting and welding the Au ball, the air bridge portion, and the pattern wiring by pressing the tip of the capillary against the substrate side;
Ａｕワイヤを出しつつ、キャピラリを基板から引き離すステップと、Pulling the capillary away from the substrate while pulling out the Au wire;
プローブを、接触させているパッド部から引き離すステップと、からなることを特徴とする、半導体装置のパターン配線へのワイヤボンディング方法。A method of wire bonding to a pattern wiring of a semiconductor device, comprising: a step of pulling a probe away from a pad portion in contact with the probe.
JP23869298A 1998-08-25 1998-08-25 Wire bonding method to pattern wiring of semiconductor device Expired - Fee Related JP3769128B2 (en)

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