JP2020159995A - Semiconductor device, method for manufacturing semiconductor device, and method for inspecting semiconductor device - Google Patents

Semiconductor device, method for manufacturing semiconductor device, and method for inspecting semiconductor device Download PDF

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JP2020159995A
JP2020159995A JP2019062437A JP2019062437A JP2020159995A JP 2020159995 A JP2020159995 A JP 2020159995A JP 2019062437 A JP2019062437 A JP 2019062437A JP 2019062437 A JP2019062437 A JP 2019062437A JP 2020159995 A JP2020159995 A JP 2020159995A
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semiconductor chip
semiconductor device
wire
substrate
semiconductor
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由香 尾土井
Yuka Odoi
由香 尾土井
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Mitsubishi Electric Corp
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Abstract

To provide a semiconductor device which can analyze electric characteristics of a semiconductor chip and specify a part of a failure, a method for manufacturing the semiconductor device, and a method for inspecting a semiconductor device.SOLUTION: The semiconductor device is formed of a substrate; a first joint unit and a second joint unit formed on the substrate; a first semiconductor chip and a second semiconductor chip equipped on the first joint unit and the second join unit, respectively, the first and second semiconductor chips each having an electrode in the back surface and the electrode being connected to the substrate; a first wire connected to a pattern at both end parts of the wire, the pattern being formed in the surface of each of the semiconductor chip and the second semiconductor chip; and a sealing unit covering a part of the substrate, the first joint unit, the second joint unit, the first semiconductor chip, and the second semiconductor chip, and a part of the first wire, the sealing unit exposing the top of the first wire.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置、半導体装置の製造方法、及び半導体装置の検査方法に関する。 The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a method for inspecting a semiconductor device.

半導体チップの故障解析は、例えば半導体装置を開封し、半導体装置に搭載されている半導体チップの電気特性を解析することによって行われる。
半導体装置を開封する方法として、半導体装置を封止している封止剤、例えばエポキシ樹脂に薬液を滴下し開封する技術（例えば、特許文献１参照）、ヒートシンク、リードフレーム等を物理研磨及び薬液によって開封する技術（例えば、特許文献２参照）が開示されている。 Failure analysis of a semiconductor chip is performed, for example, by opening a semiconductor device and analyzing the electrical characteristics of the semiconductor chip mounted on the semiconductor device.
As a method for opening a semiconductor device, a technique for dropping a chemical solution onto a sealing agent that seals the semiconductor device, for example, an epoxy resin (see, for example, Patent Document 1), a heat sink, a lead frame, etc. (See, for example, Patent Document 2) for opening the package is disclosed.

特開平６−０６１２８６号公報Japanese Unexamined Patent Publication No. 6-061286 特開２００４−２０５４４０号公報Japanese Unexamined Patent Publication No. 2004-205440

しかしながら、特許文献１に記載された技術では、故障の原因が半導体チップ表面の異物である場合、薬液による半導体装置の開封とともに異物も除去してしまうおそれがあり、半導体チップの故障を再現できないという課題があった。また、特許文献２に記載された技術では、物理研磨によって半導体チップの裏面を研磨するため、半導体チップにダメージを与えてしまうおそれがあり、本来の故障とは異なる故障が発生する可能性があった。 However, in the technique described in Patent Document 1, if the cause of the failure is a foreign substance on the surface of the semiconductor chip, the foreign substance may be removed when the semiconductor device is opened with a chemical solution, and the failure of the semiconductor chip cannot be reproduced. There was a challenge. Further, in the technique described in Patent Document 2, since the back surface of the semiconductor chip is polished by physical polishing, the semiconductor chip may be damaged, and a failure different from the original failure may occur. It was.

本発明は、上述の課題を解決するためになされたもので、半導体チップの電気特性を解析し、故障箇所の特定ができる半導体装置、半導体装置の製造方法、及び半導体装置の検査方法を提供することを目的とする。 The present invention has been made to solve the above-mentioned problems, and provides a semiconductor device capable of analyzing the electrical characteristics of a semiconductor chip and identifying a failure location, a method for manufacturing the semiconductor device, and a method for inspecting the semiconductor device. The purpose is.

本発明にかかる半導体装置は、基板と、前記基板上に形成された第１の接合部及び第２の接合部と、前記第１の接合部及び前記第２の接合部上にそれぞれ搭載されるとともに、裏面に形成された電極と前記基板とが接続された第１の半導体チップ及び第２の半導体チップと、前記第１の半導体チップ及び前記第２の半導体チップのそれぞれの表面に形成されたパターンに両端部がそれぞれ接続された第１のワイヤと、前記基板の一部、前記第１の接合部、前記第２の接合部、前記第１の半導体チップ、前記第２の半導体チップ、及び前記第１のワイヤの一部を覆うとともに、前記第１のワイヤの頂部を露出させた封止部とを備えたものである。 The semiconductor device according to the present invention is mounted on a substrate, a first joint portion and a second joint portion formed on the substrate, and the first joint portion and the second joint portion, respectively. At the same time, the first semiconductor chip and the second semiconductor chip in which the electrodes formed on the back surface and the substrate are connected, and the first semiconductor chip and the second semiconductor chip are formed on the respective surfaces. A first wire having both ends connected to the pattern, a part of the substrate, the first joint, the second joint, the first semiconductor chip, the second semiconductor chip, and It is provided with a sealing portion that covers a part of the first wire and exposes the top of the first wire.

本発明にかかる半導体装置の製造方法は、基板上に第１の接合部材及び第２の接合部材を配置する接合部材配置工程と、配置された前記第１の接合部材及び前記第２の接合部材上にそれぞれ第１の半導体チップ及び第２の半導体チップを搭載する半導体チップ搭載工程と、前記第１の半導体チップ及び前記第２の半導体チップが搭載された前記第１の接合部材及び前記第２の接合部材を硬化させ、それぞれ第１の接合部及び第２の接合部を形成する接合部形成工程と、前記第１の半導体チップ及び前記第２の半導体チップの表面に形成されたパターンと第１のワイヤの両端部とをそれぞれ接続するボンディング工程と、前記基板の一部、前記第１の接合部、前記第２の接合部、前記第１の半導体チップ、前記第２の半導体チップ、及び前記第１のワイヤの一部を覆うように封止部材を注入する封止部材注入工程と、注入した前記封止部材を硬化させ、前記頂部を露出させた封止部を形成する封止部形成工程とを備えたものである。 The method for manufacturing a semiconductor device according to the present invention includes a joining member arranging step of arranging a first joining member and a second joining member on a substrate, and the arranged first joining member and the second joining member. The semiconductor chip mounting process in which the first semiconductor chip and the second semiconductor chip are mounted on the top, the first bonding member on which the first semiconductor chip and the second semiconductor chip are mounted, and the second A joint portion forming step of curing the joint member of No. 1 to form a first joint portion and a second joint portion, respectively, and a pattern formed on the surfaces of the first semiconductor chip and the second semiconductor chip and a second. A bonding step for connecting both ends of the wire 1 and a part of the substrate, the first junction, the second junction, the first semiconductor chip, the second semiconductor chip, and A sealing member injection step of injecting a sealing member so as to cover a part of the first wire, and a sealing portion that cures the injected sealing member to form a sealing portion with the top exposed. It is equipped with a forming process.

本発明にかかる半導体装置の検査方法は、本発明の半導体装置の前記頂部を切断する工程と、切断された前記頂部の一方の先端にプローブを接触させ電圧を印加する工程とを備えたものである。 The method for inspecting a semiconductor device according to the present invention includes a step of cutting the top of the semiconductor device of the present invention and a step of bringing a probe into contact with one tip of the cut top and applying a voltage. is there.

本発明によれば、半導体チップの電気特性を解析し、故障箇所の特定ができる。 According to the present invention, it is possible to analyze the electrical characteristics of the semiconductor chip and identify the faulty part.

本発明の実施の形態１にかかる半導体装置を示す概略断面図である。It is schematic cross-sectional view which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の一部を示す概略上面図である。It is a schematic top view which shows a part of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の一部を示す概略上面図である。It is a schematic top view which shows a part of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の検査方法を示すイメージ図である。It is an image diagram which shows the inspection method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の参考例である。This is a reference example of the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態２にかかる半導体装置の製造方法を示すイメージ図である。It is an image diagram which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の製造方法を示す工程図である。It is a process drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２にかかる頂部の形成方法を示すイメージ図である。It is an image figure which shows the method of forming the top according to Embodiment 2 of this invention. 本発明の実施の形態２にかかる頂部を示すイメージ図である。It is an image diagram which shows the top which concerns on Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の変形例である。This is a modification of the semiconductor device according to the second embodiment of the present invention. 本発明の実施の形態２にかかる半導体装置の変形例である。This is a modification of the semiconductor device according to the second embodiment of the present invention. 本発明の実施の形態３にかかる半導体装置を示す概略断面図である。It is the schematic sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の検査方法を示すイメージ図である。It is an image diagram which shows the inspection method of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４にかかる半導体装置の製造方法を示すイメージ図である。It is an image diagram which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態４にかかる半導体装置の製造方法を示す工程図である。It is a process drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態４にかかる頂部の形成方法を示すイメージ図である。FIG. 5 is an image diagram showing a method of forming a top according to a fourth embodiment of the present invention. 本発明にかかるワイヤを示すイメージ図である。It is an image diagram which shows the wire which concerns on this invention. 本発明にかかる半導体装置の検査方法を示すイメージ図である。It is an image diagram which shows the inspection method of the semiconductor device which concerns on this invention. 本発明にかかる半導体装置の検査方法を示すイメージ図である。It is an image diagram which shows the inspection method of the semiconductor device which concerns on this invention. 本発明にかかる半導体装置の変形例である。This is a modification of the semiconductor device according to the present invention. 本発明にかかる半導体装置の変形例である。This is a modification of the semiconductor device according to the present invention. 本発明にかかる半導体装置の一部を示す概略上面図である。It is a schematic top view which shows a part of the semiconductor device which concerns on this invention.

実施の形態１．
図１は、本発明の実施の形態１にかかる半導体装置を示す概略断面図である。半導体装置１００は、端子４０、端子４１を有するケース４に接着されたヒートシンク５、及びヒートシンク５上に配置された絶縁基板６を備える。絶縁基板６上には、第１の配線７（以下、配線７という）と第２の配線８（以下、配線８という）とが形成されている。以下、ヒートシンク５、絶縁基板６、及び絶縁基板６上に形成された配線７、８を合わせて、基板という。 Embodiment 1.
FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. The semiconductor device 100 includes a terminal 40, a heat sink 5 adhered to a case 4 having terminals 41, and an insulating substrate 6 arranged on the heat sink 5. A first wiring 7 (hereinafter referred to as wiring 7) and a second wiring 8 (hereinafter referred to as wiring 8) are formed on the insulating substrate 6. Hereinafter, the heat sink 5, the insulating substrate 6, and the wirings 7 and 8 formed on the insulating substrate 6 are collectively referred to as a substrate.

配線７、８上にそれぞれ形成された第１の接合部及び第２の接合部（以下、合わせて接合部９という）上には、表面にパターン、裏面に電極が形成された第１の半導体チップ１（以下、半導体チップ１という）及び第２の半導体チップ２（以下、半導体チップ２という）が搭載されている。接合部９によって、半導体チップ１、２のそれぞれの裏面の電極と、配線７、８のそれぞれの表面とが接続されている。 A first semiconductor in which a pattern is formed on the front surface and electrodes are formed on the back surface on the first joint portion and the second joint portion (hereinafter, collectively referred to as the joint portion 9) formed on the wirings 7 and 8, respectively. A chip 1 (hereinafter referred to as a semiconductor chip 1) and a second semiconductor chip 2 (hereinafter referred to as a semiconductor chip 2) are mounted. The joints 9 connect the electrodes on the back surfaces of the semiconductor chips 1 and 2 to the front surfaces of the wirings 7 and 8.

半導体チップ１、２の表面に形成されたパターンには、頂部３３を有するワイヤ３の端部がそれぞれ接続されている。頂部３３とは、ワイヤ３を半導体チップ１、２にボンディングした際に形成される、例えば湾曲した部分を指す。
さらに、半導体チップ１と端子４０とを接続するワイヤ３０、配線８と端子４１とを接続するワイヤ３１を備える。 The ends of the wire 3 having the top 33 are connected to the patterns formed on the surfaces of the semiconductor chips 1 and 2, respectively. The top 33 refers to, for example, a curved portion formed when the wire 3 is bonded to the semiconductor chips 1 and 2.
Further, it includes a wire 30 for connecting the semiconductor chip 1 and the terminal 40, and a wire 31 for connecting the wiring 8 and the terminal 41.

ケース４内には、端子４０、４１の一部、ヒートシンク５の一部、絶縁基板６、配線７、８、半導体チップ１、２、ワイヤ３０、３１、及びワイヤ３の一部を覆うとともに、半導体チップ１、２間に位置するワイヤ３の頂部３３を露出させるように封止部１０が形成されている。半導体装置１００は、例えばエポキシ樹脂により形成された蓋部１１を有し、蓋部１１はケース４内にはめ込まれ、封止部１０を保護する。 The case 4 covers a part of terminals 40 and 41, a part of a heat sink 5, an insulating substrate 6, wirings 7 and 8, semiconductor chips 1, 2 and wires 30, 31 and a part of wire 3. The sealing portion 10 is formed so as to expose the top 33 of the wire 3 located between the semiconductor chips 1 and 2. The semiconductor device 100 has a lid portion 11 formed of, for example, an epoxy resin, and the lid portion 11 is fitted in the case 4 to protect the sealing portion 10.

ここで、図２は、半導体装置１００の一部を示す概略上面図であり、図３は、図２から封止部１０を取り除いた図である。図２、図３において、ワイヤ３０、３１は省略する。
図２の破線部は封止部１０内の半導体チップ１、２の搭載位置、点線部は封止部１０内のワイヤ３の配置位置であり、封止部１０からワイヤ３の頂部３３を露出させた状態を示す。各ワイヤ３の頂部３３間の幅である頂部幅Ｗ１は、ワイヤ３同士が接触せず、且つ半導体装置１００が絶縁を保てる距離となるように配置させる。 Here, FIG. 2 is a schematic top view showing a part of the semiconductor device 100, and FIG. 3 is a view in which the sealing portion 10 is removed from FIG. In FIGS. 2 and 3, the wires 30 and 31 are omitted.
The broken line portion in FIG. 2 is the mounting position of the semiconductor chips 1 and 2 in the sealing portion 10, the dotted line portion is the arrangement position of the wire 3 in the sealing portion 10, and the top 33 of the wire 3 is exposed from the sealing portion 10. Shows the state of being made. The top width W1, which is the width between the tops 33 of each wire 3, is arranged so that the wires 3 do not come into contact with each other and the semiconductor device 100 can maintain insulation.

このように、半導体装置１００は、基板と、基板上に形成された接合部９と、接合部９上にそれぞれ搭載されるとともに、裏面に形成された電極と基板とが接続された半導体チップ１、２と、半導体チップ１、２のそれぞれの表面に形成されたパターンに両端部がそれぞれ接続されたワイヤ３と、基板の一部、接合部９、半導体チップ１、２、及びワイヤ３の一部を覆うとともに、ワイヤ３の頂部３３を露出させた封止部１０とを備えたものである。 As described above, the semiconductor device 100 is mounted on the substrate, the joint portion 9 formed on the substrate, and the semiconductor chip 1 in which the electrode formed on the back surface and the substrate are connected to each other. , 2 and a wire 3 whose both ends are connected to a pattern formed on the surface of each of the semiconductor chips 1 and 2, and a part of a substrate, a bonding portion 9, semiconductor chips 1, 2 and one of wires 3. It is provided with a sealing portion 10 that covers the portion and exposes the top 33 of the wire 3.

この構成により、簡易に半導体チップ１、２の電気特性を解析し、故障箇所１３の特定ができる。 With this configuration, the electrical characteristics of the semiconductor chips 1 and 2 can be easily analyzed, and the failure location 13 can be identified.

ここで、半導体チップ１、２の電気特性を解析し、半導体装置１００を検査する方法について、図４を用いて説明する。
半導体装置１００の蓋部１１を取り外し、封止部１０から露出させたワイヤ３の頂部３３を切断する（図４（ａ））。切断された頂部３３において半導体チップ１と接続されている端部を切断頂部３４、半導体チップ２と接続されている端部を切断頂部３５とする。半導体チップ１の電気特性を解析する場合、切断頂部３４にプローブ１２をコンタクトさせるとともに、別のプローブ１２を端子４０、４１のいずれかにコンタクトさせ、それぞれに電圧を印加する（図４（ｂ））。切断されたワイヤ３を介して半導体チップ１に電圧が印加される。 Here, a method of analyzing the electrical characteristics of the semiconductor chips 1 and 2 and inspecting the semiconductor device 100 will be described with reference to FIG.
The lid portion 11 of the semiconductor device 100 is removed, and the top portion 33 of the wire 3 exposed from the sealing portion 10 is cut (FIG. 4A). The end of the cut top 33 connected to the semiconductor chip 1 is referred to as the cut top 34, and the end connected to the semiconductor chip 2 is referred to as the cut top 35. When analyzing the electrical characteristics of the semiconductor chip 1, the probe 12 is brought into contact with the cutting top 34, and another probe 12 is brought into contact with any of the terminals 40 and 41, and a voltage is applied to each of them (FIG. 4B). ). A voltage is applied to the semiconductor chip 1 via the cut wire 3.

例えばショートリーク不良によって、電圧が印加された半導体チップ１の故障箇所１３には電流が集中する。電流の集中によりジュール熱が発生するため、この発熱を発熱解析装置のカメラ、例えばＩｎＧａＡｓカメラによって検出する。これにより、半導体チップ１上の発熱箇所が特定され、発熱の特定によって半導体チップ１の故障箇所１３が特定できる。 For example, due to a short leak defect, the current is concentrated at the failure portion 13 of the semiconductor chip 1 to which the voltage is applied. Joule heat is generated by the concentration of current, and this heat generation is detected by a camera of a heat generation analyzer, for example, an InGaAs camera. As a result, the heat generating portion on the semiconductor chip 1 can be specified, and the failure portion 13 of the semiconductor chip 1 can be identified by specifying the heat generation.

切断頂部３４に電圧の印加を行っても半導体チップ１から発熱が生じなければ、切断頂部３５にプローブ１２を接触させ電圧を印加し、同様に半導体チップ２の電気特性を解析する。 If heat is not generated from the semiconductor chip 1 even when the voltage is applied to the cutting top 34, the probe 12 is brought into contact with the cutting top 35 and a voltage is applied, and the electrical characteristics of the semiconductor chip 2 are analyzed in the same manner.

半導体装置１００において、頂部３３は半導体チップ１、２間等、半導体チップ１、２上以外の位置に配置させる。図５に示すように、封止部１０から露出した頂部３３が半導体チップ２上に配置された場合、切断頂部３５に接触させたプローブ１２の下に故障箇所１３があると、プローブ１２によって故障箇所１３からの発熱の伝搬が遮られる。プローブ１２が発熱の伝搬を遮ることにより、発熱の検出ができず、半導体チップ２上の故障箇所１３の特定が困難となる場合がある。 In the semiconductor device 100, the top 33 is arranged at a position other than above the semiconductor chips 1 and 2, such as between the semiconductor chips 1 and 2. As shown in FIG. 5, when the top 33 exposed from the sealing portion 10 is arranged on the semiconductor chip 2, if the failure portion 13 is under the probe 12 in contact with the cutting top 35, the probe 12 causes a failure. Propagation of heat from location 13 is blocked. Since the probe 12 blocks the propagation of heat generation, the heat generation cannot be detected, and it may be difficult to identify the failure location 13 on the semiconductor chip 2.

上述のように、封止部１０から露出させた頂部３３を切断し、切断した頂部３３にプローブ１２を接触させて半導体チップの電気特性の解析することにより、薬液、物理研磨等を用いた半導体装置１００の開封作業を行わずに、半導体チップの故障箇所１３を特定できる。 As described above, a semiconductor using a chemical solution, physical polishing, or the like is used by cutting the top 33 exposed from the sealing portion 10 and bringing the probe 12 into contact with the cut top 33 to analyze the electrical characteristics of the semiconductor chip. The failure location 13 of the semiconductor chip can be identified without opening the device 100.

また、薬液、物理研磨等を用いた開封作業を行わないため、半導体装置１００の検査時間を短縮できる。 Further, since the opening operation using a chemical solution, physical polishing, or the like is not performed, the inspection time of the semiconductor device 100 can be shortened.

なお、絶縁基板６は、例えばセラミック基板のＡｌＮを用いることができ、絶縁基板６の表面には、例えばパターン厚さ０．４ｍｍの配線７、８が設けられる。
また、絶縁基板６は、絶縁性が得られ、配線７、８を形成できれば、アルミナ、炭化ケイ素、窒化ケイ素等を用いてもよい。ガラスエポキシ基板又は金属ベース基板でもよい。 As the insulating substrate 6, for example, AlN of a ceramic substrate can be used, and wirings 7 and 8 having a pattern thickness of 0.4 mm are provided on the surface of the insulating substrate 6, for example.
Further, as the insulating substrate 6, alumina, silicon carbide, silicon nitride or the like may be used as long as the insulating substrate 6 can be obtained and the wirings 7 and 8 can be formed. It may be a glass epoxy substrate or a metal base substrate.

絶縁基板６に形成される配線７、８は、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ等の金属を用いればよい。 Metals such as Cu, Ni, Au, and Ag may be used for the wirings 7 and 8 formed on the insulating substrate 6.

実施の形態２．
図６は、本発明の実施の形態２にかかる半導体装置の製造方法を示すイメージ図であり、図７は、半導体装置の製造方法を示す工程図である。
図６（ａ）に示すように、ヒートシンク５に、表面に配線７、８が形成された絶縁基板６の裏面が、例えばはんだによって接合される。ヒートシンク５、絶縁基板６、及び配線７、８により基板が形成される（基板形成工程）。 Embodiment 2.
FIG. 6 is an image diagram showing a manufacturing method of the semiconductor device according to the second embodiment of the present invention, and FIG. 7 is a process diagram showing a manufacturing method of the semiconductor device.
As shown in FIG. 6A, the back surface of the insulating substrate 6 having the wirings 7 and 8 formed on the front surface thereof is joined to the heat sink 5 by, for example, solder. A substrate is formed by the heat sink 5, the insulating substrate 6, and the wirings 7 and 8 (substrate forming step).

配線７、８のそれぞれに、接合部材９９（図示せず）を配置し（接合部材配置工程）、接合部材９９上にそれぞれ半導体チップ１、２を搭載する（半導体チップ搭載工程）。接合部材９９を加熱等により、半導体チップ１、２の裏面に形成された電極と、配線７、８の表面とをそれぞれ接合させ接合部９を形成する（接合部形成工程）。 A joining member 99 (not shown) is placed on each of the wirings 7 and 8 (joining member placement step), and semiconductor chips 1 and 2 are mounted on the joining member 99, respectively (semiconductor chip mounting step). The joint member 99 is heated or the like to join the electrodes formed on the back surfaces of the semiconductor chips 1 and 2 and the front surfaces of the wirings 7 and 8, respectively, to form the joint portion 9 (joint portion forming step).

半導体チップ１、２を搭載した基板をケース４の底部に、例えばシリコーン樹脂を接着剤として用いて接着固定する（基板接着工程）。このとき、ヒートシンク５を外部に露出させるように配置する。ケース４は、予め例えばインサート成型によって、端子４０、４１、例えばドレイン端子、エミッタ端子、信号端子等の外部端子の一部を露出させ、埋め込んで形成すればよい。 A substrate on which the semiconductor chips 1 and 2 are mounted is adhered and fixed to the bottom of the case 4 by using, for example, a silicone resin as an adhesive (substrate bonding step). At this time, the heat sink 5 is arranged so as to be exposed to the outside. The case 4 may be formed by exposing and embedding a part of terminals 40, 41, for example, external terminals such as a drain terminal, an emitter terminal, and a signal terminal in advance by insert molding.

図６（ｂ）に示すように、ワイヤ３の一端を半導体チップ１のパターン上に、他端を半導体チップ２のパターン上に配置し、超音波振動等によってボンディングする（ボンディング工程）。このとき、ワイヤ３の湾曲した部分を頂部３３とし、頂部３３は半導体チップ１、２間等、半導体チップ１、２上以外の位置に配置させる。さらに、ワイヤ３０の一端を半導体チップ１のパターン上に、他端を端子４０に配置し、ワイヤ３１の一端を配線８上に、他端を端子４１に配置し、それぞれボンディングする。 As shown in FIG. 6B, one end of the wire 3 is arranged on the pattern of the semiconductor chip 1 and the other end is arranged on the pattern of the semiconductor chip 2, and the wires are bonded by ultrasonic vibration or the like (bonding step). At this time, the curved portion of the wire 3 is designated as the top 33, and the top 33 is arranged at a position other than on the semiconductor chips 1 and 2, such as between the semiconductor chips 1 and 2. Further, one end of the wire 30 is arranged on the pattern of the semiconductor chip 1, the other end is arranged on the terminal 40, one end of the wire 31 is arranged on the wiring 8, and the other end is arranged on the terminal 41, and they are bonded to each other.

図６（ｃ）に示すように、封止部材１４、例えば６０℃の液状のエポキシ樹脂をディスペンサ１５によってケース４内に注入する（封止部材注入工程）。このとき、封止部材１４はワイヤ３の頂部３３が露出する高さまで注入する。 As shown in FIG. 6C, a sealing member 14, for example, a liquid epoxy resin at 60 ° C. is injected into the case 4 by a dispenser 15 (sealing member injection step). At this time, the sealing member 14 is injected to a height at which the top 33 of the wire 3 is exposed.

図６（ｄ）に示すように、ケース４内に注入した封止部材１４を真空脱泡した後、例えば加熱硬化させる。これによって、端子４０、４１の一部、ヒートシンク５の一部、絶縁基板６、配線７、８、半導体チップ１、２、ワイヤ３０、３１、及びワイヤ３の一部が覆われるとともに、半導体チップ１、２間に配置したワイヤ３の頂部３３が封止部１０から露出する（封止部形成工程）。ここで、加熱硬化とは、例えば封止部材１４を１００℃、１．５時間で加熱した後、１４０℃、１．５時間で加熱することにより行う。 As shown in FIG. 6D, the sealing member 14 injected into the case 4 is vacuum defoamed and then, for example, heat-cured. As a result, a part of the terminals 40 and 41, a part of the heat sink 5, an insulating substrate 6, wirings 7 and 8, semiconductor chips 1, 2, wires 30, 31 and a part of the wire 3 are covered, and the semiconductor chip is covered. The top 33 of the wire 3 arranged between 1 and 2 is exposed from the sealing portion 10 (sealing portion forming step). Here, heat curing is performed, for example, by heating the sealing member 14 at 100 ° C. for 1.5 hours and then heating at 140 ° C. for 1.5 hours.

上述の方法により、簡易に半導体チップ１、２の電気特性を解析し、故障箇所１３の特定できる半導体装置１００を製造できる。 By the above method, the semiconductor device 100 capable of easily analyzing the electrical characteristics of the semiconductor chips 1 and 2 and identifying the failure portion 13 can be manufactured.

また、頂部３３を露出させるために従来よりも封止部１０の厚みを薄くすれば、封止部１０内における故障箇所１３からの発熱の拡散を抑制でき、故障箇所１３の絞り込みが容易となる。そのため、例えば半導体チップの終端、中央部等、数ミリ単位で故障箇所１３を特定することができる。 Further, if the thickness of the sealing portion 10 is made thinner than before in order to expose the top portion 33, the diffusion of heat generated from the failed portion 13 in the sealing portion 10 can be suppressed, and the failure portion 13 can be easily narrowed down. .. Therefore, the failure location 13 can be identified in units of several millimeters, such as the terminal end and the central portion of the semiconductor chip.

なお、ワイヤ３を半導体チップ１、２にボンディングさせた際に形成された湾曲した部分を頂部３３とする例を示したが、頂部３３を直線状に形成してもよい。図８（ａ）、図８（ｂ）に示すように、湾曲した頂部３３を押さえ板１６によって上からプレスすることにより、頂部３３を直線状に形成できる（図９）。
この構成により、切断頂部３４、３５とプローブ１２との接触面積が大きくなり、安定して導通を確保することができるため、半導体チップ１、２の解析が容易となる。 Although the curved portion formed when the wire 3 is bonded to the semiconductor chips 1 and 2 is used as the top portion 33, the top portion 33 may be formed in a straight line. As shown in FIGS. 8 (a) and 8 (b), the top 33 can be formed in a straight line by pressing the curved top 33 from above with the pressing plate 16 (FIG. 9).
With this configuration, the contact area between the cutting tops 34 and 35 and the probe 12 is increased, and stable conduction can be ensured, so that the semiconductor chips 1 and 2 can be easily analyzed.

また、図１０に示すように、ワイヤ３よりも長さの長いワイヤ３２を用いる、又は封止部１０の高さを低くする等により、封止部１０から露出する頂部３３の高さＨ１を高くする。これにより、押さえ板１６を、例えば斜めにスライドさせながら頂部３３をプレスすると、封止部１０側に頂部３３が倒れる（図１１）。
この構成により、露出している頂部３３の面積が大きくなるとともに接触面積が大きくなるため、安定して導通を確保することができ、半導体チップ１、２の解析が容易となる。また、頂部３３を封止部１０側に倒して配置するため、封止部１０上の突起物を少なくでき、搬送時等に取り扱い易く、ワイヤ３２の破損を抑制できる。 Further, as shown in FIG. 10, the height H1 of the top portion 33 exposed from the sealing portion 10 is increased by using a wire 32 having a length longer than that of the wire 3 or lowering the height of the sealing portion 10. Make it high. As a result, when the top portion 33 is pressed while sliding the pressing plate 16 diagonally, for example, the top portion 33 falls to the sealing portion 10 side (FIG. 11).
With this configuration, the area of the exposed top 33 becomes large and the contact area becomes large, so that stable conduction can be ensured and the analysis of the semiconductor chips 1 and 2 becomes easy. Further, since the top portion 33 is arranged so as to be tilted toward the sealing portion 10, the number of protrusions on the sealing portion 10 can be reduced, it is easy to handle during transportation and the like, and damage to the wire 32 can be suppressed.

また、封止部材１４としてエポキシ樹脂を用いる例を示したが、シリコーンゲルでもよい。 Further, although an example in which an epoxy resin is used as the sealing member 14 is shown, a silicone gel may also be used.

また、ケース４は、例えばＰＰＳ（ＰｏｌｙＰｈｅｎｙｌｅｎｅ Ｓｕｌｆｉｄｅ）樹脂、ＬＣＰ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｐｏｌｙｍｅｒ、液晶ポリマー）樹脂等を用いて形成できる。 Further, the case 4 can be formed by using, for example, a PPS (PolyPhene sulfide) resin, an LCP (Liquid Crystal Polymer) resin, or the like.

なお、実施の形態１、２において、ヒートシンク５、絶縁基板６、及び配線７、８により基板を形成する例を示したが、少なくとも絶縁基板６及び配線７、８があればよい。 In the first and second embodiments, an example in which the substrate is formed by the heat sink 5, the insulating substrate 6, and the wirings 7 and 8 is shown, but at least the insulating substrate 6 and the wirings 7 and 8 may be provided.

実施の形態３．
図１２は、本発明の実施の形態３にかかる半導体装置を示す概略断面図である。図１２において、図１と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。 Embodiment 3.
FIG. 12 is a schematic cross-sectional view showing the semiconductor device according to the third embodiment of the present invention. In FIG. 12, those having the same reference numerals as those in FIG. 1 indicate the same or corresponding configurations, and the description thereof will be omitted.

半導体装置２００には、ヒートシンク５上にリードフレーム１９及びリードフレーム２０が配置されている。以下、ヒートシンク５及びリードフレーム１９、２０を合わせて基板という。リードフレーム１９上には半導体チップ１、２が搭載される。半導体チップ１、２は、それぞれリードフレーム１９と接合部９によって接合される。 In the semiconductor device 200, a lead frame 19 and a lead frame 20 are arranged on the heat sink 5. Hereinafter, the heat sink 5 and the lead frames 19 and 20 are collectively referred to as a substrate. Semiconductor chips 1 and 2 are mounted on the lead frame 19. The semiconductor chips 1 and 2 are joined by the lead frame 19 and the joining portion 9, respectively.

実施の形態１と同様に、ワイヤ３の両端部は、それぞれ半導体チップ１、２の表面のパターンと接続され、頂部３３は半導体チップ１、２の上以外、例えば半導体チップ１、２間に配置される。さらに本実施の形態では、半導体チップ１の表面のパターンとリードフレーム２０とが、ワイヤ３６によって接続されている。 Similar to the first embodiment, both ends of the wire 3 are connected to the surface patterns of the semiconductor chips 1 and 2, respectively, and the top 33 is arranged other than above the semiconductor chips 1 and 2, for example, between the semiconductor chips 1 and 2. Will be done. Further, in the present embodiment, the surface pattern of the semiconductor chip 1 and the lead frame 20 are connected by a wire 36.

封止部２１は、ヒートシンク５の一部、リードフレーム１９、２０の一部、半導体チップ１、２、ワイヤ３の一部、及びワイヤ３６を覆うとともに、ワイヤ３のそれぞれの頂部３３を露出させるように形成される。 The sealing portion 21 covers a part of the heat sink 5, a part of the lead frames 19 and 20, a part of the semiconductor chips 1, 2 and the wire 3, and the wire 36, and exposes the top 33 of each of the wires 3. Is formed like this.

このように、半導体装置２００は、基板と、基板上に形成された接合部９と、接合部９上にそれぞれ搭載されるとともに、裏面に形成された電極と基板とが接続された半導体チップ１、２と、半導体チップ１、２のそれぞれの表面に形成されたパターンに両端部がそれぞれ接続されたワイヤ３と、基板の一部、接合部９、半導体チップ１、２、及びワイヤ３の一部を覆うとともに、ワイヤ３の頂部３３を露出させた封止部２１とを備えたものである。 As described above, the semiconductor device 200 is mounted on the substrate, the joint portion 9 formed on the substrate, and the joint portion 9, respectively, and the semiconductor chip 1 in which the electrode formed on the back surface and the substrate are connected to each other. , 2 and a wire 3 whose both ends are connected to a pattern formed on the surface of each of the semiconductor chips 1 and 2, and a part of a substrate, a bonding portion 9, semiconductor chips 1, 2 and one of wires 3. It is provided with a sealing portion 21 that covers the portion and exposes the top 33 of the wire 3.

この構成により、簡易に半導体チップ１、２の電気特性を解析し、故障箇所１３の特定ができる。 With this configuration, the electrical characteristics of the semiconductor chips 1 and 2 can be easily analyzed, and the failure location 13 can be identified.

ここで、半導体装置２００を検査する方法について、図１３を用いて説明する。図１３（ａ）は半導体チップ１を解析する図、図１３（ｂ）は半導体チップ２を解析する図である。
図１３（ａ）、図１３（ｂ）において、それぞれ切断頂部３４、切断頂部３５にプローブ１２を接触させるとともに、リードフレーム１９に別のプローブ１２を接触させ、電圧を印加する。切断されたワイヤ３を介して半導体チップ１、２に電圧が印加される。 Here, a method of inspecting the semiconductor device 200 will be described with reference to FIG. FIG. 13A is a diagram for analyzing the semiconductor chip 1, and FIG. 13B is a diagram for analyzing the semiconductor chip 2.
In FIGS. 13 (a) and 13 (b), the probe 12 is brought into contact with the cutting top 34 and the cutting top 35, respectively, and another probe 12 is brought into contact with the lead frame 19 to apply a voltage. A voltage is applied to the semiconductor chips 1 and 2 via the cut wire 3.

実施の形態１と同様に、例えばショートリーク不良によって電圧が印加された半導体チップ１又は半導体チップ２の故障箇所１３には電流が集中し、電流の集中により発生したジュール熱を発熱解析装置のカメラ、例えばＩｎＧａＡｓカメラによって検出する。これにより、半導体チップ１上の発熱箇所が特定され、発熱の特定によって半導体チップ１又は半導体チップ２の故障箇所１３が特定できる。 Similar to the first embodiment, for example, a current is concentrated on the failure portion 13 of the semiconductor chip 1 or the semiconductor chip 2 to which a voltage is applied due to a short leak defect, and the Joule heat generated by the current concentration is collected by the camera of the heat generation analyzer. For example, it is detected by an InGaAs camera. As a result, the heat generating portion on the semiconductor chip 1 is specified, and the failure portion 13 of the semiconductor chip 1 or the semiconductor chip 2 can be identified by specifying the heat generation.

上述のように、封止部２１から露出している頂部３３を切断し、切断した頂部３３にプローブ１２を接触させて半導体チップ１、２の電気特性の解析することにより、半導体装置２００を薬液、物理研磨等を用いた開封作業を行わずに、半導体チップの故障箇所１３を特定できる。 As described above, the semiconductor device 200 is subjected to a chemical solution by cutting the top 33 exposed from the sealing portion 21 and bringing the probe 12 into contact with the cut top 33 to analyze the electrical characteristics of the semiconductor chips 1 and 2. , The failure portion 13 of the semiconductor chip can be identified without performing the opening operation using physical polishing or the like.

実施の形態４．
図１４は、本発明の実施の形態４にかかる半導体装置の製造方法を示すイメージ図であり、図１５は、半導体装置の製造方法を示す工程図である。図１４において、図６と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。実施の形態２とは、上金型１７、下金型１８を用いてその中に封止部材２２を充填し、硬化させて封止部２１を形成する点が異なる。 Embodiment 4.
FIG. 14 is an image diagram showing a manufacturing method of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 15 is a process diagram showing a manufacturing method of the semiconductor device. In FIG. 14, those having the same reference numerals as those in FIG. 6 indicate the same or corresponding configurations, and the description thereof will be omitted. The second embodiment is different from the second embodiment in that the sealing member 22 is filled in the upper mold 17 and the lower mold 18 and cured to form the sealing portion 21.

図１４（ａ）に示すように、ヒートシンク５上にリードフレーム１９、２０を配置し、ヒートシンク５及びリードフレーム１９、２０から構成された基板を形成する（基板形成工程）。リードフレーム１９上に接合部材９９を配置し（接合部材配置工程）、半導体チップ１、２を搭載する（半導体チップ搭載工程）。接合部材９９を、例えば加熱することによって、半導体チップ１、２の裏面に形成された電極と、リードフレーム１９とを接合させ、接合部９を形成する（接合部形成工程）。 As shown in FIG. 14A, lead frames 19 and 20 are arranged on the heat sink 5 to form a substrate composed of the heat sink 5 and lead frames 19 and 20 (board forming step). The joining member 99 is arranged on the lead frame 19 (joining member arrangement step), and the semiconductor chips 1 and 2 are mounted (semiconductor chip mounting step). By heating the joining member 99, for example, the electrodes formed on the back surfaces of the semiconductor chips 1 and 2 and the lead frame 19 are joined to form the joining portion 9 (joining portion forming step).

図１４（ｂ）に示すように、ワイヤ３の両端部をそれぞれ半導体チップ１、２の表面のパターン上に配置し、超音波振動等によってボンディングする。同様に、ワイヤ３６の両端部をそれぞれ半導体チップ１及びリードフレーム２０上に配置し、ボンディングする（ボンディング工程）。このとき、ワイヤ３の湾曲した部分を頂部３３とする。 As shown in FIG. 14B, both ends of the wire 3 are arranged on the surface patterns of the semiconductor chips 1 and 2, respectively, and bonded by ultrasonic vibration or the like. Similarly, both ends of the wire 36 are arranged on the semiconductor chip 1 and the lead frame 20, respectively, and bonded (bonding step). At this time, the curved portion of the wire 3 is designated as the top portion 33.

図１４（ｃ）に示すように、基板の表面側（リードフレーム１９、２０側）にボンディングされたワイヤ３、３６を含むように半筒状の上金型１７を配置し、基板の裏面側（ヒートシンク５側）に半筒状の下金型１８を配置し、基板を上下から挟む（金型配置工程）。このとき、上金型１７と頂部３３とを接触させる。 As shown in FIG. 14C, a semi-cylindrical upper mold 17 is arranged so as to include the wires 3 and 36 bonded to the front surface side (lead frames 19 and 20 side) of the substrate, and the back surface side of the substrate is arranged. A semi-cylindrical lower mold 18 is placed on (heat sink 5 side), and the substrate is sandwiched from above and below (mold placement step). At this time, the upper mold 17 and the top 33 are brought into contact with each other.

図１４（ｄ）に示すように、封止部材２２を上金型１７及び下金型１８の間に注入し（封止部材注入工程）、基板の一部、半導体チップ１、２、ワイヤ３、３１を封止部材２２で覆う。そして、封止部材２２を例えば圧力をかけることにより硬化させ、封止部２１を形成する（封止部形成工程）。 As shown in FIG. 14D, the sealing member 22 is injected between the upper mold 17 and the lower mold 18 (sealing member injection step), and a part of the substrate, the semiconductor chips 1, 2 and the wire 3 are injected. , 31 is covered with the sealing member 22. Then, the sealing member 22 is cured by applying pressure, for example, to form the sealing portion 21 (sealing portion forming step).

上述の方法により、簡易に半導体チップ１、２の電気特性を解析し、故障箇所１３の特定ができる半導体装置２００が製造できる。 By the above method, the semiconductor device 200 capable of easily analyzing the electrical characteristics of the semiconductor chips 1 and 2 and identifying the failure portion 13 can be manufactured.

また、封止部２１を形成した後、各頂部３３と上金型１７との隙間に封止部材２２が入り込んだとしても、カッター等で頂部３３を覆う封止部材２２を除去することができ、頂部３３を容易に封止部２１から露出させることができる。 Further, even if the sealing member 22 enters the gap between each top 33 and the upper mold 17 after the sealing portion 21 is formed, the sealing member 22 covering the top 33 can be removed by a cutter or the like. , The top 33 can be easily exposed from the sealing portion 21.

なお、封止部２１から露出させる頂部３３を予め絶縁材、例えばポリイミドによってコーティングすることにより、頂部３３に封止部材１４が付着しにくくなり、封止部２１から頂部３３を露出させることが容易となる。 By coating the top 33 exposed from the sealing portion 21 in advance with an insulating material, for example, polyimide, the sealing member 14 is less likely to adhere to the top 33, and it is easy to expose the top 33 from the sealing portion 21. It becomes.

また、図１６に示すように、半導体チップ１から頂部３３までの高さＨ２を、半導体チップ１から上金型１７の内周面までの高さＨ３よりも高くして、上金型１７をセッティングする際にワイヤ３、３１の頂部３３を上金型１７の内周面によって押さえつけ、各頂部３３を直線状に形成してもよい。
この構成により、封止部２１から露出させた頂部３３の面積が大きくなり、プローブ１２の接触面積が大きくなる。そのため、安定して導通を確保することができ、半導体チップ１、２の解析が容易となる。また、頂部３３が封止部２１側に倒れるように配置されるため、封止部２１上の突起物を少なくでき、搬送時等に取り扱い易くなり、ワイヤ３、３６の破損を抑制できる。 Further, as shown in FIG. 16, the height H2 from the semiconductor chip 1 to the top 33 is made higher than the height H3 from the semiconductor chip 1 to the inner peripheral surface of the upper mold 17, so that the upper mold 17 is formed. At the time of setting, the top 33 of the wires 3 and 31 may be pressed by the inner peripheral surface of the upper mold 17, and each top 33 may be formed in a straight line.
With this configuration, the area of the top portion 33 exposed from the sealing portion 21 becomes large, and the contact area of the probe 12 becomes large. Therefore, stable conduction can be ensured, and analysis of the semiconductor chips 1 and 2 becomes easy. Further, since the top portion 33 is arranged so as to fall toward the sealing portion 21, the number of protrusions on the sealing portion 21 can be reduced, it becomes easier to handle during transportation and the like, and damage to the wires 3 and 36 can be suppressed.

なお、実施の形態３、４において、半導体チップ１とリードフレーム２０とを接続するワイヤ３６の頂部３３を封止部２１から露出させてもよい。ワイヤ３６の頂部３３を切断し、半導体チップ１と接続されている側のワイヤ３６を用いて、半導体チップ１の解析を行えばよい。 In the third and fourth embodiments, the top 33 of the wire 36 connecting the semiconductor chip 1 and the lead frame 20 may be exposed from the sealing portion 21. The top 33 of the wire 36 may be cut, and the semiconductor chip 1 may be analyzed using the wire 36 on the side connected to the semiconductor chip 1.

また、半導体チップ１とリードフレーム２０とをワイヤ３６で接続する例を示したが、半導体チップ２とリードフレーム２０とを接続してもよい。 Further, although the example in which the semiconductor chip 1 and the lead frame 20 are connected by the wire 36 is shown, the semiconductor chip 2 and the lead frame 20 may be connected.

また、ヒートシンク５及びリードフレーム１９、２０により基板を形成する例を示したが、少なくともリードフレーム１９、２０があればよい。 Further, although an example in which the substrate is formed by the heat sink 5 and the lead frames 19 and 20, the substrate may be formed by at least the lead frames 19 and 20.

なお、実施の形態１〜４において、ワイヤ３、３２、３６の表面を、絶縁材、例えばポリイミドで覆い、絶縁膜２３を形成したワイヤ３７を用いてもよい（図１７）。この場合、ワイヤ３７と半導体チップ１、２の表面のパターンとを超音波振動等で擦り合わせ、絶縁膜２３を除去しながらボンディングすればよい。
半導体チップ１、２の解析時は、露出させた頂部３３を切断し（図１８）、カッター等で絶縁膜２３をそぎ落として導通を取ればよい（図１９）。
これにより、頂部３３が大気に暴露されないため、腐食、劣化等を抑制できる。また、絶縁膜２３によって頂部３３の絶縁を保つことができるため、放電等の不具合を防ぐことができる。 In the first to fourth embodiments, the wire 37 in which the surfaces of the wires 3, 32 and 36 are covered with an insulating material such as polyimide to form an insulating film 23 may be used (FIG. 17). In this case, the wire 37 and the surface patterns of the semiconductor chips 1 and 2 may be rubbed against each other by ultrasonic vibration or the like, and the insulating film 23 may be removed and bonded.
When analyzing the semiconductor chips 1 and 2, the exposed top 33 may be cut (FIG. 18), and the insulating film 23 may be scraped off with a cutter or the like to obtain continuity (FIG. 19).
As a result, since the top 33 is not exposed to the atmosphere, corrosion, deterioration and the like can be suppressed. Further, since the insulating film 23 can maintain the insulation of the top 33, it is possible to prevent problems such as electric discharge.

また、図２０に示すように、封止部１０又は封止部２１の表層を絶縁性のコーティング材、例えばポリイミド等で覆い、コーティング層２４を形成してもよい。これにより、頂部３３が大気に暴露されないため腐食、劣化を抑制できる。また、ボンディング時に過度な力が半導体チップ１、２に加わらず、半導体チップ１、２の破壊を抑制できる。
また、コーティング層２４によって、露出させた頂部３３間で絶縁を保つことができ、放電等の不具合を防ぐことができる。半導体チップ１、２の解析時は、カッター等でコーティング層２４をそぎ落として導通を取ればよい。 Further, as shown in FIG. 20, the surface layer of the sealing portion 10 or the sealing portion 21 may be covered with an insulating coating material such as polyimide to form the coating layer 24. As a result, since the top 33 is not exposed to the atmosphere, corrosion and deterioration can be suppressed. Further, excessive force is not applied to the semiconductor chips 1 and 2 at the time of bonding, and the destruction of the semiconductor chips 1 and 2 can be suppressed.
In addition, the coating layer 24 can maintain insulation between the exposed tops 33 and prevent problems such as electric discharge. When analyzing the semiconductor chips 1 and 2, the coating layer 24 may be scraped off with a cutter or the like to obtain continuity.

さらに、図２１に示すように、封止部１０又は封止部２１から露出させた頂部３３にのみポリイミド等で覆い、コーティング層２５を形成してもよい。これにより、上述の効果とともに、頂部３３にのみコーティング層２５を形成することにより、コーティング材の材料費を抑えられ、加工時間も短縮できる。 Further, as shown in FIG. 21, the coating layer 25 may be formed by covering only the sealing portion 10 or the top portion 33 exposed from the sealing portion 21 with polyimide or the like. As a result, in addition to the above-mentioned effects, by forming the coating layer 25 only on the top 33, the material cost of the coating material can be suppressed and the processing time can be shortened.

また、図２２に示すように、頂部３３間の幅である頂部幅Ｗ２が大きくなるようにワイヤ３、３２、３６を湾曲させてボンディングしてもよい。これにより、頂部３３の絶縁距離を確保し、放電等の不具合を防ぐことができる。 Further, as shown in FIG. 22, the wires 3, 32, and 36 may be curved and bonded so that the top width W2, which is the width between the tops 33, becomes large. As a result, the insulation distance of the top 33 can be secured, and problems such as electric discharge can be prevented.

また、ワイヤ３、３２、３６には、Ａｌ、Ｃｕ、Ａｌ被覆Ｃｕ、Ａｕ等を用いればよい。ワイヤ３、３２、３６をリボンボンド、バスバーにしてもよい。 Further, Al, Cu, Al-coated Cu, Au and the like may be used for the wires 3, 32 and 36. The wires 3, 32 and 36 may be ribbon bonds or bus bars.

半導体チップ１、２としては、例えばＩＧＢＴ、整流ダイオード、環流ダイオード、サージ保護用ダイオード等を用いればよい。ＭＯＳＦＥＴ（Ｍｅｔａｌ−Ｏｘｉｄｅ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ−Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）を用いてもよい。 As the semiconductor chips 1 and 2, for example, an IGBT, a rectifier diode, a recirculation diode, a surge protection diode, or the like may be used. MOSFETs (Metal-Oxide-Semiconductor Field-Effective Transistors) may be used.

また、半導体装置１００、２００は、１対の半導体チップ１、２を用いる１ｉｎ１としたが、２対の２ｉｎ１、６対の６ｉｎ１であってもよい。 Further, the semiconductor devices 100 and 200 are 1in1 using a pair of semiconductor chips 1 and 2, but may be 2 pairs of 2in1 and 6 pairs of 6in1.

また、接合部材９９として例えば厚さ０．１５ｍｍのシート状はんだを用いてもよい。Ａｇフィラーをエポキシ樹脂に分散させた導電性接着剤を用いてもよい。Ａｇ焼結材又はＣｕ焼結材でもよい。 Further, as the joining member 99, for example, a sheet-like solder having a thickness of 0.15 mm may be used. A conductive adhesive in which Ag filler is dispersed in an epoxy resin may be used. It may be an Ag sintered material or a Cu sintered material.

また、本発明は、発明の範囲内において、各実施の形態を自由に組み合わせることや、各実施の形態を適宜、変形、省略することが可能である。 Further, in the present invention, each embodiment can be freely combined within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１、２ 半導体チップ、３、３０、３１、３２、３６、３７ ワイヤ、４ ケース、
５ ヒートシンク、６ 絶縁基板、７、８ 配線、９ 接合部、１０、２１ 封止部、
１１ 蓋部、１２ プローブ、１３ 故障箇所、１４、２２ 封止部材、
１５ ディスペンサ、１６ 押さえ板、１７ 上金型、１８ 下金型、
１９、２０ リードフレーム、２３ 絶縁膜、２４、２５ コーティング層、
３３ 頂部、３４、３５ 切断頂部、４０、４１ 端子、９９ 接合部材、
１００、２００ 半導体装置。 1, 2 semiconductor chips, 3, 30, 31, 32, 36, 37 wires, 4 cases,
5 heat sink, 6 insulation board, 7, 8 wiring, 9 joints, 10, 21 seals,
11 Lid, 12 Probe, 13 Failure, 14, 22 Sealing member,
15 dispenser, 16 holding plate, 17 upper mold, 18 lower mold,
19, 20 lead frame, 23 insulating film, 24, 25 coating layer,
33 top, 34, 35 cutting top, 40, 41 terminals, 99 joint members,
100, 200 semiconductor devices.

Claims (16)

基板と、
前記基板上に形成された第１の接合部及び第２の接合部と、
前記第１の接合部及び前記第２の接合部上にそれぞれ搭載されるとともに、裏面に形成された電極と前記基板とが接続された第１の半導体チップ及び第２の半導体チップと、
前記第１の半導体チップ及び前記第２の半導体チップのそれぞれの表面に形成されたパターンに両端部がそれぞれ接続された第１のワイヤと、
前記基板の一部、前記第１の接合部、前記第２の接合部、前記第１の半導体チップ、前記第２の半導体チップ、及び前記第１のワイヤの一部を覆うとともに、前記第１のワイヤの頂部を露出させた封止部と
を備えた半導体装置。 With the board
The first joint and the second joint formed on the substrate,
A first semiconductor chip and a second semiconductor chip, which are mounted on the first joint portion and the second joint portion and in which an electrode formed on the back surface and the substrate are connected, respectively.
A first wire having both ends connected to a pattern formed on the surfaces of the first semiconductor chip and the second semiconductor chip, respectively.
A part of the substrate, the first joint, the second joint, the first semiconductor chip, the second semiconductor chip, and a part of the first wire are covered, and the first A semiconductor device including a sealing portion with an exposed top of the wire. 前記基板は配線が形成された絶縁基板を有し、前記配線上に前記第１の接合部及び前記第２の接合部が配置される、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the substrate has an insulating substrate on which wiring is formed, and the first joint portion and the second joint portion are arranged on the wiring. 前記基板はリードフレームを有し、前記リードフレーム上に前記第１の接合部及び前記第２の接合部が配置される、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the substrate has a lead frame, and the first joint portion and the second joint portion are arranged on the lead frame. 前記第１の半導体チップ及び前記第２の半導体チップの少なくともいずれかは、さらに第２のワイヤによって前記リードフレームに接続される、請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein at least one of the first semiconductor chip and the second semiconductor chip is further connected to the lead frame by a second wire. 前記頂部は、前記第１の半導体チップ及び前記第２の半導体チップ上以外に配置される、請求項１〜４のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the top portion is arranged other than on the first semiconductor chip and the second semiconductor chip. 前記頂部は湾曲している、請求項１〜５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the top is curved. 前記頂部は直線状である、請求項１〜５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the top is linear. 前記頂部は、前記封止部側に倒れて配置されている、請求項１〜７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the top portion is arranged so as to be tilted toward the sealing portion side. 前記頂部は、絶縁材によって覆われている、請求項１〜８のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 8, wherein the top portion is covered with an insulating material. 前記第１のワイヤの表面は、コーティング材によって覆われている、請求項１〜８のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 8, wherein the surface of the first wire is covered with a coating material. 前記封止部の表層は、露出させた前記頂部を含むように絶縁材によって覆われている、請求項１〜８のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 8, wherein the surface layer of the sealing portion is covered with an insulating material so as to include the exposed top portion. 基板上に第１の接合部材及び第２の接合部材を配置する接合部材配置工程と、
配置された前記第１の接合部材及び前記第２の接合部材上にそれぞれ第１の半導体チップ及び第２の半導体チップを搭載する半導体チップ搭載工程と、
前記第１の半導体チップ及び前記第２の半導体チップが搭載された前記第１の接合部材及び前記第２の接合部材を硬化させ、それぞれ第１の接合部及び第２の接合部を形成する接合部形成工程と、
前記第１の半導体チップ及び前記第２の半導体チップの表面に形成されたパターンと第１のワイヤの両端部とをそれぞれ接続するボンディング工程と、
前記基板の一部、前記第１の接合部、前記第２の接合部、前記第１の半導体チップ、前記第２の半導体チップ、及び前記第１のワイヤの一部を覆うように封止部材を注入する封止部材注入工程と、
注入した前記封止部材を硬化させ、前記頂部を露出させた封止部を形成する封止部形成工程と
を備えた半導体装置の製造方法。 A joining member arranging step of arranging a first joining member and a second joining member on a substrate, and
A semiconductor chip mounting process in which a first semiconductor chip and a second semiconductor chip are mounted on the first joining member and the second joining member, respectively, which are arranged.
A joint in which the first semiconductor chip, the first joint member on which the second semiconductor chip is mounted, and the second joint member are cured to form a first joint portion and a second joint portion, respectively. Part formation process and
A bonding step of connecting the patterns formed on the surfaces of the first semiconductor chip and the second semiconductor chip and both ends of the first wire, respectively.
A sealing member that covers a part of the substrate, the first joint portion, the second joint portion, the first semiconductor chip, the second semiconductor chip, and a part of the first wire. Sealing member injection process to inject
A method for manufacturing a semiconductor device, comprising a sealing portion forming step of curing the injected sealing member to form a sealing portion with an exposed top portion. 前記封止部材注入工程において、前記封止部材を前記頂部が露出する高さまで注入する、請求項１２に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 12, wherein in the sealing member injection step, the sealing member is injected to a height at which the top is exposed. 前記封止部材注入工程において、前記基板の裏面を半筒状の下金型、前記第１の半導体チップ及び前記第２の半導体チップが搭載された表面を前記第１のワイヤが含まれるように半筒状の上金型で挟み、前記下金型及び前記上金型で囲まれた部分に前記封止部材を注入する、請求項１２に記載の半導体装置の製造方法。 In the sealing member injection step, the back surface of the substrate includes a semi-cylindrical lower mold, and the front surface on which the first semiconductor chip and the second semiconductor chip are mounted includes the first wire. The method for manufacturing a semiconductor device according to claim 12, wherein the sealing member is injected into a portion surrounded by the lower mold and the upper mold by sandwiching the semi-cylindrical upper mold. 前記封止部材注入工程において、前記頂部が前記上金型の内側に接した状態で前記封止部材を注入する、請求項１４に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 14, wherein in the sealing member injection step, the sealing member is injected with the top portion in contact with the inside of the upper mold. 請求項１〜１１のいずれか１項に記載の半導体装置の前記頂部を切断する工程と、
切断された前記頂部の一方の先端にプローブを接触させ電圧を印加する工程と
を備えた半導体装置の検査方法。 The step of cutting the top of the semiconductor device according to any one of claims 1 to 11.
A method for inspecting a semiconductor device, comprising a step of bringing a probe into contact with one tip of the cut top and applying a voltage.
JP2019062437A 2019-03-28 2019-03-28 Semiconductor device, method for manufacturing semiconductor device, and method for inspecting semiconductor device Pending JP2020159995A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4084062A1 (en) * 2021-04-30 2022-11-02 Infineon Technologies AG Power semiconductor module arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4084062A1 (en) * 2021-04-30 2022-11-02 Infineon Technologies AG Power semiconductor module arrangement

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