JP3754695B2 - Liquid crystal display device and video signal line driving device - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to video signal line driving means (drain driver) of a liquid crystal display device capable of multi-gradation display.

2. Description of the Related Art An active matrix liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switching driving the active element is widely used as a display device such as a notebook personal computer.
This active matrix type liquid crystal display device applies a video signal voltage (a gray scale voltage corresponding to display data; hereinafter referred to as a gray scale voltage) to the pixel electrode through an active element. Therefore, it is not necessary to use a special driving method for preventing crosstalk as in the case of a simple matrix liquid crystal display device, and multi-gradation display is possible.
One of the active matrix type liquid crystal display device, a TFT (T hin F ilm T ransister ) mode liquid crystal display panel (TFT-LCD), a drain driver disposed above the liquid crystal display panel, the liquid crystal display panel A TFT-type liquid crystal display module having a gate driver and an interface unit arranged on a side surface is known.
In this TFT type liquid crystal display module, a multi-grayscale voltage generation circuit in the drain driver and one grayscale corresponding to display data from the multi-grayscale voltage generated by the multi-grayscale voltage generation circuit. A gradation voltage selection circuit for selecting a voltage and an amplifier circuit to which one gradation voltage selected by the gradation voltage selection circuit is input.
In this case, each bit value of the display data is input to the gradation voltage selection circuit via the level shift circuit.

As prior art documents related to the invention of the present application, there are the following.
JP-A-9-281930

In recent years, in a liquid crystal display device such as a TFT-type liquid crystal display module, multi-gradation display is progressing from 64-gradation display to 256-gradation display. The voltage width per gradation of the regulated voltage (that is, the potential difference between adjacent gradation voltages) is small.
On the other hand, in the amplifier circuit, an offset voltage is generated due to variations in the characteristics of the active elements constituting the amplifier circuit. However, when an offset voltage occurs in the amplifier circuit, an error occurs in the output voltage of the amplifier circuit, and the amplifier circuit The output voltage is a voltage different from the target value (regular gradation voltage).
As a result, black or white vertical stripes are generated in the display screen displayed on the liquid crystal display panel (TFT-LCD), and there is a problem that display quality is remarkably impaired.
On the other hand, in a liquid crystal display device such as a TFT liquid crystal display module, there is a tendency for a liquid crystal display panel (TFT-LCD) to increase in size and resolution (multiple pixels), and furthermore, useless space is eliminated, In order to bring about an aesthetic appearance as a display device, it is desired to make a region other than the display region of the liquid crystal display device, that is, a frame portion as small as possible (narrow frame).
The level shift circuit provided in the previous stage of the gradation voltage selection circuit is composed of a transistor having a high breakdown voltage between the source and the drain.
However, when a high-breakdown-voltage transistor is used as the transistor of the level shift circuit, the area of the level shift circuit portion in the semiconductor integrated circuit (IC chip) constituting the drain driver increases, and accordingly, the drain driver is There is a problem that the chip size of the semiconductor integrated circuit to be configured is increased, the unit price of the chip cannot be lowered, and the narrow frame cannot be dealt with.

  Furthermore, in the past, liquid crystal display devices have been required to have a high resolution of the liquid crystal display panel, and the resolution of the liquid crystal display panel is, for example, from 640 × 480 pixels in the VGA display mode to 800 × 600 pixels in the SVGA display mode. In recent years, in liquid crystal display devices, with the demand for a larger liquid crystal display panel, the resolution of the liquid crystal display panel is 1024 × 768 pixels in the XGA display mode, and 1280 × in the SXGA display mode. There is a demand for higher resolution with 1024 pixels and 1600 × 1200 pixels in the UXGA display mode.

As the resolution of the liquid crystal display panel is increased, the display control device, the drain driver, and the gate driver are also forced to operate at high speed. CL2) and an increase in operating frequency of display data are required.
As a result, there is a problem in that the timing margin when the display data is latched inside the semiconductor integrated circuit constituting the drain driver is reduced.

  The present invention has been made to solve the problems of the prior art, and an object of the present invention is to display a liquid crystal display element in a liquid crystal display device by using an offset voltage of an amplifier circuit of a video signal line driving means. An object of the present invention is to provide a technique capable of preventing the occurrence of black or white vertical stripes in the screen and improving the display quality of the display screen displayed on the liquid crystal display element.

  Another object of the present invention is to provide a semiconductor integrated circuit that constitutes a video signal line driving means by using a low-breakdown-voltage transistor with a source-drain breakdown voltage in the level shift circuit of the video signal line driving means in a liquid crystal display device. The object is to provide a technique capable of reducing the chip size.

Another object of the present invention is to latch display data in a semiconductor integrated circuit constituting a video signal line driving means in a liquid crystal display device even if the display data latch clock and the display data operating frequency are increased. It is an object of the present invention to provide a technique that can ensure the timing margin.
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
A liquid crystal display element having a plurality of pixels to which a video signal voltage corresponding to display data is applied by a plurality of video signal lines, and a video signal line driving means for supplying a video signal voltage corresponding to the display data to each video signal line; The video signal line driving means includes a plurality of amplifier circuits that amplify an input video signal to be input and output a video signal voltage corresponding to display data to each video signal line. In the liquid crystal display device, each amplifier circuit has one of a pair of input terminals as an inverting input terminal or a non-inverting input terminal, and the other of the pair of input terminals as a non-inverting input terminal or an inverting input terminal. Switching means for switching, and the video signal line driving means further includes one of a pair of input terminals of the amplifier circuit as an inverting input terminal and the other as a non-inverting input terminal, A switching instruction means for outputting a switching control signal for switching one of a pair of input terminals of the amplifier circuit to a non-inverting input terminal and the other to an inverting input terminal to the switching means of the amplifier circuit at predetermined intervals. It is characterized by that.

  The switching instruction unit of the video signal line driving unit outputs the switching control signal every n frames to the switching unit of each amplifier circuit.

  The switching instruction means of the video signal line driving means outputs the switching control signal for every n lines and every n frames within each frame to the switching means of each amplifier circuit. To do.

  The video signal line driving means includes a pre-latch unit that latches display data for two pixels at the input stage and outputs the latched data for each pixel, and two bus lines.

  The video signal line driving means has input video signal generating means for generating an input video signal to be input to each amplifier circuit, and the input video signal generating means is a level shift for converting a voltage level of display data. Each level shift circuit including the circuit group and constituting the level shift circuit group includes a transistor having a low breakdown voltage between the first electrode and the second electrode.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, black or white vertical stripes are prevented from being generated in the display screen of the liquid crystal display element due to the offset voltage of the amplifier circuit of the video signal line driving means, and displayed on the liquid crystal display element. The display quality of the display screen can be improved.

(2) According to the present invention, the level shift circuit of the video signal line driving means uses a transistor with a low breakdown voltage between the source and drain, and the breakdown voltage between the source and drain is between the source and drain of the low breakdown voltage transistor. Compared with the case where a high voltage transistor having a withstand voltage or higher is used, the area of the level shift circuit in the chip of the video signal line driving means can be reduced.

(3) According to the present invention, it is possible to reduce the chip size of the video signal line driving means, thereby making it possible to easily cope with the narrowing of the frame, and to reduce the cost of the liquid crystal display device. It becomes possible to improve the property.

(4) According to the present invention, even when the display data latching clock and the display data operating frequency are increased, the timing margin for latching the display data inside the semiconductor integrated circuit constituting the video signal line driving means is reduced. It can be secured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Embodiment 1]
FIG. 1 is a block diagram showing a schematic configuration of a TFT liquid crystal display module according to Embodiment 1 of the present invention.
In the liquid crystal display module (LCM) of the present embodiment, a drain driver 130 is disposed on the upper side of a liquid crystal display panel (TFT-LCD) 10, and a gate driver 140 and an interface unit 100 are provided on a side surface of the liquid crystal display panel 10. Be placed.
The interface unit 100 is mounted on an interface board, and the drain driver 130 and the gate driver 140 are also mounted on a dedicated TCP (Tape Careeier Package) or directly on a liquid crystal display panel, respectively.

FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel 10 shown in FIG.
As shown in FIG. 2, the liquid crystal display panel 10 has a plurality of pixels formed in a matrix.
Each pixel includes two adjacent signal lines (drain signal line (D) or gate signal line (G)) and two adjacent signal lines (gate signal line (G) or drain signal line (D)). It is arranged in the intersection area.
Each pixel has a thin film transistor (TFT1, TFT2), and the source electrode of the thin film transistor (TFT1, TFT2) of each pixel is connected to the pixel electrode (ITO1). In addition, since the liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (ITO2), the liquid crystal capacitance (CLC) is equivalent between the pixel electrode (ITO1) and the common electrode (ITO2). Connected.
Further, an additional capacitor (CADD) is connected between the source electrode of the thin film transistor (TFT1, TFT2) and the previous gate signal line (G).

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG.
In the example shown in FIG. 2, an additional capacitor (CADD) is formed between the previous gate signal line (G) and the source electrode, but in the equivalent circuit of the example shown in FIG. 3, the common signal line (COM) A storage capacitor (CSTG) is formed between the source electrode and the source electrode.
The present invention can be applied to both. In the former method, the gate signal line (G) pulse in the former stage jumps into the pixel electrode (ITO1) via the additional capacitor (CADD), whereas the latter method. Then, since there is no dive, better display becomes possible.
2 and 3 show an equivalent circuit of a vertical electric field type liquid crystal display panel. In FIGS. 2 and 3, AR is a display region. 2 and 3 are circuit diagrams, which are drawn corresponding to an actual geometric arrangement.

  In the liquid crystal display panel 10 shown in FIGS. 2 and 3, the drain electrodes of the thin film transistors (TFTs) of the pixels arranged in the column direction are connected to the drain signal lines (D), respectively, and the drain signal lines (D) are The drain driver 130 applies a gradation voltage to the liquid crystal of each pixel in the column direction.

  In addition, the gate electrode of the thin film transistor (TFT) in each pixel arranged in the row direction is connected to the gate signal line (G), and each gate signal line (G) corresponds to each pixel in the row direction for one horizontal scanning time. The gate driver 140 supplies a scanning drive voltage (positive bias voltage or negative bias voltage) to the gate electrode of the thin film transistor (TFT).

The interface unit 100 illustrated in FIG. 1 includes a display control device 110 and a power supply circuit 120.
The display control device 110 is composed of one semiconductor integrated circuit (LSI), and each display control signal and display data of a clock signal, a display timing signal, a horizontal synchronization signal, and a vertical synchronization signal transmitted from the computer main body side. The drain driver 130 and the gate driver 140 are controlled and driven based on the data (R, G, B).
When the display timing signal is input, the display control device 110 determines that this is a display start position, and outputs a start pulse (display data capture start signal) to the first drain driver 130 via the signal line 135. In addition, the received simple one-column display data is output to the drain driver 130 via the display data bus line 133.
At that time, the display control device 110 displays a display data latch clock (CL2) (hereinafter simply referred to as clock (CL2)) which is a display control signal for latching display data in the data latch circuit of each drain driver 130. ) Is output via the signal line 131.
The display data from the main body computer side is 6 bits, and is transferred in unit of one pixel unit, that is, each data of red (R), green (G), and blue (B) as one set.
Further, the latch operation of the data latch circuit in the first drain driver 130 is controlled by the start pulse input to the first drain driver 130.
When the latch operation of the data latch circuit in the first drain driver 130 is completed, a start pulse is input from the first drain driver 130 to the second drain driver 130, and the second drain driver 130 The latch operation of the data latch circuit is controlled.
Similarly, the latch operation of the data latch circuit in each drain driver 130 is controlled to prevent erroneous display data from being written to the data latch circuit.

  The display control device 110 determines that the display data for one horizontal line has ended when the input of the display timing signal ends or when a predetermined fixed time has passed after the display timing signal is input, and each drain driver 130 Output timing control clock (CL1) (hereinafter simply referred to as clock (CL1)), which is a display control signal for outputting the display data stored in the data latch circuit in FIG. 2 to the drain signal line (D) of the liquid crystal display panel 10. .) Is output to each drain driver 130 via the signal line 132.

  When the first display timing signal is input after the vertical synchronization signal is input, the display control device 110 determines that the first display timing signal is the first display line and transmits the frame to the gate driver 140 via the signal line 142. A start instruction signal is output.

Further, the display control device 110 applies signal lines so as to sequentially apply a positive or negative bias voltage to each gate signal line (G) of the liquid crystal display panel 10 every horizontal scanning time based on the horizontal synchronization signal. The clock (CL3), which is a shift clock of one horizontal scanning time period, is output to the gate driver 140 via 141.
As a result, a plurality of thin film transistors (TFTs) connected to the gate signal lines (G) of the liquid crystal display panel 10 are conducted for one horizontal scanning time.
With the above operation, an image is displayed on the liquid crystal display panel 10.

The power supply circuit 120 illustrated in FIG. 1 includes a positive voltage generation circuit 121, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, and a gate electrode voltage generation circuit 124.
Each of the positive voltage generation circuit 121 and the negative voltage generation circuit 122 is configured by a series resistance voltage dividing circuit, and a positive five-value gradation reference voltage (V ″ 0 to V ″ 4) is generated. A negative five-value gradation reference voltage (V ″ 5 to V ″ 9) is output.
The positive polarity reference voltage (V ″ 0 to V ″ 4) and the negative polarity reference voltage (V ″ 5 to V ″ 9) are supplied to each drain driver 130.
In addition, an AC signal (AC timing signal; M) from the display control device 110 is also supplied to each drain driver 130 via a signal line 134.

  The common electrode voltage generation circuit 123 generates a drive voltage to be applied to the common electrode (ITO2), and the gate electrode voltage generation circuit 124 generates a drive voltage (a positive bias voltage and a negative bias voltage) to be applied to the gate electrode of the thin film transistor (TFT). Generate.

In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, resulting in an afterimage phenomenon and shortening the life of the liquid crystal layer.
In order to prevent this, in this TFT type liquid crystal display module, the voltage applied to the liquid crystal layer is changed to AC every certain time, that is, applied to the pixel electrode based on the voltage applied to the common electrode. The voltage to be changed is changed to the positive voltage side / negative voltage side at regular time intervals.

As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known. The common inversion method is a method of alternately inverting the voltage applied to the common electrode and the voltage applied to the pixel electrode to positive and negative. The common symmetry method is a method in which the voltage applied to the common electrode is constant and the voltage applied to the pixel electrode is alternately inverted to positive and negative with reference to the voltage applied to the common electrode. .
In this common symmetry method, the amplitude of the voltage applied to the pixel electrode (ITO1) is twice that of the common inversion method, and a low breakdown voltage driver cannot be used unless a liquid crystal with a low threshold voltage is developed. Although there are drawbacks, the dot inversion method or the N-line inversion method, which is excellent in terms of low power consumption and display quality, can be used.

In the liquid crystal display module of the present embodiment, the dot inversion method is used as the driving method.
FIG. 4 shows a case where the liquid crystal display module is applied to the liquid crystal drive voltage (that is, the pixel electrode (ITO1)) output from the drain driver 130 to the drain signal line (D) when the dot inversion method is used. It is a figure for demonstrating the polarity of a liquid crystal drive voltage.

When the dot inversion method is used as the driving method of the liquid crystal display module, as shown in FIG. 4, for example, in the odd line of the odd frame, the common signal is supplied from the drain driver 130 to the odd drain signal line (D). The liquid crystal drive voltage (shown by ● in FIG. 4) having a negative polarity with respect to the liquid crystal drive voltage (VCOM) applied to the electrode (ITO2) is also applied to the even-numbered drain signal line (D). ) Is applied to the liquid crystal drive voltage (VCOM) applied to the positive electrode).
Further, in the even-numbered line of the odd-numbered frame, the positive driver liquid crystal driving voltage is applied to the odd-numbered drain signal line (D) and the negative-polarity liquid crystal driving voltage is applied to the even-numbered drain signal line (D). Is applied.
In addition, the polarity of each line is inverted for each frame. That is, as shown in FIG. 4, in the odd line of the even frame, the positive liquid crystal drive is applied from the drain driver 130 to the odd drain signal line (D). A voltage is applied to the even-numbered drain signal line (D), and a negative liquid crystal driving voltage is applied to the even-numbered drain signal line (D).
Further, in the even line of the even frame, the negative driver liquid crystal drive voltage is applied to the odd-numbered drain signal line (D) and the positive liquid crystal drive voltage is applied to the even-numbered drain signal line (D). Is applied.
By using this dot inversion method, the voltage applied to the adjacent drain signal line (D) has a reverse polarity, so the current flowing through the common electrode (ITO2) and the gate electrode of the thin film transistor (TFT) is adjacent to each other. They can cancel each other out and reduce power consumption.
Further, since the current flowing through the common electrode (ITO2) is small and the voltage drop does not increase, the voltage level of the common electrode (ITO2) is stabilized, and the deterioration of display quality can be minimized.

FIG. 5 is a block diagram showing a schematic configuration of an example of the drain driver 130 shown in FIG. The drain driver 130 is composed of one semiconductor integrated circuit (LSI).
In the figure, the positive polarity gradation voltage generation circuit 151 a is based on the positive polarity quinary gradation reference voltage (V ″ 0 to V ″ 4) input from the positive voltage generation circuit 121. A gradation voltage of gradation is generated and output to the output circuit 157 via the voltage bus line 158a.
The negative polarity gradation voltage generation circuit 151b is based on the negative polarity quinary gradation reference voltage (V ″ 5 to V ″ 9) input from the negative voltage generation circuit 122, and has a negative gradation level of 64 gradations. A regulated voltage is generated and output to the output circuit 157 via the voltage bus line 158b.

Further, the shift register circuit 153 in the control circuit 152 of the drain driver 130 generates a data fetch signal for the input register circuit 154 based on the clock (CL2) input from the display control device 110, and the input register circuit 154. Output to.
The input register circuit 154 outputs display data of 6 bits for each color by the number of outputs in synchronization with the clock (CL2) input from the display control device 110 based on the data capturing signal output from the shift register circuit 153. Latch.

The storage register circuit 155 latches display data in the input register circuit 154 in accordance with the clock (CL1) input from the display control device 110.
The display data captured by the storage register circuit 155 is input to the output circuit 157 via the level shift circuit 156.
The output circuit 157 generates one gradation voltage corresponding to display data (one gradation in 64 gradations) based on a positive gradation voltage of 64 gradations or a negative gradation voltage of 64 gradations. The control voltage is selected and output to each drain signal line (D).

FIG. 6 is a block diagram for explaining the configuration of the drain driver 130 shown in FIG. 5, focusing on the configuration of the output circuit 157.
In FIG. 5, reference numeral 153 denotes a shift register circuit in the control circuit 152 shown in FIG. 5, 156 denotes a level shift circuit shown in FIG. 5, and the data latch unit 265 includes an input register circuit 154 and a storage register shown in FIG. Further, a switch unit (2) 264 that switches the outputs of the decoder unit (grayscale voltage selection circuit) 261, the amplifier circuit pair 263, and the amplifier circuit pair 263 constitutes the output circuit 157 shown in FIG. .
Here, the switch unit (1) 262 and the switch unit (2) 264 are controlled based on the alternating signal (M).
Y1, Y2, Y3, Y4, Y5, and Y6 indicate the first, second, third, fourth, fifth, and sixth drain signal lines (D), respectively. .

  In the Doin driver 130 shown in FIG. 6, the switch unit (1) 262 switches the data capturing signal input to the data latch unit 265 (more specifically, the input register 154 shown in FIG. 5). The display data is input to the adjacent data latch unit 265 for each color.

The decoder unit 261 selects each data latch unit 265 (more specifically, as shown in FIG. A high voltage decoder circuit 278 for selecting a positive gradation voltage corresponding to display data output from the storage register 155), and a negative polarity output from the gradation voltage generation circuit 151b via the voltage bus line 158b. And a low voltage decoder circuit 279 for selecting a negative gray scale voltage corresponding to the display data output from each data latch unit 265 from the 64 gray scale voltages.
The high voltage decoder circuit 278 and the low voltage decoder circuit 279 are provided for each adjacent data latch unit 265.

The amplifier circuit pair 263 includes a high voltage amplifier circuit 271 and a low voltage amplifier circuit 272.
The positive voltage gradation voltage generated by the high voltage decoder circuit 278 is input to the high voltage amplifier circuit 271, and the high voltage amplifier circuit 271 outputs the positive gradation voltage.
The low voltage amplifier circuit 272 receives the negative gradation voltage generated by the low voltage decoder circuit 279, and the low voltage amplifier circuit 272 outputs the negative gradation voltage.

  In the dot inversion method, the gradation voltages of adjacent colors have opposite polarities, and the arrangement of the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 of the amplifier circuit pair 263 is the high voltage amplifier circuit 271 → low. Since the voltage amplifier circuit 272 → the high voltage amplifier circuit 271 → the low voltage amplifier circuit 272, the switch unit (1) 262 switches the data capturing signal input to the data latch unit 165, so that each color is changed. Display data is input to the adjacent data latch unit 265 for each color, and the output voltage output from the high voltage amplifier circuit 271 or the low voltage amplifier circuit 272 is switched by the switch unit (2) 264 accordingly. The drain signal line (D) from which the gradation voltage for each color is output, for example, the first drain signal line (Y1) and the fourth drain signal line (Y1) By outputting rain signal line (Y4), it becomes possible to output a positive polarity or negative polarity gray scale voltages to the respective drain signal lines (D).

FIG. 7 is a circuit diagram showing a circuit configuration of one switch circuit of the switch unit (2) 264 shown in FIG.
As shown in the figure, one switch circuit of the switch unit (2) 264 shown in FIG. 6 is a PMOS transistor (PM1) connected between the high voltage amplifier circuit 271 and the nth drain signal (Yn). A PMOS transistor (PM2) connected between the high voltage amplifier circuit 271 and the (n + 3) th drain signal (Yn + 1), and a low voltage amplifier circuit 272 and the (n + 3) th drain signal (Yn + 3). And an NMOS transistor (NM2) connected between the low voltage amplifier circuit 272 and the nth drain signal (Yn).

The output of the NOR circuit (NOR1) inverted by the inverter (INV) is applied to the gate electrode of the PMOS transistor (PM1), and the NOR circuit inverted by the inverter (INV) is applied to the gate electrode of the PMOS transistor (PM2). The output of the circuit (NOR2) is level-shifted by the level shift circuit (LS) and input.
Similarly, the output of the NAND circuit (NAND2) inverted by the inverter (INV) is applied to the gate electrode of the NMOS transistor (NM1), and the output of the NAND transistor (NM2) is inverted by the inverter (INV). The output of the NAND circuit (NAND1) is level-shifted by the level shift circuit (LS) and input.
Here, the alternating signal (M) is supplied to the NAND circuit (NAND1) and the NOR circuit (NOR1), and the alternating signal is inverted by the inverter (INV) to the NAND circuit (NAND2) and the NOR circuit (NOR2). (M) is input.
The NAND circuit (NAND1, NAND2) receives the output enable signal (ENB), and the NOR circuit (NOR1, NOR2) receives the output enable signal (ENB) inverted by the inverter (INV).
Table 1 shows the truth table of the NAND circuit (NAND1, NAND2) and the NOR circuit (NOR1, NOR2), and the ON / OFF states of the MOS transistors (PM1, PM2, NM1, NM2) at that time.

As can be seen from Table 1, when the output enable signal (ENB) is at the low level (hereinafter, L level), the NAND circuit (NAND1, NAND2) is at the high level (hereinafter, H level), and the NOR circuit (NOR1, NOR2) is at It becomes L level and each MOS transistor (PM1, PM2, NM1, NM2) is turned off.
At the time of scanning line switching, both the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 are in an unstable state.
This output enable signal (ENB) is provided to prevent the output of each amplifier circuit (271, 272) from being output to each drain signal line (D) during the scanning line switching period. .
In this embodiment, an inverted signal of the clock (CL1) is used as the output enable signal (ENB), but it can also be generated internally by counting the clock (CL2). .

As can be seen from Table 1, when the output enable signal (ENB) is at the H level, each NAND circuit (NAND1, NAND2) is at the H level or the L level according to the H level or L level of the alternating signal (M). The level and each NOR circuit (NOR1) becomes H level or L level.
As a result, the PMOS transistor (PM1) and the NMOS transistor (NM1) are turned off or on, the PMOS transistor (PM2) and the NMOS transistor (NM2) are turned on or off, and the output of the high voltage amplifier circuit 271 is the drain signal line (Yn + 3). The output of the low voltage amplifier circuit 272 is the drain signal line (Yn), the output of the high voltage amplifier circuit 271 is the drain signal line (Yn), and the output of the low voltage amplifier circuit 272 is the drain signal line. Output to (Yn + 3).

Here, in the liquid crystal display module (LCM) of the present embodiment, the voltage range of the gradation voltage applied to the liquid crystal layer of each pixel is 0 to 5 V on the negative polarity side and 5 to 10 V on the positive polarity side. Accordingly, a negative gradation voltage of 0 to 5 V is output from the low voltage amplifier circuit 272, and a positive gradation voltage of 5 to 10 V is output from the high voltage amplifier circuit 271.
In this case, for example, when the PMOS transistor (PM1) is off and the NMOS transistor (NM2) is on, a voltage of 10 V at maximum is applied between the source and drain of the PMOS transistor (PM1).
Therefore, each MOS transistor (PM1, PM2, NM1, NM2) is a high voltage MOS transistor having a source-drain breakdown voltage of 10V.

In recent years, in a liquid crystal display device such as a TFT-type liquid crystal display module, the liquid crystal display panel 10 has been increased in size and resolution, and the display screen size of the liquid crystal display panel 10 has been increasing. Multi-gradation display is progressing from display to 256 gradation display.
Accordingly, the drain driver 130 is required to have a high-speed charging characteristic for the thin film transistor (TFT), and the drain driver 130 simply satisfies the above requirement by directly selecting the grayscale voltage and directly outputting the drain signal (D). It has become difficult to do.
For this reason, a method of providing an amplifier circuit at the final stage of the drain driver 130 and outputting the gradation voltage to the drain signal line (D) through the amplifier circuit has become mainstream.
The high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 shown in FIG. 6 are provided for the reasons described above. Conventionally, as the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272, For example, as shown in FIG. 8, it is configured by a voltage follower circuit in which an inverting input terminal (−) and an output terminal of an operational amplifier (OP) are directly connected and its non-inverting input terminal (+) is an input terminal. .
Further, the operational amplifier (OP) used in the low voltage amplifier circuit 272 is constituted by, for example, a differential amplifier circuit as shown in FIG. 9, and further, the operational amplifier (OP) used in the high voltage amplifier circuit 271. Is constituted by a differential amplifier circuit as shown in FIG. 10, for example.

However, in general, the operational amplifier (OP) has an offset voltage (Voff).
When the basic amplifier circuit of the operational amplifier (OP) is constituted by, for example, the differential amplifier circuit shown in FIG. 9 or FIG. 10, the offset voltage (Voff) is shown in FIG. 9 or FIG. Symmetry of the PMOS transistor (PM51, 52) or NMOS transistor (NM61, 62) in the input stage or the NMOS transistor (NM63, 64) or PMOS transistor (PM53, 54) constituting the active load circuit in the differential amplifier circuit This is caused by a subtle imbalance.
Subtle imbalance in symmetry of the PMOS transistor (PM51, 52) or NMOS transistor (NM61, 62) in the input stage, or the NMOS transistor (NM63, 64) or PMOS transistor (PM53, 54) constituting the active load circuit. The threshold voltage (Vth) of the MOS transistor or the gate width / gate length (W / L) of the MOS transistor changes due to variations in the ion implantation / ion implantation process or the photolithography process in the manufacturing process. However, it is impossible to make the offset voltage (Voff) zero even if the process control is strict.

As shown in FIG. 11, if the operational amplifier (OP) is an ideal operational amplifier having no offset voltage (Voff), the input voltage (Vin) and the output voltage (Vout) are equal (Vin). = Vout), if the operational amplifier (OP) has an offset voltage (Voff), the input voltage (Vin) and the output voltage (Vout) are not equal, and the output voltage (Vout) is The offset voltage (Voff) is added to the input voltage (Vin) (Vout = Vin + Voff).
FIG. 11 is a diagram showing an equivalent circuit of an operational amplifier considering an offset voltage (Voff). In FIG. 11, ROP is an ideal operational amplifier having no offset voltage (Voff), and VOS is its voltage. A voltage source whose value is equal to the offset voltage (Voff).

Therefore, the voltage holo shown in FIG. 8 is used as the high voltage amplifier circuit (271 shown in FIG. 6) and the low voltage amplifier circuit (272 shown in FIG. 6) of the drain driver output circuit (157 shown in FIG. 5). In the conventional liquid crystal display module using the power circuit, the input voltage and the output voltage of the voltage follower circuit do not match, and the liquid crystal driving voltage output from the voltage follower circuit to the drained signal line (D) is the voltage follower circuit. The offset voltage of the operational amplifier is added to the gradation voltage input to the power circuit.
As a result, the conventional liquid crystal display module has a problem that black or white vertical stripes are generated in the display screen displayed on the liquid crystal display panel, and the display quality is significantly impaired.

Hereinafter, the reason why the black or white vertical stripe occurs will be described in detail.
FIG. 12 illustrates the liquid crystal driving voltage applied to the drain signal line (D) (or the pixel electrode (ITO1)) when there is an offset voltage (Voff) and when there is no offset voltage (Voff). FIG.
The area A shown in the figure shows the positive and negative liquid crystal drive voltages applied to the drain signal line (D) when there is no offset voltage (Voff). In this case, the luminance of the pixel is Normal luminance corresponding to the gradation voltage is obtained.
Further, the region B shown in the figure shows the positive and negative liquid crystal drive voltages applied to the drain signal line (D) when there is a minus (−) offset voltage (Voff). Since the drive voltage applied to the pixel is lowered by the offset voltage (Voff), the luminance of the pixel corresponds to the gradation voltage if the liquid crystal display panel is a normally white type liquid crystal display panel. It becomes whiter than normal brightness.
Further, the region C shown in the figure shows the positive and negative liquid crystal drive voltages applied to the drain signal line (D) when there is a plus (+) offset voltage (Voff). Since the drive voltage applied to the pixel is increased by the offset voltage (Voff), the luminance of the pixel corresponds to the gradation voltage if the liquid crystal display panel is a normally white liquid crystal display panel. It becomes blacker than normal brightness.
Here, in the drain driver 130 shown in FIG. 6, the high-voltage amplifier circuit 271 connected to the Y1 and Y4 drain signal lines (D) has a positive (+) offset voltage (Vofh), and Y1 and Y4 The low voltage amplifier circuit 272 connected to the drain signal line (D) has a minus (−) offset voltage (Vofl), and the high voltage amplifier is connected to the drain signal lines (D) of Y2 and Y5. The circuit 271 and the low-voltage amplifier circuit 272, and the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 connected to the drain signal lines (D) of Y3 and Y6 do not have an offset voltage (Voff). If the same gradation voltage is applied to the drain signal lines (D) of Y1 to Y4, then Y1 to Y4 are applied. The luminance of the pixel connected to the 4-drain signal line (D) is as shown in FIG. 13A. If the liquid crystal display panel is a normally white liquid crystal display panel, Black vertical streaks appear.

  Further, as can be easily understood, under the above conditions, the high voltage amplifier circuit 271 connected to the drain signal lines (D) of Y1 and Y4 has a negative (−) offset voltage (Vofh), and Y1 and When the low-voltage amplifier circuit 272 connected to the Y4 drain signal line (D) has a plus (+) offset voltage (Vofl), white vertical streaks appear in the display image of the liquid crystal display panel. become.

In this case, the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 connected to the drain signal lines (D) of Y1 and Y4 have the same plus (+) or minus (−) offset voltage (Vofh). , Vofl), as shown in FIG. 13B, the pixels connected to the Y1 and Y4 drain signal lines (D) have a higher luminance than the normal luminance corresponding to the gradation voltage in the first frame. It is black, and in the second frame, it becomes whiter than the normal luminance corresponding to the gradation voltage.
As a result, the luminance of the pixels connected to the Y1 and Y4 drain signal lines (D) is canceled every two frames, so that white or black vertical stripes are not noticeable in the display image of the liquid crystal display panel.
However, the offset voltage (Voff) of the operational amplifier is randomly generated for each operational amplifier, and it is extremely rare that the two operational amplifiers have the same offset voltage (Vofh, Vofl). The voltages (Vofh, Vofl) cannot normally be the same.

Thus, in the conventional liquid crystal display module, white or black vertical stripes are generated in the display screen of the liquid crystal display panel due to the offset voltage (Voff) of the amplifier circuit connected to each drain signal line (D). There was a problem.
An offset canceller circuit is also known, but since this offset canceller circuit uses a switched capacitor circuit, grayscale voltage errors due to feedthrough, an increase in the area of the capacitor, and speeding up due to the capacity charging time can be achieved. There were problems such as limitations.

FIG. 14 is a circuit diagram showing a basic circuit configuration of the low-voltage amplifier circuit 272 in the drain driver 130 of the present embodiment, and FIG. 15 is a basic circuit of the high-voltage amplifier circuit 271 in the drain driver 130 of the present embodiment. It is a circuit diagram which shows a structure.
The low-voltage amplifier circuit 272 of the present embodiment shown in FIG. 14 is different from the differential amplifier circuit shown in FIG. 9 in that the gate electrode (control electrode) of the PMOS transistor (PM51) in the input stage is connected to the (+) input terminal or Switching transistors (NA2, NB2) that connect the switching transistor (NA1, NB1) connected to the (−) input terminal and the gate electrode of the PMOS transistor (PM52) in the input stage to the (+) input terminal or the (−) input terminal. And the gate electrode of the NMOS transistor (NM65) in the output stage are connected to the drain electrode (second electrode) of the PMOS transistor (PM51) in the input stage or the drain electrode of the PMOS transistor (PM52) in the input stage. Transistors (NA3, NB3) and an NMOS transistor constituting an active load circuit A switching transistor (NA4, NB4) for connecting the gate electrode of the register (NM63, NM64) to the drain electrode of the input stage PMOS transistor (PM51) or the drain electrode of the input stage PMOS transistor (PM52). is there.
The high voltage amplifier circuit 271 of the present embodiment shown in FIG. 15 is similar to the low voltage amplifier circuit 272 shown in FIG. 14 in that switching transistors (PA1 to PA4, PB1 to PB4) are added to the differential amplifier circuit shown in FIG. ) Is added.
Here, the control signal (A) is applied to the gate electrodes of the switching transistors (NA1 to NA4, PA1 to PA4), and the control signals are applied to the gate electrodes of the switching transistors (NB1 to NB4, PB1 to PB4). (B) is applied.

In the low voltage amplifier circuit 272 of the present embodiment shown in FIG. 14, the circuit configuration when the control signal (A) is at the H level and the control signal (B) is at the L level is shown in FIG. 16, and the control signal (A FIG. 17 shows a circuit configuration in the case where) is at the L level and the control signal (B) is at the H level.
16 and 17 also show the circuit configuration when the amplifier circuit shown in FIGS. 16 and 17 is expressed using general operational amplifier symbols.
As can be understood from FIGS. 16 and 17, in the low voltage amplifier circuit 272 of the present embodiment, the MOS transistor in the input stage to which the input voltage (Vin) is applied and the output voltage (Vout) are fed back. The input stage MOS transistors are alternately switched.
Accordingly, in the circuit configuration of FIG. 16, as shown in the following equation (1), the output voltage (Vout) is obtained by adding the offset voltage (Voff) to the input voltage (Vin).

[Equation 1]
Vout = Vin + Voff (1)
In the circuit configuration of FIG. 17, the output voltage (Vout) is obtained by subtracting the offset voltage (Voff) from the input voltage (Vin) as shown in the following equation (2).

[Equation 2]
Vout = Vin−Voff (2)
FIG. 18 is a diagram showing the configuration of the output stage of the drain driver 130 of this embodiment, and FIG. 19 is a timing chart for explaining the operation of the drain driver 130 of this embodiment.
The output voltage shown in FIG. 19 corresponds to the drain signal line (D) connected to the high voltage amplifier circuit 271 having the offset voltage Vofh and the low voltage amplifier circuit 272 having the offset voltage Vofh. The output voltage output from the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 is shown. In this output voltage, VH is the high-voltage amplifier when the high-voltage amplifier circuit 271 does not have an offset voltage. A normal gradation voltage VL output from the circuit 271 is a normal gradation voltage output from the low voltage amplifier circuit 272 when the low voltage amplifier circuit 272 does not have an offset voltage.

Further, as shown in the time chart of FIG. 19, the phases of the control signal (A) and the control signal (B) output from the control circuit 152 shown in FIG. 18 are inverted every two frames.
Accordingly, as shown in FIG. 19, the drain signal line (D) connected to the high voltage amplifier circuit 271 having the offset voltage of Vofh and the low voltage amplifier circuit 272 having the offset voltage of Vofh has 1 The voltage of (VH + Vofh) is output from the high voltage amplifier circuit 271 to the first line of the frame, while the voltage of (VH−Vofh) is output from the high voltage amplifier circuit 271 to the first line of the third frame. Therefore, the increase and decrease in luminance caused by the offset voltage (Vofh) of the high voltage amplifier circuit 271 are canceled out in the corresponding pixel.
Further, the voltage (VL + Vofl) is output from the low voltage amplifier circuit 272 to the first line of the second frame, but the voltage (VL−Vofl) is output from the low voltage amplifier circuit 272 to the first line of the fourth frame. Therefore, the increase and decrease in luminance caused by the offset voltage (Vofl) of the low-voltage amplifier circuit 272 are canceled out in the corresponding pixel.
As a result, as shown in FIG. 20, the increase and decrease in luminance caused by the offset voltages (Vofh, Vofl) of the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 are offset every four consecutive frames. The luminance of the pixel to which the output voltage shown in FIG. 19 is applied is normal luminance corresponding to the gradation voltage.

In the time chart shown in FIG. 19, the phases of the control signal (A) and the control signal (B) are inverted every two frames. However, the phases of the control signal (A) and the control signal (B) are reversed. May be reversed every two lines and every two frames within each frame. The luminance of the pixel in this case is shown in FIGS.
FIG. 21 shows that when the control signal (A) is at the H level, the high voltage amplifier circuit 271 generates the (+) offset voltage (Vofh) and the low voltage amplifier circuit 272 displays the (+) offset voltage (Vofl). FIG. 22 shows a case where the high voltage amplifier circuit 271 has a (+) offset voltage (Vofh) and the low voltage amplifier circuit 272 has a (−) when the control signal (A) is at the H level. The offset voltage (Vofl) is.
In any case, the increase and decrease in luminance caused by the offset voltages (Vofh, Vofl) of the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 are offset every four consecutive frames. Is a normal luminance corresponding to the gradation voltage.
However, by inverting the phases of the control signal (A) and the control signal (B) every two lines in each frame, the luminance of the pixel in the column direction is 2 lines as shown in FIGS. Since black changes to white (or white → black) every time, vertical stripes are less noticeable in the display screen displayed on the liquid crystal display panel 10.
In FIG. 21 or FIG. 22, the luminance of the pixels in the column direction is changed by inverting the phases of the control signal (A) and the control signal (B) every two lines within one frame, thereby making the vertical stripes conspicuous. Needless to say, it does not have to be every two lines.

Hereinafter, in the present embodiment, a method for generating the control signal (A) and the control signal (B) will be described.
FIG. 23 is a block diagram showing a main circuit configuration in the control circuit 152 in the drain driver 130 of the present embodiment.
As shown in the figure, a control circuit 152 in the drain driver 130 of this embodiment includes a shift register 153, a control signal generation circuit 400, a frame recognition signal generation circuit 410, a shift clock enable signal generation circuit 420, and a shift. A clock generation circuit 430, a pulse generation circuit 440, and a pulse selection circuit 450 are provided.

24 is a circuit diagram showing a circuit configuration of the control signal generation circuit 400 shown in FIG. 23, and FIG. 25 is a time chart for explaining the operation of the control signal generation circuit 400 shown in FIG.
A clock (CL1) is input to the control signal generation circuit 400. As shown in FIG. 25, the clock (CL1) is divided by two by a D-type flip-flop circuit (F1) to become a clock (HCL1). Further, this clock (HCL1) is converted to a D-type flip-flop circuit (HCL1). F2) is divided by 2, and the clock (CL1) is divided by 4 to obtain a clock (QCL1).
In addition, a frame recognition signal (FLMN) for recognizing each frame is input to this control signal generation circuit. A method for generating the frame recognition signal (FLMN) will be described later.
The frame recognition signal (FLMN) is inverted by an inverter (INV) to become a signal (FLMIP). As shown in FIG. 25, this signal (FLMIP) is divided by two by a D-type flip-flop circuit (F3) to become a signal (HCL1). Further, this signal (HCL1) is a D-type flip-flop circuit. The frame recognition signal (FLMN) is divided by 4 by (F4) to become a signal (QFLM) obtained by dividing the frequency by 4.
The clock (QCL1) and the signal (QFLM) are input to an exclusive OR circuit (EXOR1), and a signal (CHOPA) is output from the exclusive OR circuit (EXOR1), and this signal (CHOPA) ) Is inverted by an inverter (INV) to generate a signal (CHOPB).
The signals (CHOPA, CHOPB) are level-shifted by a level shift circuit to become a control signal (A) and a control signal (B).

Thereby, the phases of the control signal (A) and the control signal (B) can be inverted every two lines and every two frames in each frame.
When the phases of the control signal (A) and the control signal (B) are inverted every two frames, a signal (QFLM) obtained by dividing the frame recognition signal (FLMN) by 4 is defined as a signal (CHOPA). Further, the signal (CHOPA) may be inverted by an inverter (INV) to be a signal (CHOPP).
In this case, in the control signal generation circuit 400 shown in FIG. 24, the D-type flip-flop circuits (F1, F2) and the exclusive OR circuit (EXOR1) are not necessary.
In this control signal generation circuit 400, the D-type flip-flop circuits (F1, F2) are initialized with the frame recognition signal (FLMN).
On the other hand, the D-type flip-flop circuit (F3, F4) is initialized by the signal (PORN) from the PORN signal generation circuit 401.
The PORN signal generation circuit 401 includes a voltage dividing circuit 402 that divides a high power supply voltage (VDD), and an inverter circuit group 403 to which an output of the voltage dividing circuit 402 is input.
This power supply voltage (VDD) is a voltage generated by a DC / DC converter (not shown) in the power supply circuit 120 shown in FIG. 1, and this power supply voltage (VDD) is supplied to the liquid crystal display module. After a while, I get up.
Therefore, after the power of the liquid crystal display module is turned on, the signal (PORN) of the PORN signal generation circuit 401 becomes L level for a while, so that the D-type flip-flop circuits (F3, F4) It is surely initialized at the time of input.

Next, a method for generating a frame recognition signal (FLMN) in the present embodiment will be described.
In order to generate the frame recognition signal (FLMN), a signal for recognizing frame switching is required.
Since the frame start instruction signal is output from the display control device 110 to the gate driver 140, if this frame start instruction signal is also input to the drain driver 130, the frame recognition signal (FLMN) can be easily obtained. Can be generated.
However, in this method, it is necessary to increase the number of input pins of the semiconductor integrated circuit (semiconductor chip) constituting the drain driver 130, and thus, it is necessary to change the wiring pattern of the printed wiring board.
And with the change of the wiring pattern of the printed wiring board, the high-frequency noise characteristics generated by the liquid crystal display module change, and there is a concern that the EMI (electromagnetic interference) level is lowered.
Further, increasing the number of input pins of the semiconductor integrated circuit makes the input pins incompatible.

  Therefore, in the present embodiment, the pulse width of the start pulse output from the display control device 110 to the drain driver 130 is the first start pulse in the frame (hereinafter referred to as a frame start pulse) for each frame. This is different from other start pulses (hereinafter referred to as intra-frame start pulses), whereby the switching of each frame is recognized and a frame recognition signal (FLMN) is generated.

26 is a circuit diagram showing a circuit configuration of the frame recognition signal generation circuit 410 shown in FIG. 23, and FIG. 27 is a time chart for explaining the operation of the frame recognition signal generation circuit 410 shown in FIG.
In this embodiment, it is assumed that the frame start pulse has a pulse width corresponding to four cycles of the clock signal (CL2), and the intra-frame start pulse has a pulse width corresponding to one cycle of the clock signal (CL2).
In FIG. 26, in the D-type flip-flop circuits (F11 to F13), the clock (CL2) is input to the clock signal input terminal.
Therefore, the start pulse is latched in the D-type flip-flop circuit (F11) in synchronization with the clock (CL2) and becomes a signal (STEIO).
This signal (STEIO) is latched by the D-type flip-flop circuit (F12) in synchronization with the clock (CL2) to become the signal (Q1). Further, this signal (Q1) is synchronized with the clock (CL2). And is latched by the D-type flip-flop circuit (F13) to become a signal (Q2).
This signal (Q2) is input to the clock signal input terminal of the D-type flip-flop circuit (F14), and the signal (STEIO) is input to the data input terminal (D) of the D-type flip-flop circuit (F14). Is entered.
Therefore, if the start pulse is a frame start pulse having a pulse width corresponding to four cycles of the clock signal (CL2), the Q output of the D-type flip-flop circuit (F14) becomes H level.
Here, since the Q output of the D-type flip-flop circuit (F14) becomes the start pulse selection signal (FSTENBP) for the next drain driver, the start pulse selection signal (FSTENBP) becomes the H level.
The Q output of the D-type flip-flop circuit (F14) and the signal (STEIO) are input to the NAND circuit (NAND11), and the output of the NAND circuit (NAND11) becomes the frame recognition signal (FLMN). Therefore, the frame recognition signal (FLMN) becomes L level for two cycles of the clock (CL2).
On the other hand, if the start pulse is an intra-frame start pulse having a pulse width corresponding to one cycle of the clock signal (CL2), the Q output of the D-type flip-flop circuit (F14) becomes L level.
As a result, the start pulse selection signal (FSTENBP) becomes L level, and the frame recognition signal (FLMN) maintains H level.

Each D-type flip-flop circuit (F11 to F14) is initialized by a signal (RESETN).
In this embodiment, an inverted signal of the clock (CL1) is used as this signal (RESETN).
In this embodiment, the case where the frame start pulse has a pulse width corresponding to four cycles of the clock signal (CL2) has been described. However, the present invention is not limited to this, and the frame start pulse is input. If the frame recognition signal (FLMN) that is at the L level for a predetermined period can be generated only when the frame start pulse is generated, the pulse width of the frame start pulse can be set arbitrarily.

In the present embodiment, the first drain driver 130 receives a frame start pulse and an intra-frame start pulse from the display control device 110, and performs the above-described operation.
However, since the frame start pulse and the intra-frame start pulse are not input to the second and subsequent drain drivers 130 from the display control device 110, the second and subsequent drain drivers 130 also perform the above-described operation. In this case, it is necessary to output a pulse having the same pulse width as the input start pulse to the next drain driver 130 as a start pulse.
Therefore, in this embodiment, the pulse generation circuit 440 illustrated in FIG. 23 generates a frame start pulse having a pulse width corresponding to four cycles of the clock signal (CL2), and the input start pulse is the frame start pulse. In this case, the frame start pulse generated by the pulse generation circuit 440 is sent to the next drain driver 130.

Hereinafter, a method of generating the frame start pulse and the frame start pulse in the drain driver 130 will be described.
FIG. 28 is a time chart for explaining the operation of the control circuit 152 in the drain driver 130 of the present embodiment shown in FIG.
As shown in FIG. 28, the shift clock enable signal generation circuit 420 outputs an H level enable signal (EENB) to the shift clock generation circuit 430 when a start pulse is input.
Accordingly, the shift clock generation circuit 430 generates a shift clock synchronized with the clock (CL2) and outputs the shift clock to the shift register circuit 153.
Each flip-flop circuit of the shift register circuit 153 sequentially outputs data capture signals (SFT1 to SFTn + 3), whereby display data is latched in the input register 154.
The SFTn data capture signal is a start pulse in the frame of the drain driver 130 at the next stage having a pulse width of one cycle of the clock (CL2).
Here, the data capture signals of SFT1 to SFTn are used to latch the 1st to nth display data in the input register 154, but the data capture signals of SFTn + 1 to SFTn + 3 are displayed on the input register 154. It is not used to latch data.
The data capture signals SFTn + 1 to SFTn + 3 are used to generate a frame start pulse for the drain driver 130 at the next stage.
That is, as shown in FIG. 28, the clock generation circuit 450 generates a frame start pulse having a pulse width corresponding to four cycles of the clock (CL2) based on the data capture signals SFTn to SFTn + 3.
As described above, if the start pulse is an intra-frame start pulse, the start pulse selection signal (FSTENBP) is at the L level, so that the pulse selection circuit 450 uses the intra-frame start pulse (that is, the signal for capturing data of SFTn) Is output to the next drain driver 130.
On the other hand, if the start pulse is a frame start pulse, the start pulse selection signal (FSTENBP) is at the H level, and the pulse selection circuit 450 selects the frame start pulse and outputs it to the next drain driver 130.

Here, as the clock generation circuit 450, for example, the one shown in FIG. 29 can be used.
The clock generation circuit 450 shown in FIG. 29 inverts the Q output of the D-type flip-flop circuit (F21) based on the data acquisition signal of SFTn, and also acquires the data of SFTn + 3 inverted by the inverter (INV). Based on the signal, the Q output of the D-type flip-flop circuit (F22) is inverted.
Further, the Q output of the flip-flop circuit of F21 and F22 is input to the exclusive OR circuit (EXOR2), and the frame has a pulse width corresponding to four cycles of the clock (CL2) from the exclusive OR circuit (EXOR2). Start pulses are generated.

  As described above, in this embodiment, since the start pulse for frame and the start pulse for frame are generated in each drain driver 130, the input of the semiconductor integrated circuit constituting the drain driver 130 is thereby generated. Each drain driver 130 can recognize the switching of each frame while maintaining the compatibility of the input pins without increasing the number of pins.

FIG. 30 is a main part layout diagram showing an arrangement of each part in the semiconductor integrated circuit constituting the drain driver 130 of the present embodiment.
As shown in the figure, the semiconductor integrated circuit constituting the drain driver 130 of this embodiment is provided with a terminal portion connected to the drain signal line (D) in the longitudinal direction of the semiconductor integrated circuit. A data latch portion 265, a level shift circuit 156, a decoder portion 261, and an amplifier circuit pair 263 are provided in the short direction.

Conventionally, the level shift circuit 156 has a circuit configuration as shown in FIG.
In this case, the level shift circuit 156 needs to convert the input voltage of 0V to 5V to a voltage of 0V to 10V and output it. Therefore, in the level shift circuit shown in FIG. It was necessary to use high voltage MOS transistors (PSB1, PSB2, NSB1, NSB2) having a withstand voltage of 10V.
This high breakdown voltage MOS transistor with a source-drain breakdown voltage of 10 V requires a longer gate length and a larger current value than a low breakdown voltage MOS transistor with a source-drain breakdown voltage of 5 V. The width is also increased.
Therefore, if a level shift circuit using high breakdown voltage MOS transistors (PSB1, PSB2, NSB1, NSB2) having a breakdown voltage of 10V between the source and the drain is used as the level shift circuit 156, the semiconductor integrated circuit constituting the drain driver 130 is used. As a result, the area of the level shift circuit 156 increases, and accordingly, the chip size of the short method of the semiconductor integrated circuit constituting the drain driver 130 increases, the chip unit price cannot be reduced, and the frame is narrowed. There was a problem that it could not be handled.

FIG. 32 is a circuit diagram showing a configuration of a level shift circuit used in the level shift circuit 156 of the present embodiment.
The level shift circuit shown in FIG. 32 includes a series circuit of a voltage drop PMOS transistor (PSA3) and an NMOS transistor (NSA3) between the PMOS transistor (PSA1) and the NMOS transistor (NSA1). The level shift circuit shown in FIG. 31 is connected in that a series circuit of a voltage drop PMOS transistor (PSA4) and an NMOS transistor (NSA4) is inserted between (PSA2) and the NMOS transistor (NSA2). Is different.
Here, an intermediate bias potential (Vbis) between the VDD power supply potential and the reference potential (GND) is applied to the gate electrodes of the PMOS transistors (PSA3, PSA4) and NMOS transistors (NSA3, NSA4). Is done.

FIG. 33 is a diagram showing voltage waveforms at various parts of the level shift circuit shown in FIG. 32. FIG. 33 shows a case where the power supply potential (VDD) is 8V, the bias potential (Vbis) is 4V, and the input voltage is 0V to 4V. It is a figure which shows the waveform of each part.
Hereinafter, the operation of the level shift circuit shown in FIG. 32 will be described with reference to FIG.
Now, when the input voltage is H level of 4V, 4V is applied to the gate electrode of the NMOS transistor (NSA1), and 0V (input voltage inverted by the inverter) is applied to the gate electrode of the NMOS transistor (NSA2). Is applied, the NMOS transistor (NSA1) is turned on and the NMOS transistor (NSA2) is turned off.
Accordingly, the potential at the point (a) shown in FIG. 32 is 0V, and the bias voltage (Vbis) of 4V is applied to the gate electrode of the NMOS transistor (NSA3), so the NMOS transistor (NSA3) is turned on. The potential at point (c) shown in FIG. 32 is also 0V.

Further, when the potential at the point (c) shown in FIG. 32 becomes 0V, since the bias potential (Vbis) of 4V is also applied to the gate electrode of the PMOS transistor (PSA3), the source electrode of the PMOS transistor (PSA3) The source potential drops.
Since the source potential of the PMOS transistor (PSA3) is applied to the gate electrode of the PMOS transistor (PSA2), the PMOS transistor (PSA2) is turned on, and the potential at the point (b ′) shown in FIG. It becomes.
When the potential at the point (b ′) shown in FIG. 32 becomes 8V, the PMOS transistor (PSA1) to which the potential at the point (b ′) is applied to the gate electrode is turned off.
When the PMOS transistor (PSA1) is turned off, no current flows through the series circuit of the PMOS transistors (PSA1, PSA3) and the NMOS transistors (NSA1, NSA3), so the source electrode of the PMOS transistor (PSA3) The source potential (VPS) is expressed by the following equation (3).

[Equation 3]
VPGS + VPth = 0
VPG-VPS + VPth = 0
VPS = VPG + VPth (3)
Where VPGS is the gate-source voltage of the PMOS transistor (PSA3), VPG is the gate potential of the PMOS transistor (PSA3), and VPth is the threshold voltage.
Therefore, the potential at the point (b) shown in FIG. 32, that is, the source potential (VPS) of the PMOS transistor (PSA3) becomes a voltage obtained by adding the threshold voltage (VPth) to the gate potential (VPG), and the PMOS transistor ( The source potential (VPS) of PSA3) is approximately equal to its gate potential (VPG) (= 4V).
Since the source voltage (VPS) of the PMOS transistor (PSA3) is equal to the drain voltage (VPD) of the drain electrode of the PMOS transistor (PSA1), the PMOS transistor (PSA1) and the PMOS transistor (PSA3) have a source-drain breakdown voltage. However, it is possible to use a low-voltage PMOS transistor with 5V.

Further, when the PMOS transistor (PSA2) is turned on, the PMOS transistor (PSA4) is turned on, and the potential at the point (c ′) shown in FIG. 32 becomes 8V.
Furthermore, since the NMOS transistor (NSA2) is off and no current flows through the series circuit of the transistors composed of the PMOS transistors (PSA2, PSA4) and the NMOS transistors (NSA2, NSA4), the source electrode of the NMOS transistor (NSA4) The source potential (VNS) is expressed by the following equation (4).

[Equation 4]
VNGS−VNth = 0
VNG−VNS−VNth = 0
VNS = VNG−VNth (4)
Where VNGS is the gate-source voltage of the NMOS transistor (NSA4), VNG is the gate potential of the NMOS transistor (NSA4), and VNth is the threshold voltage.
Therefore, the potential at the point (a ′) shown in FIG. 32, that is, the source potential (VNS) of the NMOS transistor (NSA4) is a voltage obtained by subtracting the threshold voltage (VNth) from the gate potential (VNG). The source potential (VNS) of the transistor (NSA4) is approximately equal to its gate potential (VNG) (= 4V).
Since the source voltage (VNS) of the NMOS transistor (NSA4) is equal to the drain voltage (VND) of the drain electrode of the NMOS transistor (NSA2), the NMOS transistor (NSA2) and the NMOS transistor (NSA4) have a source-drain breakdown voltage. However, it is possible to use a low-breakdown-voltage NMOS transistor of 5V.

32, when the point (a) is 0V and the point (b) is 4V, the PMOS transistor (PBP1) of the inverter circuit (INVP) is turned on and the NMOS transistor (NBP1) is turned off.
A series circuit of a PMOS transistor (PBP2) and an NMOS transistor (NBP2) is inserted between the PMOS transistor (PBP1) and the NMOS transistor (NBP1) of the inverter circuit (INVP). Since a bias potential (Vbis) of 4V is applied to the gate electrode of NBP2), the output (Q) is 8V.
In this case, as described above, the source potential of the NMOS transistor (NBP2) becomes substantially equal to the gate potential thereof, so that the NMOS-transistor (NBP1) and the NMOS transistor (NBP2) have a low breakdown voltage of 5V between the source and drain. An NMOS transistor can be used.
Similarly, when the PMOS transistor (PBP1) of the inverter circuit (INVP) is off and the NMOS transistor (NBP1) is on, the source potential of the PMOS transistor (PBP2) is substantially equal to its gate potential. As the (PBP1) and the NMOS transistor (PBP2), it is possible to use a low breakdown voltage PMOS transistor having a source-drain breakdown voltage of 5V.
Thereby, in this embodiment, the area occupied by the level shift circuit 156 in the semiconductor integrated circuit constituting the drain driver 130 can be reduced, and the length in the short direction of the semiconductor integrated circuit can be reduced. Is possible.

FIG. 34 is a schematic diagram for explaining a region occupied by the level shift circuit 156 in the semiconductor integrated circuit constituting the drain driver 130 of the present embodiment.
In the figure, D (0) to D (5) are latch circuits in the data latch unit 265 that latch each bit value of display data, and LS (0) to LS (5) are latch circuits (D (0 ) To D (5)) is a level shift circuit in the level shift circuit 156.
As shown in FIG. 34, when the conventional level shift circuit is employed, it is necessary to use a high voltage MOS transistor having a source-drain breakdown voltage of 8V, which increases the area of the level shift circuit, and It was necessary to place two level shift circuits on top of each other for every two latch circuits.
However, in the level shift circuit according to the present embodiment, a low breakdown voltage MOS transistor having a source-drain breakdown voltage of 5 V can be used, so that the area of the level shift circuit can be reduced. It is possible to arrange two level shift circuits in the area occupied by one conventional level shift circuit.

Therefore, as shown in FIG. 34, in the present embodiment, one level shift circuit can be arranged for each latch circuit in the data latch unit 265.
Therefore, in the present embodiment, it is possible to shorten the length in the short direction of the semiconductor integrated circuit constituting the drain driver 130 by the length of (L1) shown in FIG. It becomes possible to cope with the narrowing of the frame.

FIG. 35 is a main-portion cross-sectional view showing a cross-sectional structure of the PMOS transistors (PSA1, PSA3) and NMOS transistors (NSA1, NSA3) shown in FIG.
As shown in the figure, an n-well region 21 is formed in a p-type semiconductor substrate 20, and each p-type semiconductor region (25a, 25b, 25c) formed in the n-well region 21 and a gate electrode (27a, 27b) constitutes PMOS transistors (PSA1, PSA3).
In this case, the p-type semiconductor region (25b) serves as both the drain region of the PMOS transistor (PSA1) and the source region of the PMOS transistor (PSA3).
Further, a p-well region 22 is formed in the p-type semiconductor substrate 20, and each n-type semiconductor region (24a, 24b, 24c) formed in the p-well region 22 and a gate electrode (26a, 26b) form an NMOS. Transistors (NSA1, NSA3) are formed.
In this case, the n-type semiconductor region (24b) serves as both the drain region of the NMOS transistor (NSA1) and the source region of the NMOS transistor (NSA3).
Here, a voltage of 0 V is applied to the p-type semiconductor substrate 20, a voltage of 0 V is applied to the p well region 22, and a voltage of 8 V is applied to the n well region 21.

  Therefore, a reverse voltage of 8 V at the maximum is applied between the n-type semiconductor region (24c) and the p-well region 22, and between the p-type semiconductor region (25c) and the n-well region 21, so this portion If the withstand voltage is not sufficient, it is necessary to improve the withstand voltage of this portion by, for example, a double drain structure (DDD).

[Embodiment 2]
In the liquid crystal display module according to the second embodiment of the present invention, the number of transistors constituting the high voltage decoder circuit 278 or the low voltage decoder circuit 279 in the drain driver 130 is reduced. 1 and the liquid crystal display module.
Hereinafter, the drain driver 130 of the present embodiment will be described focusing on the differences from the first embodiment.

FIG. 36 is a circuit diagram showing circuit configurations of the high voltage decoder circuit 278 and the low voltage decoder circuit 279 in the drain driver 130 of the first embodiment. FIG. 36 also shows schematic circuit configurations of the positive gradation voltage generation circuit 151a and the negative gradation voltage generation circuit 151b.
The high voltage decoder circuit 278 has 64 transistor rows (TRP2) composed of 6 high voltage PMOS transistors and 6 high voltage depletion PMOS transistors connected in series to the output terminal. A gradation voltage for 64 gradations of positive polarity output from the gradation voltage generation circuit 151a via the voltage bus line 158a is input to a terminal opposite to the output terminal of the transistor array (TRP2).
In addition, 6-bit display data output from the level shift circuit 156 is provided on the gate electrodes of the six high-breakdown-voltage PMOS transistors and the six high-breakdown-voltage depletion PMOS transistors that constitute each transistor row (TRP2). Each bit value (T) or its inverted bit value (B) is selectively applied based on a predetermined combination.

The low-voltage decoder circuit 279 has 64 transistor rows (TRP3) composed of 6 high-voltage NMOS transistors and 6 high-voltage depletion NMOS transistors connected in series to the output terminal. To the terminal opposite to the output terminal of the transistor array (TRP3), the gradation voltage for 64 gradations of negative polarity output from the gradation voltage generation circuit 151b via the voltage bus line 158b is input.
In addition, 6-bit display data output from the level shift circuit 156 is provided at the gate electrodes of the six high-breakdown-voltage NMOS transistors and the six high-breakdown-voltage depletion NMOS transistors that constitute each transistor row (TRP3). Each bit value (T) or its inverted bit value (B) is selectively applied based on a predetermined combination.

As described above, the high voltage decoder circuit 278 and the low voltage decoder circuit 279 according to the first embodiment have a configuration in which 12 MOS transistors are cascade-connected for every 64 gradations.
Therefore, the total number of MOS transistors per drain signal line (D) is 768 (64 × 12).

In recent years, in a liquid crystal display device, multi-gradation display is progressing from 64 gradation display to 256 gradation display. However, when 256 gradation display is performed using the conventional high voltage decoder circuit 278 and low voltage decoder circuit 279, the total number of MOS transistors per drain signal line (D) is 4096 ( 256 × 16).
For this reason, there is a problem that the area occupied by the decoder unit 261 increases, and the chip size of the semiconductor integrated circuit (IC chip) constituting the drain driver 130 increases.

FIG. 37 is a circuit diagram showing a circuit configuration of the high-voltage decoder circuit 278 and the positive gradation voltage generation circuit 151a in the drain driver 130 of the second embodiment.
As shown in the figure, the positive polarity gradation voltage generation circuit 151a does not generate the gradation voltage of 64 gradations as in the first embodiment, but has a positive polarity input from the positive voltage generation circuit 121. Based on the five-level gradation reference voltage (V ″ 0 to V ″ 4), a positive first gradation voltage of 17 gradations is generated.
In this case, each of the voltage dividing resistors of the resistance voltage dividing circuit that constitutes the positive polarity gradation voltage generating circuit 151a is weighted according to the relationship between the voltage applied to the liquid crystal layer and the transmittance.
The high-voltage decoder circuit 278 includes a decoder circuit 301 that selects the first gradation voltages (VOUTA and VOUTB) adjacent to each other of the first gradation voltage of 17 gradations, and the first floor selected by the decoder circuit 301. The multiplexer 302 outputs the regulated voltage (VOUTA) to the terminal (P1) or the terminal (P2), and the first gradation voltage (VOUTB) selected by the decoder circuit 301 to the terminal (P2) or the terminal (P1). And the potential difference (ΔV) between the adjacent first gradation voltages (VOUTA, VOUTB) output from the multiplexer 302 is divided into Va, Va + 1 / 4ΔV, Va + 2/4 (= 1/2) ΔV, A second gradation voltage generation circuit 303 that generates a voltage of Va + 3 / 4ΔV.

The decoder circuit 301 has an even number of first decoder circuits 311 for selecting a first gradation voltage corresponding to the upper 4 bits (D2 to D5) of 6-bit display data from among odd-numbered first gradation voltages. The second decoder circuit 312 selects the first gradation voltage corresponding to the upper 3 bits (D3 to D5) of the 6-bit display data from the first first gradation voltage.
The first decoder circuit 311 generates the first first gradation voltage (V1) and the seventeenth first gradation voltage (V17) according to the upper 4 bits (D2 to D5) of the 6-bit display data. The third gray scale voltage (V3) through the fifteenth gray scale voltage (V15) are selected once and twice in succession.
However, the second decoder circuit 312 uses the upper 3 bits (D3 to D5) of the 6-bit display data to change from the second first gradation voltage (V2) to the sixteenth first gradation voltage (V16). Are selected once.
In FIG. 37, ◯ is a switch element (eg, a PMOS transistor) that is turned on when the data bit is at L level, and ● is a switch element (eg, an NMOS transistor) that is turned on when the data bit is at H level. is there.

Here, since V "0 <V" 1 <V "2 <V" 3 <V "4, if the bit value of 3 bits (D2) of the display data is L level, the gradation voltage VOUTA is VOUTB. When a gradation voltage having a lower potential than the gradation voltage of the output data is output and the bit value of the 3 bits (D2) of the display data is H level, the gradation voltage VOUTA is higher than the gradation voltage of VOUTB. Is output.
Therefore, the multiplexer 302 is switched according to the H level and L level of the 3rd bit (D2) bit value of the display data, and the terminal (P1) when the 3rd bit (D2) bit value of the display data is at the L level. Is output to the terminal (P2), and the gradation value of VOUTB is output to the terminal (P1) when the bit value of the third bit (D2) of the display data is H level. The voltage is output to the terminal (P2) as a gradation voltage of VOUTA.
Thereby, when the gradation voltage of the terminal (P1) is (Va) and the gradation voltage of the terminal (P2) is (Vb), Va <Vb can always be established, and the second gradation voltage generation circuit The design of 303 is simplified.

The second gradation voltage generation circuit 303 includes a switch element (S1) connected between the terminal (P1) and the input terminal of the high voltage amplifier circuit 271, and one end connected to the input terminal of the high voltage amplifier circuit 271. A capacitor (C1) connected to the terminal (P1) via the switch element (S2) and the other end connected to the terminal (P2) via the switch element (S5); A capacitor (C2) connected to the input end of the amplifier circuit 271 and the other end connected to the terminal (P1) via the switch element (S3) and to the terminal (P2) via the switch element (S4). And a capacitor (C3) connected between the terminal (P2) and the input terminal of the high voltage amplifier circuit 271.
Here, the capacitance values of the capacitor (C1) and the capacitor (C3) are the same, and the capacitance value of the capacitor (C2) is twice the capacitance value of the capacitors (C1) and (C3). .
Further, as shown in FIG. 38, each switch element (S1 to S5) is turned on / off according to the bit value of the lower 2 bits (D0, D1) of the display data.
In FIG. 38, the grayscale voltage value output from the second grayscale voltage generation circuit 303 and the lower 2 bits of the display data according to the bit values of the lower 2 bits (D0, D1) of the display data are shown. The circuit configuration of the second gradation voltage generation circuit 303 corresponding to the bit value of (D0, D1) is also shown.

The low-voltage decoder circuit 279 can be configured in the same manner as the high-voltage decoder circuit 278. In this case, the low-voltage decoder circuit 279 has a negative polarity generated from the negative polarity gradation voltage generation circuit 151b. A first gradation voltage of 17 gradations is selected.
Further, the negative polarity gradation voltage generation circuit 151b is based on the negative polarity quinary gradation reference voltage (V ″ 5 to V ″ 9) input from the negative voltage generation circuit 122 and has 17 negative gradations. In addition, each voltage dividing resistor of the resistance voltage dividing circuit constituting the negative gradation voltage generating circuit 151b is predetermined according to the relationship between the voltage applied to the liquid crystal layer and the transmittance. Is weighted.
In this low voltage decoder circuit 279, V ″ 5> V ″ 6> V ″ 7> V ″ 8> V ″ 9, so that the gradation voltage of the terminal (P1) is (Va) and the terminal (P2). When the gradation voltage is (Vb), Va> Vb is always satisfied.

FIG. 39 shows the second embodiment when the high voltage decoder circuit 278 shown in FIG. 37 and the low voltage decoder circuit 279 having the same circuit configuration as the high voltage decoder circuit 278 shown in FIG. It is a figure which shows schematic structure of the output stage in the drain driver 130 of a liquid crystal display module.
In the figure, an amplifier circuit having the circuit configuration shown in FIG. 15 is used for the high voltage amplifier circuit 271, and an amplifier circuit having the circuit configuration shown in FIG. 14 is used for the low voltage amplifier circuit 272.
Thus, in this embodiment, the switching elements constituting the decoder circuit are 64 (= (9 + 7) × 4) in the first decoder circuit 311, and 24 (= 3 × 8) in the second decoder circuit 312. Therefore, the total number of switching elements (MOS transistors) constituting the decoder circuit per drain signal line (D) is 88, and the total number of MOS transistors per drain signal line (D) in the first embodiment is 768. Compared to this, it is possible to significantly reduce the number.
Further, since the internal current of the drain driver 130 can be reduced by reducing the switching elements, the power consumption of the entire liquid crystal display module (LCM) can be reduced, and thereby the liquid crystal display module (LCM). It becomes possible to improve the reliability.

  FIG. 40 is a circuit diagram showing another example of the circuit configuration of the high-voltage decoder circuit 278 in the drain driver 130 of this embodiment. In FIG. 40, a circle indicates a PMOS transistor, and a circle indicates an NMOS transistor. ing.

  Note that FIG. 40 shows an example of a circuit configuration in the case of generating a gradation voltage of 256 gradations. For this reason, each bit value of (D0 to D7) 8-bit display data and its inverted value are predetermined. The voltage is applied to the gate electrode of each PMOS transistor based on the combination.

In the high voltage decoder circuit 278 shown in FIG. 37, the MOS transistors to which the same voltage is applied to the gate electrode for each decode row are continuous as the upper bits of the display data.
Therefore, there is no functional problem even if the same voltage is applied to the gate electrode for each digit and the MOS transistor continuous for each decode row is replaced with one MOS transistor.

In the high voltage decoder circuit 278 shown in FIG. 40, the same voltage is applied to the gate electrode for each digit, and the continuous MOS transistor for each decode row is replaced with one MOS transistor.
Further, in the high-voltage decoder circuit 278 shown in FIG. 40, when the gate width of the gate electrode of the minimum size MOS transistor is W, the gate width of the MOS transistor of the upper digit of the minimum size MOS transistor is 2 W, and the gate width of the gate electrode of the upper digit MOS transistor is 4 W, and the gate width (W of the gate electrode of the MOS transistor (the upper bit side MOS transistor) to which the upper bit of the display data is applied to the gate electrode. ) Is 2 (m−j) times the gate width of the gate electrode of the MOS transistor of the minimum size.
Here, m is the number of bits of display data, and j is the bit number of the most significant bit among the bits composed of MOS transistors of the minimum size.

In the high voltage decoder circuit 278 shown in FIG. 40, when the resistance of the MOS transistor of the minimum size is R, the combined resistance of the MOS transistors in each decode row is about 2R (≈R + R / 2 + R / 4 + R / 8 + R / 16) and about 2R (≈R + R / 2 + R / 4 + R / 8) in the decoder circuit 312.
FIG. 40 also shows the resistances of the MOS transistors in each digit when the resistance of the MOS transistor of the minimum size is R.
Therefore, in the high voltage decoder circuit 278 shown in FIG. 40, the combined resistance of the MOS transistors in each decode row can be reduced, and when the charge is redistributed to each capacitor constituting the second gradation voltage generation circuit 303. Therefore, the decoder circuit can be speeded up and the combined resistance values of the decoder circuit 311 and the decoder circuit 312 can be made equal, so that the speed of the generated two gradations can be increased. The difference can be reduced.

  In general, in a MOS transistor, the threshold voltage (Vth) changes in the positive direction due to the substrate-source voltage (VBS), thereby reducing the drain current (IDS). That is, the resistance of the MOS transistor increases.

Therefore, in the high-voltage decoder circuit 278 shown in FIG. 40, the gradation voltage (V16 (or V18), V15 (or V17) gradation voltage in FIG. 40) is equivalent to the substrate-source voltage (VBS). The boundary is separated into a PMOS transistor region and an NMOS transistor region.
Thereby, in the high-voltage decoder circuit 278 shown in FIG. 40, an increase in resistance due to the substrate bias effect in the MOS transistor constituting the decoder circuit can be suppressed.

FIG. 41 is a circuit diagram showing a circuit configuration of another example of the low-voltage decoder circuit 279 in the drain driver 130 of the present embodiment.
The low voltage decoder circuit 279 shown in FIG. 41 has a circuit configuration similar to that of the high voltage decoder circuit 278 shown in FIG.
However, in the low-voltage decoder circuit 279, the gradation voltage (the gradation voltage of V16 (or V18) or V15 (or V17) in FIG. 40) at which the substrate-source voltage (VBS) is equivalent is used as a boundary. In separating the PMOS transistor region and the NMOS transistor region, the PMOS transistor region and the NMOS transistor region are opposite to the high voltage decoder circuit 278.
However, each voltage is V1>V2>V3...>V32> V33.

In each of the above embodiments, each MOS transistor constituting the decoder circuit 301 is composed of a high voltage MOS transistor or a MOS transistor having a high voltage structure only in the gate electrode portion.
Further, the MOS transistor on the low bit side of the decoder circuit 301 can use a MOS transistor having a low drain-source breakdown voltage. In this case, the size of the decoder circuit 301 can be further reduced. .

FIG. 42 is a circuit diagram showing an example of the circuit configuration of the second gradation voltage generation circuit 303 used in the high voltage decoder circuit 278 shown in FIG.
In the second gradation voltage generation circuit 303 shown in FIG. 42, the capacitance values of the capacitor (Co1) and the capacitor (Co2) are the same, and the capacitance value of the capacitor (Co3) is twice the capacitance value of the capacitor (Co1). The capacitance value and the capacitance value of the capacitor (Co4) are four times the capacitance value of the capacitor (Co1).
Each switch control circuit (SG1 to SG3) includes a NAND circuit (NAND), an AND circuit (AND), and a NOR circuit (NOR). Table 2 shows a truth table of the NAND circuit (NAND), the AND circuit (AND), and the NOR circuit (NOR).

  When the reset pulse (/ CR) is at L level, the switch element (SS1) is turned on, the output of the NOR circuit (NOR) is at L level, and each switch element (S02, S12, S22) is turned on.

  In this case, the timing pulse (/ TCK) is at the H level, the output of the NAND circuit (NAND) is at the H level, and each switch element (S01, S11, S21) is turned off. Thereby, both ends of each capacitor (Co1 to Co4) are connected to the terminal (P2), so that each capacitor (Co1 to Co4) is charged and discharged, and the potential difference is set to 0 volts.

  Next, when the reset pulse (/ CR) is at the H level and the timing pulse (/ TCK) is at the L level, each switch element (D0 to D2) is displayed in accordance with each bit value of the lower 3 bits (D0 to D2) of the display data. S01, S02, S11, S12, S21, S22) are turned on or off.

  Thus, when the gradation voltage of the terminal (P1) is (Va) and the gradation voltage of the terminal (P2) is (Vb), the second gradation voltage generation circuit 302 outputs Va + 1 / 8Δ, Va + 2 / 8Δ, ... A gradation voltage of Vb (Va + 8 / 8Δ) is output.

  The second gradation voltage generation circuit 303 can use a resistor instead of the capacitor. In this case, a resistor having a high resistance value is used, and the resistance value of each resistor is large or small. The relationship needs to be reversed with the capacitor.

  For example, in the second gradation voltage generation circuit 303 shown in FIG. 37, when a resistor is used instead of the capacitor, the resistance value of the resistor replaced with the capacitor (C1) and the capacitor (C3) is the capacitor (C2). It is necessary to set the resistance value to twice the resistance value of the resistor to be replaced.

[Embodiment 3]
The liquid crystal display module according to the third embodiment of the present invention is different from the liquid crystal display module according to the second embodiment in that an inverting amplifier circuit is used as the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 in the drain driver 130. Is different.
Hereinafter, the drain driver 130 of the present embodiment will be described focusing on the differences from the second embodiment.
FIG. 43 shows the configuration of the third embodiment in the case of using the high voltage decoder circuit 278 shown in FIG. 37 and the low voltage decoder circuit 279 having the same circuit configuration as the high voltage decoder circuit 278 shown in FIG. It is a figure which shows schematic structure of the output stage in the drain driver 130 of a liquid crystal display module.
In the figure, the differential amplifier circuit shown in FIG. 15 is used for the high voltage amplifier circuit 271, and the differential amplifier circuit shown in FIG. 14 is used for the low voltage amplifier circuit 272.
FIG. 44 is a diagram showing one of the high-voltage amplifier circuit 271 or the low-voltage amplifier circuit 272 shown in FIG. 43 and the switched capacitor circuit 313 connected to the input stage thereof.
As shown in FIG. 44, a parallel circuit of a switch circuit (SWA01) and a capacitor (CA1) is connected between the inverting input terminal (−) and the output terminal of the operational amplifier (OP2), and the operational amplifier (OP2) One terminal of each capacitor (CA2 to CA4) is connected to the inverting input terminal (−).
The other terminals of the capacitors (CA2 to CA4) are connected to one of the first gradation voltages adjacent to each other, that is, the terminal (P1) shown in FIG. 37 via the switch circuits (SWA11 to SWA31). The output first gray scale voltage (Va) is also passed through each switch circuit (SWA12 to SWA32) to one of the first gray scale voltages adjacent to each other, that is, the terminal (P2) shown in FIG. The output first gradation voltage (Vb) is applied.
Further, the non-inverting input terminal (+) of the operational amplifier (OP2) has one of the first gradation voltages adjacent to each other (the first gradation voltage (Vb) output to the terminal (P2) shown in FIG. 37). Is applied.
Here, the capacitance values of the capacitor (CA2) and the capacitor (CA4) are the same, the capacitance value of the capacitor (CA3) is twice the capacitance value of the capacitor (CA2), and the capacitance value of the capacitor (CA1). Is four times the capacitance value of the capacitor (CA2).

In this inverting amplifier circuit, the switch circuit (SWA01) and the switch circuits (SWA11 to SWA31) are turned on and the switch circuits (SWA12 to SWA32) are turned off during the reset operation.
In this state, the capacitor (CA1) is reset, the operational amplifier (OP2) constitutes a voltage follower circuit, and the potential of the output terminal and the inverting input terminal (−) of the operational amplifier (OP2) is the first gradation voltage ( Vb), the capacitors (CA2 to CA4) are charged to a voltage of (Vb−Va = ΔV).
In a normal state, the switch circuit (SWA01) is turned off, and the switch circuits (SWA11 to SWA31) and the switch circuits (SWA12 to SWA32) are turned on or off according to a predetermined combination.
As a result, the first gradation voltage of Va is inverted and amplified with reference to the first gradation voltage (Vb), and Vb + Va, Vb + Va + 1 / 4ΔV, Vb + Va + 1 / 2ΔV, Vb + Va + 3 / 4ΔV are output from the output terminal of the operational amplifier (OP2). Voltage is output.

[Embodiment 4]
The liquid crystal display module according to the fourth embodiment of the present invention outputs a gray scale reference voltage (V ″ 5 to V ″ 9) having a negative polarity from the power supply circuit 120 to the drain driver 130. The negative gray scale voltage is generated from the negative gray scale reference voltage (V ″ 5 to V ″ 9), and an inverting amplifier circuit is used as the high voltage amplifier circuit 271. This is different from the liquid crystal display module of the first embodiment in that the regulated voltage is inverted and amplified by the inverting amplifier circuit and the positive gradation voltage is applied to the drain signal line (D).
Hereinafter, the drain driver 130 of the present embodiment will be described focusing on the differences from the first embodiment.
FIG. 45 is a diagram showing a schematic configuration of an output stage in the drain driver 130 of the liquid crystal display module according to the third embodiment.
In the figure, the differential amplifier circuit shown in FIG. 15 is used for the high voltage amplifier circuit 271, and the differential amplifier circuit shown in FIG. 14 is used for the low voltage amplifier circuit 272.
In the high voltage amplifier circuit 271 of the present embodiment, the operational amplifier (OP3) constitutes an inverting amplifier circuit.
Therefore, a low voltage decoder circuit 279 shown in FIG. 6 is connected to the input stage of the operational amplifier (OP3) instead of the high voltage decoder circuit 278 shown in FIG.
That is, in this embodiment, the decoder section 261 shown in FIG. 6 uses the low voltage decoder circuit 279.
Accordingly, although not shown, the positive voltage generation circuit 121 in the power supply circuit 120 and the positive gradation voltage generation circuit 151a in the drain driver 130 are not necessary in the present embodiment.

As shown in FIG. 45, a parallel circuit of a switch circuit (SWB1) and a capacitor (CB1) is connected between the inverting input terminal (−) and the output terminal of the operational amplifier (OP3), and the operational amplifier (OP3). One terminal of the capacitor (CB2) is connected to the inverting input terminal (−).
To the other terminal of the capacitor (CB2), the gradation voltage from the low voltage decoder circuit 272 is applied via the switch (SWB3), and the reference potential (Vref) is applied via the switch (SWB2).
Further, the reference potential (Vref) is applied to the non-inverting input terminal (+) of the operational amplifier (OP3).
Here, the reference potential (Vref) is also the potential of the liquid crystal driving voltage (Vcom) applied to the common electrode (ITO2).

In the inverting amplifier circuit, the switch circuit (SWB1) and the switch circuit (SWB2) are turned on and the switch circuit (SWB3) is turned off during the reset operation.
In this state, the operational amplifier (OP3) constitutes a voltage follower circuit, and the potential of the output terminal and the inverting input terminal of the operational amplifier (OP3) becomes the reference potential (Vref), and also the other terminal of the capacitor (CB2). Since the reference potential (Vref) is applied, the capacitor (CB1) and the capacitor (CB2) are reset.
In a normal state, the switch circuit (SWB1) and the switch circuit (SWB2) are turned off, the switch circuit (SWB3) is turned on, and the negative gradation voltage input through the capacitor (CA2) is the reference potential. The voltage is inverted and amplified with reference to (Vref), and a positive gradation voltage is output from the output terminal of the operational amplifier (OP3).
In this embodiment, a low voltage decoder circuit 272 shown in FIG. 6 is used instead of the high voltage decoder circuit 271 shown in FIG. 6, and the positive voltage generation circuit 121 in the power supply circuit 120 and the drain driver are used. Since the positive polarity gradation voltage generation circuit 151a in 130 is not required, the configuration can be simplified.

[Embodiment 5]
The liquid crystal display module according to the fifth embodiment of the present invention is different from the first embodiment in that a single amplifier circuit 273 is used as the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272.
Hereinafter, the drain driver 130 of the present embodiment will be described focusing on the differences from the first embodiment.
FIG. 46 is a diagram showing a schematic configuration of an output stage in the drain driver 130 of the liquid crystal display module according to the third embodiment.
In the figure, reference numeral 273 denotes a single amplifier circuit that outputs negative and positive gradation voltages. In this embodiment, the amplifier circuit 273 outputs negative and positive gradation voltages.
Therefore, it is necessary to input the positive polarity gradation voltage selected by the high voltage decoder circuit 278 or the negative polarity gradation voltage selected by the negative voltage decoder circuit 279 to the amplifier circuit 273.
Accordingly, as shown in FIG. 47, in this embodiment, the switch unit (2) 264 needs to be provided between the decoder unit 261 and the amplifier circuit pair 263.

FIG. 48 is a diagram showing a circuit configuration of an example of a differential amplifier circuit used in the amplifier circuit 273 shown in FIG.
In the amplifier circuit 273 shown in FIG. 48, ● indicates a switching transistor, and is supplemented with A in the drawing, ● is a switching transistor that is turned on by a control signal (A), and ● is appended with B A switching transistor that is turned on by a control signal (B) is shown.
The amplifier circuit 273 shown in FIG. 48 has a push-pull configuration as an output stage, thereby enabling output of negative and positive gradation voltages with a single amplifier circuit.
In addition, the amplifier circuit 273 illustrated in FIG. 48 has a characteristic that a dynamic range is wide because the current (I1 ′, I2 ′) can flow even when the current (I1, I2) is off.

  In the present embodiment, negative and positive gradation voltages are output from a single amplifier circuit for each drain signal line (D), and the luminance of each pixel is the common electrode (ITO2). Since it is determined by the potential from the common potential (Vcom) applied to the voltage, a voltage (| VH−Vcom |) between the positive gradation voltage (VH) and the potential (Vcom) of the common electrode (ITO2). Is equal to the voltage (| VL−Vcom |) between the negative gradation voltage (VL) and the potential (Vcom) of the common electrode (ITO2) (| VH−Vcom | = | VL−Vcom |). In some cases, there is no problem of vertical stripes, but in many cases, the positive gradation voltage (VH) and the negative gradation voltage due to the symmetry due to the polarity of the liquid crystal layer or the coupling of the gate driver 140. (VL) does not match Also the present invention in this embodiment is useful.

[Embodiment 6]
As described above, the liquid crystal display device is required to have a high resolution of the liquid crystal display panel.
With such high resolution of the liquid crystal display panel, the display control device 110, the drain driver 130, and the gate driver 140 are also forced to operate at high speed, and in particular, a clock output from the display control device 110 to the drain driver 130. The operating frequency of (CL2) and display data is greatly affected by the increase in speed.
For example, a liquid crystal display panel with 1024 × 768 pixels in the XGA display mode requires a clock (CL2) with a frequency of 65 MHz and display data with a frequency of 32.5 MHz (half of 65 MHz).

Therefore, for example, in the case of the XGA display mode, in the liquid crystal display module of this embodiment, the frequency of the clock (CL2) is set to 32.5 MHz (half of 65 MHz) from the display control device 110 to the drain driver 130. In 130, display data is latched at the rise and fall of the clock (CL2).
FIG. 49 is a block diagram for explaining the configuration of the drain driver 130 according to the sixth embodiment, focusing on the configuration of the output circuit.
FIG. 49 is a diagram corresponding to FIG. 6, but the contents shown in FIG. 49 are slightly different from those in FIG. 6, and the shift register circuit (156 in FIG. 6) is omitted.
Hereinafter, the driver 130 according to the present embodiment will be described focusing on differences from the first embodiment.
As shown in FIG. 49, in the driver 130 of the present embodiment, a pre-latch unit 160 is provided.
FIG. 50 shows a circuit configuration of pre-latch unit 160 shown in FIG.
As shown in FIG. 50, one of the display data sent from the display control device 110 is latched in the flip-flop circuit (F31) at the rising edge of the clock (CL2), and further flipped at the falling edge of the clock (CL2). Is latched by the loop circuit (F32) and output to the switch section (3) 266.
One of the display data is latched in the flip-flop circuit (F33) at the falling edge of the clock (CL2), and further latched in the flip-flop circuit (F34) at the rising edge of the clock (CL2). ) 266.

The display data latched by the pre-latch unit 160 is selected by the switch unit (3) and is alternately output to the bus line 161a or the bus line 161b of the display data.
Display data on these two bus lines (161 a, 161 b) is captured by the data latch unit 265 based on the data capture signal from the shift register 153.
In this case, in this embodiment mode, data for two pixels (data for six drain signal lines (D)) are taken into the data latch unit 265 at a time.
Based on the display data latched by the data latch unit 265, a gradation voltage corresponding to the display data is output from the amplifier circuit pair 263 of the drain driver 130 to each drain signal line (D).
Since this operation is the same as that of the first embodiment, the description thereof is omitted.

FIG. 51 is a diagram for explaining the display data on the bus lines (161a, 161b) shown in FIG. 49 and the operating frequency of the clock (CL2).
In FIG. 51, the case where the frequency of the display data is 60 MHz for one data (30 MHz for two data) and the frequency of the clock (CL2) is 30 MHz will be described.
As shown in FIG. 51, the display data sent from the display control device 110 at a frequency of 60 MHz includes the flip-flop circuit (F31) and the flip-flop circuit (F32), and the flip-flop circuit (F33) and the flip-flop circuit (F34). ) And is sent to the bus lines (161a, 161b), the frequency of display data on the bus lines (161a, 161b) is 30 MHz for one data (15 MHz for two data).

FIG. 52 shows a case where the display data is latched at the rising edge and falling edge of the clock (CL2), and the drain driver configuration is centered on the configuration of the output circuit when there is only one bus line 161 in the drain driver. It is a block diagram for demonstrating a structure.
FIG. 53 is a diagram for explaining the display data on the bus line 161 shown in FIG. 52 and the operating frequency of the clock (CL2).
As can be seen from FIG. 53, when there is only one system bus line 161 in the drain driver, the frequency of the display data on the one system bus line 161 is the same as the display data sent from the display control device 110. 60 MHz.

FIG. 54 shows a layout of bus lines 161 in the semiconductor integrated circuit constituting the drain driver shown in FIG.
As shown in FIG. 54, since the bus line 161 is formed to both ends in the longitudinal direction in the semiconductor integrated circuit constituting the drain driver, the delay time increases as the distance from the pre-latch portion 160 increases.
Therefore, if the frequency of the display data on one system bus line 161 is the same as the display data sent from the display control device 110 (for example, 60 MHz), the display data is displayed at the far end away from the pre-latch unit 160. The timing margin when latching is reduced.

However, in the present embodiment, two bus lines (161a, 161b) are provided, and the display data frequency sent from the display control device 110 is set to the frequency of the display data on the two bus lines (161a, 161b). Therefore, the timing margin when the display data is latched at the far end away from the pre-latch unit 160 can be reduced as compared with the case of the drain driver shown in FIG. Can be doubled.
Thereby, according to the present embodiment, it is possible to increase the speed of the drain driver 130.

In the drain driver shown in FIG. 52, the flip-flop circuit of the shift register 153 has one flip-flop circuit for every three drain signal lines (D) (for example, 86 if the total number of drain signal lines (D) is 258). Required).
However, in the drain driver 130 of this embodiment, data for two pixels (data for six drain signal lines (D)) are fetched into the data latch unit 265 at a time, so that the flip-flop circuit of the shift register 153 is One for every six drain signal lines (D) (for example, 43 if the total number of drain signal lines (D) is 258), the number of flip-flop circuits of the shift register 153 is shown in FIG. The drain driver 130 shown in FIG.

Further, in the drain driver 130 of the present embodiment, the display data output from the pre-latch unit 160 is switched by the switch unit (3) 266 and is alternately output to the two bus lines (161a, 161b). Therefore, the switch part (1) 262 shown in FIG. 52 is not necessary.
One switch section (1) 262 is required for every six drain signal lines (D) (for example, 43 if the total number of drain signal lines (D) is 258).
However, the switch unit (3) 266 of the drain driver 130 according to the present embodiment only needs to have the number of display data bits (18 in FIG. 49 because the display data is 6 bits).
Thus, in the drain driver 130 of this embodiment, the number of flip-flop circuits and switch portions of the shift register 153 can be significantly reduced as compared with the drain driver shown in FIG. It is possible to simplify the configuration of the internal circuit.

In each of the above embodiments, the embodiment in which the present invention is applied to the vertical electric field type liquid crystal display panel has been described. However, the present invention is not limited to this, and the present invention is not limited to this. It can also be applied to panels.
FIG. 55 is a diagram showing an equivalent circuit of an electric field type liquid crystal display panel.
In the vertical electric field type liquid crystal display panel shown in FIG. 2 or FIG. 3, a common electrode (ITO2) is provided on the color filter substrate, whereas in the horizontal electric field type liquid crystal display panel, the counter electrode (CT) is provided on the TFT substrate. And a counter electrode signal line (CL) for applying a drive voltage (VCOM) to the counter electrode (CT).
Therefore, the liquid crystal capacitor (Cpix) is equivalently connected between the pixel electrode (PX) and the counter electrode (CT). A storage capacitor (Cstg) is also formed between the pixel electrode (PX) and the counter electrode (CT).
Further, in each of the above embodiments, the embodiment in which the dot inversion method is applied as the driving method has been described. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be applied to a common inversion method in which the drive voltage applied to the ITO1) and the common electrode (ITO2) is inverted.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

1 is a block diagram illustrating a schematic configuration of a TFT liquid crystal display module according to a first embodiment of the present invention. It is a figure which shows the equivalent circuit of an example of the liquid crystal display panel shown in FIG. It is a figure which shows the equivalent circuit of the other example of the liquid crystal display panel shown in FIG. It is a figure for demonstrating the polarity of the liquid-crystal drive voltage output to a drain signal line (D) from a drain driver, when a dot inversion method is used as a drive method of a liquid crystal display module. FIG. 2 is a block diagram illustrating a schematic configuration of an example of a drain driver illustrated in FIG. 1. FIG. 6 is a block diagram for explaining the configuration of the drain driver shown in FIG. 5, focusing on the configuration of the output circuit. It is a circuit diagram which shows the circuit structure of one switch circuit of the switch part (2) shown in FIG. FIG. 7 is a circuit diagram showing a voltage follower circuit used as the high voltage amplifier circuit and the low voltage amplifier circuit shown in FIG. 6. FIG. 7 is a circuit diagram showing an example of a differential amplifier circuit constituting an operational amplifier used in the low voltage amplifier circuit shown in FIG. 6. FIG. 7 is a circuit diagram showing an example of a differential amplifier circuit constituting an operational amplifier used in the high voltage amplifier circuit shown in FIG. 6. FIG. 11 is a diagram illustrating an equivalent circuit of an operational amplifier in consideration of an offset voltage (Voff). It is a figure for demonstrating the liquid-crystal drive voltage applied to a drain signal line (D) when there exists offset voltage (Voff) and there is no offset voltage (Voff). It is a figure for demonstrating the reason a vertical streak arises in a liquid crystal display panel by offset voltage (Voff). FIG. 3 is a circuit diagram showing a circuit configuration of a low voltage amplifier circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a circuit configuration of a high voltage amplifier circuit according to the first embodiment. 5 is a circuit diagram showing a circuit configuration when a control signal (A) is at an H level in the low voltage amplifier circuit according to the first embodiment; FIG. FIG. 3 is a circuit diagram showing a circuit configuration when a control signal (B) is at an H level in the low voltage amplifier circuit according to the first embodiment; It is a figure which shows the structure of the output stage of the drain driver of this Embodiment 1. FIG. 3 is a timing chart for explaining the operation of the drain driver according to the first embodiment. FIG. 4 is a diagram for explaining the reason why vertical stripes generated in a liquid crystal display panel are not noticeable due to an offset voltage (Voff) in the first embodiment. FIG. 4 is a diagram for explaining the reason why vertical stripes generated in a liquid crystal display panel are not noticeable due to an offset voltage (Voff) in the first embodiment. FIG. 4 is a diagram for explaining the reason why vertical stripes generated in a liquid crystal display panel are not noticeable due to an offset voltage (Voff) in the first embodiment. FIG. 3 is a block diagram illustrating a main circuit configuration of a control circuit in the drain driver according to the first embodiment. FIG. 24 is a circuit diagram showing a circuit configuration of a control signal generation circuit shown in FIG. 23. 25 is a timing chart for explaining the operation of the control signal generation circuit shown in FIG. 24. FIG. 24 is a circuit diagram showing a circuit configuration of a frame recognition signal generation circuit shown in FIG. 23. 27 is a timing chart for explaining the operation of the frame recognition signal generation circuit shown in FIG. 26. 3 is a timing chart for explaining the operation of the control circuit according to the first embodiment. FIG. 29 is a circuit diagram illustrating an example of a clock generation circuit illustrated in FIG. 28. FIG. 3 is a main part layout diagram showing an arrangement of each part in the semiconductor integrated circuit constituting the drain driver of the first embodiment. It is a circuit diagram which shows the circuit structure of the conventional level shift circuit. FIG. 3 is a circuit diagram illustrating a circuit configuration of a level shift circuit according to the first embodiment. It is a figure which shows the voltage waveform of each part shown in FIG. FIG. 3 is a diagram for explaining a region occupied by a level shift circuit in the semiconductor integrated circuit constituting the drain driver of the first embodiment. FIG. 33 is a main part sectional view showing a sectional structure of a PMOS transistor (PSA1, PSA3) and an NMOS transistor (NSA1, NSA3) shown in FIG. 32; FIG. 3 is a circuit diagram showing a circuit configuration of a high voltage decoder circuit and a low voltage decoder circuit in the drain driver of the first embodiment. FIG. 10 is a circuit diagram showing a circuit configuration of an example of a high-voltage decoder circuit in the drain driver according to the second embodiment. FIG. 38 is a diagram for explaining the operation of the second gradation voltage generation circuit shown in FIG. 37. It is a figure which shows the structure of the output stage of the drain driver of this Embodiment 2. FIG. FIG. 10 is a circuit diagram showing a circuit configuration of another example of a high-voltage decoder circuit in the drain driver according to the second embodiment. FIG. 10 is a circuit diagram showing a circuit configuration of another example of a low voltage decoder circuit in the drain driver according to the second embodiment. FIG. 42 is a diagram showing an example of a second gradation voltage generation circuit used in the high voltage decoder circuit shown in FIG. 40 or the low voltage decoder circuit shown in FIG. 41. It is a figure which shows the structure of the output stage of the drain driver of this Embodiment 3. FIG. 44 is a diagram showing one of the high-voltage amplifier circuit or the low-voltage amplifier circuit shown in FIG. 43 and a switched capacitor circuit connected to the input stage. It is a figure which shows the structure of the output stage of the drain driver of this Embodiment 4. It is a figure which shows the structure of the output stage of the drain driver of this Embodiment 5. It is a block diagram for demonstrating the structure of the drain driver of this Embodiment 5 focusing on the structure of an output circuit. 48 is a circuit diagram showing a circuit configuration of an example of a differential amplifier circuit used in the amplifier circuit shown in FIG. 47. FIG. It is a block diagram for demonstrating the structure of the drain driver 130 of this Embodiment 6 focusing on the structure of an output circuit. It is a figure which shows one circuit structure of the pre latch part 160 shown in FIG. It is a figure for demonstrating the display data on the bus line (161a, 161b) shown in FIG. 49, and the operating frequency of a clock (CL2). To explain the configuration of the drain driver, focusing on the configuration of the output circuit when the display data is latched at the rise and fall of the clock (CL2) and there is only one bus line in the drain driver. FIG. FIG. 53 is a diagram for explaining display data on the bus line shown in FIG. 52 and an operating frequency of a clock (CL2). FIG. 53 is a diagram showing a layout of bus lines in a semiconductor integrated circuit constituting the drain driver shown in FIG. 52. It is a figure which shows the equivalent circuit of the liquid crystal display panel of an electric field system.

Explanation of symbols

10 Liquid crystal display panel (TFT-LCD)
20 p-type semiconductor substrate 21 n-well 22 p-well 24a, 24b, 24c, 24d n-type semiconductor region 25a, 25b, 25c, 25d p-type semiconductor region 26a, 26b, 27a, 27b gate electrode 100 interface unit 110 display control device 120 Power supply circuit 121, 122 Voltage generation circuit 123 Common electrode voltage generation circuit 124 Gate electrode voltage generation circuit 130 Drain driver 131, 132, 134, 135, 141, 142 Signal line 133, 161, 161a, 161b Display data bus line 140 Gate Driver 151a, 151b Gradation voltage generation circuit 152 Control circuit 153 Shift register circuit 154 Input register circuit 155 Storage register circuit 156 Level shift circuit 157 Output circuit 158a, 158b Electricity Bus line 160 Pre-latch unit 261 Decoder unit 262, 264, 266 Switch unit 263 Amplifier circuit pair 265 Data latch unit 271 High-voltage amplifier circuit 272 Low-voltage amplifier circuit 273 High-voltage / low-voltage amplifier circuit 278, 279, 301, 311 and 312 Decoder circuit 302 Multiplexer 303 Second gradation voltage generating circuit 400 Control signal generating circuit 401 PORN signal generating circuit 402 Voltage dividing circuit 403 Inverter circuit group 410 Frame recognition signal generating circuit 420 Shift clock enable signal generating circuit 430 Shifting clock Generation circuit 440 Pulse generation circuit 450 Pulse selection circuit D Drain signal line (video signal line or vertical signal line)
G Gate signal line (scanning signal line or horizontal signal line)
ITO1, CX Pixel electrode ITO2 Common electrode CT Counter electrode CL Counter electrode signal line TFT Thin film transistor CLC, Cpix Liquid crystal capacitor CSTG Holding capacitor CADD Additional capacitor Cstg Storage capacitor S, SWA, SWB Switch element
PM, PA, PB, PSB, PSA, PBP, PBB PMOS transistor NM, NA, NB, NSB, NSA, NBP, NBB NMOS transistor C, Co, CA, CB capacitor SG1-SG3 switch control circuit NAND NAND circuit AND AND circuit NOR NOR circuit INV Inverter OP Operational amplifier F Flip-flop circuit EXOR Exclusive OR circuit

Claims (9)

A data latch circuit for latching display data;
A decoder circuit for selecting a gradation voltage based on the display data latched by the data latch circuit;
An amplifier circuit to which the gradation voltage selected by the decoder circuit is supplied;
A drain signal line to which the output of the amplifier circuit is supplied;
A gate signal line;
A liquid crystal display device having a thin film transistor connected to the drain signal line and the gate signal line,
The amplifier circuit includes: a first transistor having a first terminal connected to a first power supply;
A second transistor having a first terminal connected to the first power supply;
A third transistor having a first terminal connected to a second power source and a second terminal connected to a second terminal of the first transistor;
A fourth transistor having a first terminal connected to the second power source and a second terminal connected to a second terminal of the second transistor;
Switching means for supplying the gradation voltage supplied from the decoder circuit to the gate electrode of the first transistor or the gate electrode of the second transistor by a switching control signal;
The liquid crystal display device according to claim 1, wherein a period of the switching control signal is one horizontal scanning time or more. The amplifier circuit includes a fifth transistor connected between the second terminal and the output terminal of the first transistor;
A sixth transistor connected between the second terminal of the second transistor and the output terminal;
The liquid crystal display device according to claim 1, wherein the switching unit turns on a fifth transistor or turns on a sixth transistor according to the switching control signal.   3. The liquid crystal according to claim 1, wherein the switching unit connects the output terminal to a gate electrode of the first transistor or a gate electrode of the second transistor by a switching control signal. Display device.   4. The liquid crystal display device according to claim 3, wherein the cycle of the switching control signal is twice the horizontal scanning time.   The liquid crystal display device according to claim 3, wherein the phase of the switching control signal is inverted every two frames. A data latch circuit for latching display data input from the outside;
A decoder circuit for selecting a gradation voltage based on the display data supplied from the data latch circuit;
An amplifier circuit that outputs the gradation voltage selected by the decoder circuit as a video signal voltage;
The amplifier circuit includes: a first transistor having a first terminal connected to a first power supply;
A second transistor having a first terminal connected to the first power supply;
A third transistor having a first terminal connected to a second power source and a second terminal connected to a second terminal of the first transistor;
A fourth transistor having a first terminal connected to the second power source and a second terminal connected to a second terminal of the second transistor;
Switching means for supplying the gradation voltage supplied from the decoder circuit to the gate electrode of the first transistor or the gate electrode of the second transistor by a switching control signal;
2. A video signal line driving device according to claim 1, wherein a cycle of the switching control signal is equal to or greater than a cycle of an output control clock input to the data latch circuit. The amplifier circuit includes a fifth transistor connected between the second terminal and the output terminal of the first transistor;
A sixth transistor connected between the second terminal of the second transistor and the output terminal;
7. The video signal line driving apparatus according to claim 6, wherein the switching unit turns on the fifth transistor or turns on the sixth transistor according to the switching control signal.   8. The video according to claim 6, wherein the switching unit connects the output terminal to the gate electrode of the first transistor or the gate electrode of the second transistor according to a switching control signal. Signal line drive device. 9. The video signal line drive device according to claim 8, wherein the cycle of the switching control signal is equal to or longer than two cycles of the output control clock input to the data latch circuit.

Images