JP3745890B2 - Integrated circuit mounting body and integrated circuit mounting method - Google Patents

Integrated circuit mounting body and integrated circuit mounting method Download PDF

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Publication number
JP3745890B2
JP3745890B2 JP29555397A JP29555397A JP3745890B2 JP 3745890 B2 JP3745890 B2 JP 3745890B2 JP 29555397 A JP29555397 A JP 29555397A JP 29555397 A JP29555397 A JP 29555397A JP 3745890 B2 JP3745890 B2 JP 3745890B2
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Japan
Prior art keywords
integrated circuit
electrode terminal
wiring pattern
conductive paste
wiring board
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Expired - Fee Related
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JP29555397A
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Japanese (ja)
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JPH11135558A (en
Inventor
理仁 川端
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

【０００１】
【発明の属する技術分野】
本発明はベアＩＣ等の集積回路の実装体及び集積回路の実装方法に関するものである。
【０００２】
【従来の技術】
従来のベアＩＣ等の集積回路に用いられている電極端子は、金属ワイヤーをボンディングして集積回路上に形成したものを高さ調整(レベリング)したものや、金属メッキ技術により集積回路上に形成したものを先端がフラットな状態のまま基板の配線パターンと接合している。図５は従来の集積回路の電極端子とその使用状態を示す斜視図及び側面図であり、以下この図面を参照しながら説明する。
【０００３】
図中、１は電極端子、２はベアＩＣ、３は配線基板、４は配線基板３の配線パターン、５は異方性の導電性ペーストである。電極端子１はボンディングした金属ワイヤーや、金属メッキにより形成されて図５(a)に示すようにベアＩＣ２に設けられ、また、図５(b)に示すようにベアＩＣ２と配線基板３の間の全面には異方性の導電性ペースト５が塗布されている。ここで、電極端子１と配線パターン４の接合は、この両者間に異方性の導電性ペースト５が介在した状態でこの部分を熱圧着することにより行なわれる。
【０００４】
【発明が解決しようとする課題】
しかしながら、このような従来の構成では、次のように電極端子と配線基板の配線パターンとの接合状態が不安定となり、その導電接続の信頼性が低下するという問題がある。図６は従来の集積回路の電極端子と配線基板の配線パターンとの接続時における導電性ペーストの状態を示す説明図であり、この図６に示すように、電極端子１と配線パターン４を接合のために近づけて行くと両者に挾まれた部分の異方性の導電性ペースト５に含まれている導電性に寄与する導電フィラー５ｆが周辺に押し出される現象が起き、これが押し出されると電極端子１と配線パターン４の間の導電性が劣化すると同時に、押し出された導電フィラー５ｆが電極端子１の周辺に溜り、場合によっては凝縮して電極間の短絡を誘発する。したがって、この押し出される導電フィラー５ｆの分を加味して必要以上に導電フィラー５ｆの量を多くしたり、また、押し出された導電フィラー５ｆが電極端子１の周辺に溜ることにより発生する電極間の短絡を防ぐために、導電フィラー５ｆに絶縁コートを施し、前記の電極端子１と配線パターン４の接合時には、その圧力で絶縁コートが破壊されるように導電フィラー５ｆを加工したものもあるが、いずれも異方性の導電性ペースト５自体が高価となり量産に適しないという問題点がある。
【０００５】
本発明は上記従来の問題点を解決するものであり、集積回路の電極端子と配線基板の配線パターンとの導電接続の信頼性が高い集積回路の実装体及び集積回路の実装方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明の集積回路の実装体は、くぼみを有する電極端子を設けた集積回路と、導電性ペーストにより電極端子と接続する配線パターンを有した配線基板とを備え、配線パターンはくぼみに挾持して形成したものである。
【０００７】
この発明によれば、導電性ペーストの導電フィラーが電極端子のくぼみ内に入り込むと同時にそのあふれた部分は電極端子と配線パターンをつなぐような形で両者の間に介在し、かつ配線パターンをくぼみが挾持するので、導電接続の信頼性が大幅に向上する。
【０００８】
【発明の実施の形態】
以下本発明の各実施の形態について図面を参照しながら説明する。なお、従来のものと同一部分については同一符号を用いるものとする。
【０００９】
図１は本発明の集積回路の電極端子の実施の形態における参考例の構成とその使用状態を示す斜視図及び側面図、図２は本発明の集積回路の電極端子の参考例におけるレベリングと、先端加工を兼ねたキャピラリを示す斜視図である。図１において、１は電極端子、１ａは電極端子１の先端中央部に設けられた逆円錐形のくぼみ、２はベアＩＣ、３は配線基板、４は配線基板３の配線パターン、６は導電性ペースト、７は絶縁性ペーストを示しており、電極端子１には、その先端に図１(a)に示すような逆円錐形のくぼみ１ａが設けられると共に、その高さがレベリングされてベアＩＣ２に接合される。この円錐形のくぼみ１ａの形成とその高さのレベリングは図２に示すキャピラリにより同時に行なわれる。すなわち、キャピラリ８の頂部８ａを電極端子１に圧接させることにより、レベリングと円錐形の突部８ｂによる電極端子１への逆円錐形のくぼみ１ａの形成とが同時に行なわれ、図１(b)に示す状態になる。
【００１０】
このように形成されたベアＩＣあるいはフリップチップＩＣの実装は次のように行なわれる。図１(b)に示すように電極端子１の先端部付近のみに導電性ペースト６を塗布する工程を経て、電極端子１と配線パターン４を圧接接合する。この接合工程において導電性ペースト６に含まれる導電フィラーの一部はくぼみ１ａ内に入り込み、導電フィラー全体として外部に流動しにくくなると同時に、このくぼみ１ａからあふれた部分の導電フィラーが電極端子１と配線パターン４をつなぐような形で両者の間に介在するので、両者は確実に接合され、導電接続の信頼性が大幅に向上する。なお、導電性ペースト６を塗布した部分を含むベアＩＣ２と配線基板３の間には絶縁性ペースト７が充填される。
【００１１】
以上のように本参考例によれば、電極端子と配線パターンの導電接続の信頼性が大幅に向上すると同時に、従来のもののような電極間の短絡を誘発するおそれもない。また、高価な導電性ペーストは電極端子の先端部付近のみに塗布し、これ以外の部分は廉価な絶縁性ペーストを充填すれば良いのでコストダウンが図れる。
【００１２】
図３は本発明の集積回路の電極端子の実施の形態における構成とその使用状態を示す斜視図及び側面図、図４は本発明の集積回路の電極端子の実施の形態におけるレベリングと、先端加工を兼ねたキャピラリを示す斜視図である。図３において、１は電極端子、１ｂは電極端子１の先端中央部に設けられた中割れ状のくぼみでその先端部は後述の配線パターン４を挾み込めるように構成されている。２はベアＩＣ、３は配線基板、４は配線基板３の配線パターン、６は導電性ペースト、７は絶縁性ペーストであり、電極端子１には、その先端部に図３(a)に示すような中割れ状のくぼみ１ｂが設けられると共に、その高さがレベリングされてベアＩＣ２に接合される。このくぼみ１ｂの形成とその高さのレベリングは図４に示すキャピラリにより同時に行なわれる。すなわち、キャピラリ８の頂部８ａを電極端子１に圧接させることにより、レベリングと刃型の突部８ｃによる電極端子１への中割れ状のくぼみ１ｂの形成とが同時に行なわれ、図３(b)に示す状態になる。
【００１３】
このように形成されたベアＩＣあるいはフリップチップＩＣの実装は次のように行なわれる。図３(b)に示すように電極端子１の先端部付近のみに導電性ペースト６を塗布する工程を経て、電極端子１と配線パターン４を圧接接合する。この接合工程において、配線パターン４は中割れ状のくぼみ１ｂにより挾持されると共に、導電性ペースト６に含まれる導電フィラーの一部はこのくぼみ１ｂ内に入り込み、導電フィラー全体として外部に流動しにくくなると同時に、このくぼみ１ｂからあふれた部分の導電フィラーが電極端子１と配線パターン４をつなぐような形で両者の間に介在するので、くぼみ１ｂによる配線パターン４の挾持と相俟って両者は確実に接合され、導電接続の信頼性が大幅に向上する。なお、導電性ペースト６を塗布した部分を含むベアＩＣ２と配線基板３の間には絶縁性ペースト７が充填される。
【００１４】
以上のように本実施の形態によれば、電極端子と配線パターンの導電接続の信頼性は、電極端子と配線パターンをつなぐような形で両者の間に介在する導電フィラーと、くぼみによる配線パターンの挾持により大幅に向上すると同時に、従来のもののような電極間の短絡を誘発するおそれもない。また、高価な導電性ペーストは電極端子の先端部付近のみに塗布し、これ以外の部分は廉価な絶縁性ペーストを充填すれば良いのでコストダウンが図れる。
【００１５】
【発明の効果】
以上のように本発明によれば、導電性ペーストの導電フィラーが確実に電極端子と配線パターンの間に介在し、かつ配線パターンを電極端子のくぼみが挾持するので、導電接続の信頼性が大幅に向上すると共にコストダウンが図れるという有利な効果が得られる。
【図面の簡単な説明】
【図１】 本発明の集積回路の電極端子の実施の形態における参考例の構成とその使用状態を示す斜視図及び側面図
【図２】 本発明の集積回路の電極端子の参考例におけるレベリングと、先端加工を兼ねたキャピラリを示す斜視図
【図３】 本発明の集積回路の電極端子の実施の形態における構成とその使用状態を示す斜視図及び側面図
【図４】 本発明の集積回路の電極端子の実施の形態におけるレベリングと、先端加工を兼ねたキャピラリを示す斜視図
【図５】 従来の集積回路の電極端子とその使用状態を示す斜視図及び側面図
【図６】 従来の集積回路の電極端子と配線基板の配線パターンとの接続時における導電性ペーストの状態を示す説明図
【符号の説明】
１ 電極端子
１ａ 逆円錐形のくぼみ
１ｂ 中割れ状のくぼみ
２ ベアＩＣ
３ 配線基板
４ 配線パターン
５ 異方性の導電性ペースト
６ 導電性ペースト
７ 絶縁性ペースト
８ キャピラリ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mounting body of an integrated circuit such as a bare IC and a mounting method of the integrated circuit.
[0002]
[Prior art]
The electrode terminals used in conventional integrated circuits such as bare ICs are formed on the integrated circuit by height adjustment (leveling) formed on the integrated circuit by bonding metal wires, or on the integrated circuit by metal plating technology These are bonded to the wiring pattern of the substrate while the tip is flat. FIG. 5 is a perspective view and a side view showing the electrode terminals of a conventional integrated circuit and the state of use thereof, and will be described below with reference to this drawing.
[0003]
In the figure, 1 is an electrode terminal, 2 is a bare IC, 3 is a wiring board, 4 is a wiring pattern of the wiring board 3, and 5 is an anisotropic conductive paste. The electrode terminal 1 is formed by bonding metal wire or metal plating and is provided on the bare IC 2 as shown in FIG. 5A, and between the bare IC 2 and the wiring board 3 as shown in FIG. 5B. An anisotropic conductive paste 5 is applied to the entire surface. Here, the electrode terminal 1 and the wiring pattern 4 are joined by thermocompression bonding of this portion with an anisotropic conductive paste 5 interposed therebetween.
[0004]
[Problems to be solved by the invention]
However, such a conventional configuration has a problem that the bonding state between the electrode terminal and the wiring pattern of the wiring board becomes unstable as described below, and the reliability of the conductive connection is lowered. FIG. 6 is an explanatory view showing the state of the conductive paste when the electrode terminal of the conventional integrated circuit and the wiring pattern of the wiring board are connected. As shown in FIG. 6, the electrode terminal 1 and the wiring pattern 4 are joined. For the reason, when the conductive filler 5f that contributes to the conductivity contained in the anisotropic conductive paste 5 in the portion sandwiched between the two is pushed to the periphery, a phenomenon occurs, and when this is pushed, the electrode terminal At the same time as the conductivity between 1 and the wiring pattern 4 deteriorates, the extruded conductive filler 5f accumulates around the electrode terminal 1, and in some cases, condenses to induce a short circuit between the electrodes. Therefore, the amount of the conductive filler 5f to be pushed out is taken into consideration to increase the amount of the conductive filler 5f more than necessary, or between the electrodes generated when the extruded conductive filler 5f accumulates around the electrode terminal 1 In order to prevent a short circuit, an insulating coat is applied to the conductive filler 5f, and when the electrode terminal 1 and the wiring pattern 4 are joined, the conductive filler 5f is processed so that the insulating coat is broken by the pressure. However, the anisotropic conductive paste 5 itself is expensive and unsuitable for mass production.
[0005]
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides an integrated circuit mounting body and an integrated circuit mounting method with high reliability of conductive connection between an electrode terminal of an integrated circuit and a wiring pattern of a wiring board. With the goal.
[0006]
[Means for Solving the Problems]
Implementation of the integrated circuit of the present invention, an integrated circuit provided with electrode terminals having a recess, a conductive paste and a wiring board having a wiring pattern connected to the electrode terminals, the wiring pattern and clamped in the recess Formed.
[0007]
According to the present invention, the conductive filler of the conductive paste enters the recess of the electrode terminal, and at the same time, the overflowed portion is interposed between the electrode terminal and the wiring pattern , and the wiring pattern is recessed. There clamping to Runode, the reliability of the conductive connection is significantly improved.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol shall be used about the same part as a conventional thing.
[0009]
Figure 1 is a perspective view and a side view showing the configuration and use state of the definitive reference example in the form status of implementation of the electrode terminals of the integrated circuit of the present invention, the leveling of the reference example of the electrode terminals of the integrated circuit of Figure 2 is the invention It is a perspective view which shows the capillary which served as tip processing. In FIG. 1, 1 is an electrode terminal, 1a is an inverted conical depression provided at the center of the tip of the electrode terminal 1, 2 is a bare IC, 3 is a wiring board, 4 is a wiring pattern of the wiring board 3, and 6 is conductive. 1 represents an insulating paste, and the electrode terminal 1 is provided with an inverted conical recess 1a as shown in FIG. 1 (a) at the tip thereof, and the height thereof is leveled to be bare. Bonded to IC2. The formation of the conical depression 1a and the leveling of the height are simultaneously performed by the capillary shown in FIG. That is, by bringing the top 8a of the capillary 8 into pressure contact with the electrode terminal 1, the leveling and the formation of the inverted conical recess 1a in the electrode terminal 1 by the conical protrusion 8b are performed simultaneously. FIG. It will be in the state shown in.
[0010]
The bare IC or flip chip IC formed in this way is mounted as follows. As shown in FIG. 1B, the electrode terminal 1 and the wiring pattern 4 are pressure-bonded through a process of applying a conductive paste 6 only near the tip of the electrode terminal 1. In this joining step, a part of the conductive filler contained in the conductive paste 6 enters the recess 1a, and the conductive filler as a whole becomes difficult to flow to the outside. At the same time, the portion of the conductive filler overflowing from the recess 1a Since the wiring pattern 4 is interposed between the two in such a manner that the wiring patterns 4 are connected to each other, the two are reliably bonded and the reliability of the conductive connection is greatly improved. An insulating paste 7 is filled between the bare IC 2 including the portion where the conductive paste 6 is applied and the wiring board 3.
[0011]
As described above, according to this reference example , the reliability of the conductive connection between the electrode terminal and the wiring pattern is greatly improved, and at the same time, there is no possibility of inducing a short circuit between the electrodes as in the conventional case. Further, the expensive conductive paste is applied only in the vicinity of the tip portion of the electrode terminal, and the other portions may be filled with an inexpensive insulating paste, so that the cost can be reduced.
[0012]
Figure 3 is a perspective view and a side view showing the configuration and use state definitive the form status of implementation of the electrode terminals of the integrated circuit of the present invention, FIG. 4 is definitive in the form status of implementation of the electrode terminals of the integrated circuit of the present invention Leveling It is a perspective view which shows the capillary which served as tip processing. In FIG. 3, reference numeral 1 denotes an electrode terminal, and reference numeral 1 b denotes an indented recess provided at the center of the tip of the electrode terminal 1, and the tip thereof is configured to hold a wiring pattern 4 described later. 2 is a bare IC, 3 is a wiring board, 4 is a wiring pattern of the wiring board 3, 6 is a conductive paste, 7 is an insulating paste, and the electrode terminal 1 is shown in FIG. Such a hollow crack-shaped recess 1b is provided, and its height is leveled and joined to the bare IC 2. The formation of the recess 1b and the leveling of the height are simultaneously performed by the capillary shown in FIG. That is, when the top portion 8a of the capillary 8 is brought into pressure contact with the electrode terminal 1, the leveling and the formation of the hollow portion 1b in the electrode terminal 1 by the blade-shaped protrusion 8c are performed simultaneously, and FIG. It will be in the state shown in.
[0013]
The bare IC or flip chip IC formed in this way is mounted as follows. As shown in FIG. 3B, the electrode terminal 1 and the wiring pattern 4 are pressure-bonded through a process of applying the conductive paste 6 only to the vicinity of the tip of the electrode terminal 1. In this joining process, the wiring pattern 4 is held by the hollow-shaped recess 1b, and part of the conductive filler contained in the conductive paste 6 enters the recess 1b and hardly flows to the outside as the entire conductive filler. At the same time, the conductive filler in the portion overflowing from the recess 1b is interposed between the electrode terminal 1 and the wiring pattern 4, so that, together with the holding of the wiring pattern 4 by the recess 1b, It is securely joined and the reliability of the conductive connection is greatly improved. An insulating paste 7 is filled between the bare IC 2 including the portion where the conductive paste 6 is applied and the wiring board 3.
[0014]
As described above, according to the present embodiment, the reliability of the conductive connection between the electrode terminal and the wiring pattern is such that the conductive filler interposed between the electrode terminal and the wiring pattern and the wiring pattern due to the depression are connected. It is possible to greatly improve by holding, and at the same time, there is no possibility of inducing a short circuit between electrodes unlike the conventional one. Further, the expensive conductive paste is applied only in the vicinity of the tip portion of the electrode terminal, and the other portions may be filled with an inexpensive insulating paste, so that the cost can be reduced.
[0015]
【The invention's effect】
As described above, according to the present invention, since the conductive filler of the conductive paste is surely interposed between the electrode terminal and the wiring pattern , and the recess of the electrode terminal holds the wiring pattern, the reliability of the conductive connection is greatly increased. In addition, an advantageous effect that costs can be reduced and the cost can be reduced.
[Brief description of the drawings]
In reference example of the electrode terminals of the integrated circuit of FIG. 1 is a perspective view and a side view showing the configuration and use state of the definitive reference example in the form status of implementation of the electrode terminals of the integrated circuit of the present invention the present invention; FIG and leveling, perspective view of a capillary which also serves as a tip machining FIG. 3 is a perspective view and a side view showing the configuration and use state definitive the form status of implementation of the electrode terminals of the integrated circuit of the present invention [4] the present invention perspective view and a side view Figure shows the leveling definitive the form status of implementation of the electrode terminals of the integrated circuit, perspective view of a capillary which also serves as a tip machining [5] and the electrode terminals of the conventional integrated circuits that use state of the 6 is an explanatory diagram showing the state of the conductive paste when the electrode terminal of the conventional integrated circuit and the wiring pattern of the wiring board are connected.
DESCRIPTION OF SYMBOLS 1 Electrode terminal 1a Reverse cone-shaped dent 1b Middle crack-shaped dent 2 Bare IC
3 Wiring Board 4 Wiring Pattern 5 Anisotropic Conductive Paste 6 Conductive Paste 7 Insulating Paste 8 Capillary

Claims (3)

くぼみを有する電極端子を設けた集積回路と、
導電性ペーストにより前記電極端子と接続する配線パターンを有した配線基板とを備え、前記配線パターンを前記くぼみが挾持していることを特徴とする集積回路の実装体。An integrated circuit provided with electrode terminals having depressions;
An integrated circuit package comprising: a wiring board having a wiring pattern connected to the electrode terminal by a conductive paste, wherein the recess holds the wiring pattern. 前記くぼみは、中割れ状態であることを特徴とする請求項１記載の集積回路の実装体。2. The integrated circuit package according to claim 1, wherein the indentation is in an intermediate cracked state . くぼみを有する電極端子を設けた集積回路と配線基板を接続する工程を有する集積回路の実装方法であって、
前記くぼみに導電性ペーストを塗布する工程と、
前記配線基板に設けた配線パターンを前記くぼみにより挾持し、かつ前記電極端子と前記配線パターン間を前記導電性ペーストにより接続する工程と、
を備えたことを特徴とする集積回路の実装方法。 An integrated circuit mounting method comprising a step of connecting an integrated circuit provided with an electrode terminal having a depression and a wiring board,
Applying a conductive paste to the recess ;
Holding the wiring pattern provided on the wiring board by the depression, and connecting the electrode terminal and the wiring pattern by the conductive paste;
Implementation of that current product circuit to comprising the.
JP29555397A 1997-10-28 1997-10-28 Integrated circuit mounting body and integrated circuit mounting method Expired - Fee Related JP3745890B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29555397A JP3745890B2 (en) 1997-10-28 1997-10-28 Integrated circuit mounting body and integrated circuit mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29555397A JP3745890B2 (en) 1997-10-28 1997-10-28 Integrated circuit mounting body and integrated circuit mounting method

Publications (2)

Publication Number Publication Date
JPH11135558A JPH11135558A (en) 1999-05-21
JP3745890B2 true JP3745890B2 (en) 2006-02-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP29555397A Expired - Fee Related JP3745890B2 (en) 1997-10-28 1997-10-28 Integrated circuit mounting body and integrated circuit mounting method

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