JP3744431B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3744431B2
JP3744431B2 JP2002023940A JP2002023940A JP3744431B2 JP 3744431 B2 JP3744431 B2 JP 3744431B2 JP 2002023940 A JP2002023940 A JP 2002023940A JP 2002023940 A JP2002023940 A JP 2002023940A JP 3744431 B2 JP3744431 B2 JP 3744431B2
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Japan
Prior art keywords
bonding
conductive member
semiconductor element
wire
semiconductor
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JP2002023940A
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Japanese (ja)
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JP2003229449A (en
Inventor
公守 濱田
秀史 高谷
秀樹 戸嶋
武志 深見
正和 山添
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Toyota Motor Corp
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Toyota Motor Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子に設けられた電極と回路側に設けられた電極がボンディングワイヤを介して電気的に接続された半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
半導体素子の上面に設けられた電極（素子側電極）と、この半導体素子が実装される回路側に設けられた電極（回路側電極）とを、ワイヤボンディングにより電気的に接続した半導体装置が知られている。例えば特開平７−２９９３３号公報には、半導体素子に設けられた複数の素子側電極パッド（主電流電極群）のそれぞれにボンディングワイヤの一端を接続し、それらのボンディングワイヤの他端を電気絶縁基板上の電極パッド（回路側電極パッド）に接続した電力用半導体装置が開示されている。
【０００３】
【発明が解決しようとする課題】
ところで、半導体素子の小型化が進むにつれて各素子側電極パッドのサイズやパッド相互の間隔は小さくなる傾向にある。このためワイヤボンディングの精度（位置精度、形状精度等）をさらに高めることが求められている。特に、素子側電極パッド相互の間にワイヤボンディングに適さない領域（非ボンディング領域）が存在する場合にはこのような高精度化に対する要請が大きい。しかし、ワイヤボンディングの精度を高めようとすると半導体素子の生産性（作業性）が低下しがちであった。
【０００４】
そこで本発明は、素子側電極パッドにボンディングワイヤが電気的に接続された構成であって、そのワイヤボンディング時の作業性に優れた半導体装置を提供することを目的とする。本発明の他の目的は、そのような半導体装置の製造方法を提供することである。
【０００５】
【課題を解決するための手段と作用と効果】
本発明者は、非ボンディング領域を挟んで配置された二以上の素子側電極パッドを、それらのパッドの間に非ボンディング領域を跨いで掛け渡された導電部材により連結することによって上記課題を解決できることを見出した。
【０００６】
本発明により提供される半導体装置は、素子側電極パッドが設けられている半導体素子の複数個と、その複数の半導体素子間に設けられている非ボンディング領域を跨いで、複数の素子側電極パッドに共通的に接合された導電部材を備えている。その導電部材にはボンディングワイヤが接続されている。
かかる構成によると、複数の半導体素子と回路側電極とを同時に接続することができる。これにより、ワイヤボンディング時の作業性、および半導体装置の生産性が向上する。また、非ボンディング領域を跨ぐ部分の導電部材（導電部材を備えない構成ではワイヤボンディングを行うことができなかった部分）にもボンディングワイヤを接続することができる。すなわち、非ボンディング領域の位置を気にすることなく（非ボンディング領域を避けることなく）ワイヤボンディングを行うことができる。このことによって、本発明の半導体装置を製造するにあたってワイヤボンディング時の作業性を向上させ得る。また、各半導体素子の素子側電極パッドの其々にワイヤボンディングを行う場合と比較して、ボンディングワイヤの本数を少なくすることができる。
【０００７】
このような接続構造は、素子側電極パッドのうち駆動用電極パッドに対して好ましく適用される。また、このような接続構造を制御用電極パッドに適用してもよい。駆動用電極パッドおよび制御用電極パッドの双方に前記接続構造をそれぞれ適用してもよい。本発明の半導体装置のうち好ましいものでは、前記接続構造が少なくとも駆動用電極パッドに適用されている。
【０００８】
本発明により提供される半導体装置の製造方法は、素子側電極パッドが設けられている半導体素子の複数個を、間に非ボンディング領域を設けて回路基板に接合する工程を備える。また、その複数の半導体素子間に設けられている非ボンディング領域を跨いで、複数の素子側電極パッドに導電部材を共通的に接合する工程を備える。さらに、その接続された導電部材にワイヤボンディングを行う工程を備える。かかる製造方法は、本発明のいずれかの半導体装置を製造する方法として好適である。
【０００９】
特に限定するものではないが、本発明の半導体装置またはその製造方法の好ましい態様によると、以下に挙げる一または二以上の効果を得ることができる。
【００１０】
導電部材を用いることにより、二以上の素子側電極パッドにそれぞれワイヤボンディングを行う場合に比べて、ワイヤボンディングに適した領域を広く確保することができる。したがって、ワイヤボンディングの位置精度の許容範囲を広くすることができる。このことによってワイヤボンディング時の作業性、ワイヤボンディングの信頼性（接続信頼性）、半導体装置製造時の生産性（作業性、歩留まり等）の少なくとも一つが向上する。また、ワイヤボンディングに適した領域を広く確保することができるので、より多い本数のボンディングワイヤを素子側電極に接続することが可能となる。このような接続構造は、電力用半導体素子の駆動用電極（エミッタ電極やコレクタ電極）と回路側電極（基板）との接続のように、大電流が流れる箇所に特に好ましく適用される。
【００１１】
ワイヤボンディングは導電部材に対して行われる。このため、素子側電極パッドに直接ワイヤボンディングを行う場合に比べて、ボンディング時の超音波および／または加圧力が半導体素子（特に素子側電極パッド）に及ぼす影響（ワイヤボンドダメージ）を低減することができる。したがって、より太いボンディングワイヤを用いることができる。このことによって半導体装置の性能（例えば、素子側電極から容易に大電流を取り出す性能）を向上させ得る。あるいは、使用するボンディングワイヤの本数を減らすことができる。このことによってワイヤボンディング時の作業性（半導体素子の生産性）が向上する。さらに、複数の素子側電極パッドを連結する導電部材にワイヤボンディングを行うことにより、素子側電極パッドの数よりも少ない本数のボンディングワイヤによって素子側電極と回路側電極とを接続することも可能である。このような構成は、例えば半導体素子の電流容量が比較的小さい場合に有効である。
【００１２】
非ボンディング領域を跨いで導電部材を配置することにより、この非ボンディング領域の上方に相当する部分にもワイヤボンディングを行うことが可能となる。これにより半導体素子の設計自由度が高められる。
パワーＭＯＳ，ＩＧＢＴ（Insulated Gate Bipolar Transistor），ＢＪＴ（Bipolar Junction Transistor），サイリスタ等のように素子のオン・オフをコントロールする制御電極を有する半導体素子（特に電力用半導体素子）では、この制御電極と接続された配線（ゲートフィンガー）を素子表面に設けることがある。このゲートフィンガーは駆動用電極とは分離されている必要がある。したがって従来は、ゲートフィンガーが設けられた箇所（非ボンディング領域）を避けて駆動用電極パッドへのワイヤボンディングを行っていた。このため所望のゲートフィンガー密度を確保し難くなる場合があった。また、太いボンディングワイヤを用いることが困難となる場合があった。本発明の半導体素子では、ゲートフィンガー（非ボンディング領域）の配置位置や配置密度とワイヤボンディングを行う位置をそれぞれ独立して定めることができる。これにより、破壊耐量、高周波特性、大電流特性の少なくとも一つを向上させることが可能である。
【００１３】
【発明の実施の形態】
この発明は、また、下記の形態で実施することを特徴とする。
【００１４】
（形態１） 本発明の半導体装置がパワーデバイスである。このパワーデバイスに備えられた電力用半導体素子の駆動用電極パッドと回路側電極との接続に本発明の接続構造が適用されている。
【００１５】
（形態２） 導電部材は、単一の半導体素子に設けられた二以上の駆動用電極パッドに共通的に接続されている。それらの電極パッドの間にはゲートフィンガーが配置されている。後述する第一実施例はこのような形態の一例である。
【００１６】
（形態３） 導電部材は、複数の半導体素子にそれぞれ設けられた一以上の素子側電極パッド（好ましくは駆動用電極パッド）に共通的に接続されている。この導電部材にワイヤボンディングを行うことにより、複数の半導体素子と回路側電極とを同時に接続することができる。このことによってワイヤボンディング時の作業性（半導体装置の生産性）が向上する。後述する第二実施例はこのような形態の一例である。
【００１７】
（形態４） 少なくとも一本のボンディングワイヤは、非ボンディング領域の上方を含む部分の導電部材に接続されている。
【００１８】
（形態５） 半導体素子の上面には、非ボンディング領域を被覆するとともに素子側電極パッドを露出させる絶縁保護層が設けられている。
【００１９】
【実施例】
以下、本発明の好適な実施例について詳細に説明する。
本発明の半導体装置に備えられる半導体素子としては各種の半導体素子（ＩＧＢＴ等のバイポーラトランジスタやＭＯＳ等の電界効果型トランジスタ等）を用いることができる。本発明の半導体装置がパワーデバイスである（典型的には、ＩＧＢＴ、パワーＭＯＳ等の電力用半導体素子を備える）場合には、本発明を適用することによる効果が特によく発揮される。
【００２０】
導電部材の構成材料としては、導電性および熱伝導性が高い材料が適している。また、ワイヤボンドダメージを抑制する効果を高めるためには高硬度の材料が好ましい。さらに、半導体素子との間に熱応力を発生させにくくするためには、導電部材の線膨張係数がＳｉに比較的近いことが好ましい。導電部材の構成材料として使用し得る材料の具体例としては、銅、銀、金、白金、ニッケル、コバルト、亜鉛、モリブデン、鉄、アルミニウム、チタン、タングステン等（これらのうち好ましいものは、銅、モリブデン、鉄、アルミニウム、ニッケル、銀、チタンまたはタングステンである）の純金属およびこれらの金属を主体とする合金等の金属材料が挙げられる。これらの金属材料の接合品（例えば積層品）を用いてもよい。このような金属材料の表面に半田濡れ性のよい金属（ニッケル、クロム、金等）がメッキされた導電部材を用いてもよい。また、金属以外の材料（セラミックス等）の表面を金属材料で覆った導電部材を用いてもよい。
【００２１】
この導電部材の形状は特に限定されない。大まかな形状が平板状である板状導電部材（金属板等）が好ましく用いられる。このような板状導電部材は、その一部に折れ曲がった箇所や湾曲した箇所を有していてもよい。導電部材は、その全体がほぼ同程度の厚さであってもよく、部分的に厚さが異なっていてもよい。ボンディングダメージを緩和するためには、素子側電極パッドに接合される部分の導電部材の厚さが５０μm以上（より好ましくは１００μm以上）であることが好ましい。導電部材の平均厚さが比較的大きい（例えば１００μm以上、好ましくは２００μm以上である）場合には、この導電部材の畜熱効果によって半導体素子の負荷短絡容量を向上させ得る。導電部材の平均厚さが半導体素子の平均厚さと同等以上である場合にはこの効果が特によく発揮される。
【００２２】
導電部材と素子側電極の接合は導電性接合材により行うことができる。この導電性接合材の典型例としては半田に代表される低融点金属類が挙げられる。また、有機高分子等からなるマトリックス樹脂中に導電性充填材が分散された導電性樹脂材料を導電性接合材として用いてもよい。このマトリックス樹脂としてはエポキシ樹脂、ポリイミド樹脂、フェノール樹脂、シリコーン樹脂等を用いることができる。導電性充填材としては、銅、銀、金、白金、ニッケル、カーボン等からなる導電性繊維、導電性微粒子等を用いることができる。
【００２３】
以下、本発明をパワーデバイスに適用した実施例につき図面を用いて説明する。
（第一実施例）
（１）半導体素子の構成
まず、このパワーデバイスに備えられる電力用半導体素子の構成を説明する。図１に示すように、電力用半導体素子（トレンチ型ＩＧＢＴ）１０を構成するシリコン基板１１には、その上面付近にベース層１２、エミッタ層１３およびゲート１４が埋め込まれている。ゲート１４とシリコン基板１１との間にはゲート酸化膜（図示せず）が形成されている。
【００２４】
シリコン基板１１の表面には、ゲート１３の上端を覆うとともにエミッタ層１４の一部を露出させる層間絶縁膜１５が設けられている。。半導体素子１０の上面には、エミッタ層１４の露出部分に接続されたエミッタ電極２２が設けられている。また、図１に示す断面においてゲート１３はいくつかの（図１では三つを示している）ゲート群を形成しており、それらのゲート群の間および外周側に位置する基板表面に層間絶縁膜１６が設けられている。この層間絶縁膜１６の上にゲートフィンガー２６が設けられている。さらにその上には、ゲートフィンガー２６を覆うとともにエミッタ電極２２の一部を露出させる表面保護膜（絶縁保護層）１７が設けられている。半導体素子１０の上面には、表面保護膜１７から露出されたエミッタ電極２２によって複数の（図１では三つを示している）エミッタ電極パッド２２ａが形成されている。
【００２５】
図２に示すように、半導体素子１０の表面にはゲート電極２４が設けられている。このゲート電極２４は、ゲートフィンガー２６の一端に接続されているとともに、図示しない部分においてゲート１３（図１参照）に接続されている。なお、図２は半導体素子１０の上面におけるゲート電極２４およびゲートフィンガー２６の配置を示す模式図であって、他の構成部分の図示は省略されている。
【００２６】
図１および図３に示すように、半導体素子１０の上面に設けられた複数のエミッタ電極パッド２２ａには、半田５０によって一枚の金属板３０が共通的に接合されている。この金属板３０は、ゲートフィンガー２６や表面保護膜１７の設けられた部分（非ボンディング領域）を跨いで、複数の電極パッド２２ａを連結している。この金属板３０の上面に複数本のボンディングワイヤ４０のそれぞれ一端が接続されている。このように、半田５０および金属板３０を介してボンディングワイヤ４０が複数の電極パッド２２ａに電気的に接続されている。ここで使用した金属板３０の全体形状は平板状であって、その厚さは約３００μmである。この金属板３０は線膨張係数が比較的Ｓｉに近い材質を主体として構成され、その表面にはニッケルメッキが施されている。このニッケルメッキによって半田付性およびワイヤボンディング性を向上させている。また、図３および図４に示すように、ゲート電極２４の上面にはボンディングワイヤ４２の一端が直接接続されている。
【００２７】
図４に示すように、半導体素子１０の下面は半田５２によってセラミックス（例えば窒化アルミニウム）を主体とする絶縁基板７０上に設けられた回路配線（図示せず）に接続されている。また、ボンディングワイヤ４０，４２は図示しない部分において回路配線に接続されている。
なお、図１は図３のＩ−Ｉ線断面図に相当し、図４は図３のIV−IV線断面図に相当する。図３および図４では、説明の簡略化のために、半導体素子１０の構造の一部を省略して示している。
【００２８】
本実施例によると、図１および図３に示すように、非ボンディング領域の上方に位置する部分（例えばゲートフィンガー２６の直上）の金属板３０にもボンディングワイヤ４０を接続することができる。したがって、各電極パッド２２ａにそれぞれ直接ワイヤボンディングを行う構成に比べてワイヤボンディングに適した領域を広く確保することができる。これにより、ワイヤボンディングの位置精度の制約（許容範囲）が緩和される。また、絶縁基板７０（図４参照）に対する半導体素子１０の接合位置および／または図示しないハウジングに対する絶縁基板７０の接合位置についても、その位置精度の制約を緩和することができる。このことによってワイヤボンディング時の作業性を向上させることができる。
【００２９】
ワイヤボンディングは半田５０および金属板３０を介して行われるので、各電極パッド２２ａに直接ワイヤボンディングを行う構成に比べて半導体素子１０（特に電極パッド２２ａ）に対するワイヤボンドダメージが低減される。
また、一般的なリードフレームに比べてボンディングワイヤ４０は柔軟性に優れる。このため、電極パッド２２ａと回路配線との相対位置がバラついた場合にも、ボンディングワイヤ４０の柔軟性を利用してそのバラつきを吸収することができる。したがって、絶縁基板７０に対する半導体素子１０の接合位置および／または図示しないハウジングに対する絶縁基板７０の接合位置の精度の制約を緩和することができる。このことによって半導体装置の生産性（作業性、歩留まり等）を向上させ得る。
【００３０】
なお、上記実施例の半導体装置では半導体素子のうちエミッタ電極パッドが設けられた側を上面とし、このエミッタ電極パッドに金属板を接合したが、この実施例とは半導体素子の上下を反転させて半導体装置を構成することもできる。すなわち、半導体素子のうちコレクタ電極パッドが設けられた側を上面としてコレクタ電極パッドに金属板を接合し、この金属板にワイヤボンディングを行ってもよい。
【００３１】
（第二実施例）
この第二実施例は、二つの半導体素子を備えたパワーデバイスの一例である。以下、第一実施例に係る部材と同様の機能を果たす部材については同じ符号を付し、その説明を省略する。
【００３２】
図５および図６に示すように、一枚の絶縁基板７０上に第一の半導体素子１０および第二の半導体素子６０がそれぞれ半田５２によって接合されている。これにより、半導体素子１０，６０の下面に設けられたコレクタ電極（図示せず）が絶縁基板７０の上面に設けられた回路配線７１に接続されている。絶縁基板７０の下面には放熱用の金属層７２が設けられており、この下面が半田５４によって放熱板７４に接合されている。このようにして、半導体素子１０，６０の作動時に発生する熱を放熱するように半導体装置が構成されている。放熱板７４の下面はハウジング７６（図６では省略）に接合されている。このハウジング７６の上面には回路配線７８ａ，７８ｂ，７８ｃが設けられている。半導体素子１０の上面に設けられたゲート電極２４（図５参照）は、このゲート電極２４に直接接続されたボンディングワイヤ４２により回路配線７８ｂに接続されている。絶縁基板７０上に設けられた回路配線７１は、この回路配線７１に直接接続されたボンディングワイヤ４４により回路配線７８ｃに接続されている。
【００３３】
半導体素子１０の上面には少なくとも一つの（図５では六つを示している）エミッタ電極パッド２２ａが設けられている。また、半導体素子６０の上面には少なくとも一つの（図５では一つを示している）エミッタ電極パッド２２ｂが設けられている。これらの電極パッド２２ａ，２２ｂには、図６（電極パッド２２ａ，２２ｂの図示は省略している）に示すように、半田５０によって一枚の金属板３０が共通的に接続されている。すなわち金属板３０は、半導体素子１０と半導体素子６０との間の領域（非ボンディング領域）を跨いで、半導体素子１０に設けられた複数の電極パッド２２ａと半導体素子６０に設けられた電極パッド２２ｂとを連結している。この金属板３０の上面に複数本のボンディングワイヤ４０のそれぞれ一端が接続されている。ボンディングワイヤ４０の他端は回路配線７８ａに接続されている。
【００３４】
このような構成とすることにより、複数の半導体素子（半導体素子１０，６０）に設けられた電極パッド２２ａおよび電極パッド２２ｂを、ボンディングワイヤ４０によって回路配線７８ａに一度に接続することができる。このボンディングワイヤ４０の本数は、電極パッド２２ａと電極パッド２２ｂの合計数よりも少なくすることが可能である。
【００３５】
以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
【図面の簡単な説明】
【図１】 第一実施例に係る半導体素子を示す模式的断面図である。
【図２】 ゲート電極およびゲートフィンガーの配置を示す模式図である。
【図３】 図１のIII方向矢視図である。
【図４】 図３のIV−IV線断面に相当する部分で第一実施例に係る半導体装置の要部を示す断面図である。
【図５】 第二実施例に係る半導体装置の要部を示す平面図である。
【図６】 図５のVI−VI線断面図である。
【符号の説明】
１０，６０：電力用半導体素子（半導体素子）
１５，１６：層間絶縁膜
１７：表面保護膜（絶縁保護層）
２２：エミッタ電極（素子側電極）
２２ａ，２２ｂ：エミッタ電極パッド（素子側電極パッド、駆動用電極パッド）
２４：ゲート電極（素子側電極）
２６：ゲートフィンガー
３０：金属板（導電部材）
４０，４２，４４：ボンディングワイヤ
５０，５２，５４：半田
７０：絶縁基板（回路基板）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which an electrode provided on a semiconductor element and an electrode provided on a circuit side are electrically connected via a bonding wire, and a manufacturing method thereof.
[0002]
[Prior art]
A semiconductor device is known in which an electrode (element side electrode) provided on the upper surface of a semiconductor element and an electrode (circuit side electrode) provided on a circuit side on which the semiconductor element is mounted are electrically connected by wire bonding. It has been. For example, in Japanese Patent Laid-Open No. 7-29933, one end of a bonding wire is connected to each of a plurality of element side electrode pads (main current electrode group) provided in a semiconductor element, and the other end of the bonding wire is electrically insulated. A power semiconductor device connected to an electrode pad (circuit side electrode pad) on a substrate is disclosed.
[0003]
[Problems to be solved by the invention]
By the way, as the miniaturization of the semiconductor element progresses, the size of each element-side electrode pad and the distance between the pads tend to decrease. For this reason, it is required to further improve the accuracy of wire bonding (position accuracy, shape accuracy, etc.). In particular, when there is a region (non-bonding region) that is not suitable for wire bonding between the element side electrode pads, there is a great demand for such high accuracy. However, the productivity (workability) of the semiconductor element tends to be lowered when trying to increase the accuracy of wire bonding.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure in which a bonding wire is electrically connected to an element-side electrode pad and having excellent workability at the time of wire bonding. Another object of the present invention is to provide a method for manufacturing such a semiconductor device.
[0005]
[Means, actions and effects for solving problems]
The inventor solves the above problem by connecting two or more element-side electrode pads arranged across a non-bonding region with a conductive member that spans the non-bonding region between the pads. I found out that I can do it.
[0006]
A semiconductor device provided by the present invention includes a plurality of element-side electrode pads across a plurality of semiconductor elements provided with element-side electrode pads and a non-bonding region provided between the plurality of semiconductor elements. And a conductive member joined in common. A bonding wire is connected to the conductive member.
According to such a configuration, a plurality of semiconductor elements and circuit side electrodes can be connected simultaneously. Thereby, the workability at the time of wire bonding and the productivity of the semiconductor device are improved. Also, the bonding wire can be connected to a portion of the conductive member straddling the non-bonding region (a portion where wire bonding cannot be performed in a configuration without the conductive member). That is, wire bonding can be performed without worrying about the position of the non-bonding region (without avoiding the non-bonding region). This can improve the workability during wire bonding in manufacturing the semiconductor device of the present invention. In addition, the number of bonding wires can be reduced as compared with the case where wire bonding is performed on each of the element-side electrode pads of each semiconductor element.
[0007]
Such a connection structure is preferably applied to the driving electrode pad among the element side electrode pads. Such a connection structure may be applied to the control electrode pad. The connection structure may be applied to both the driving electrode pad and the control electrode pad. In a preferred semiconductor device of the present invention, the connection structure is applied to at least a driving electrode pad.
[0008]
A method for manufacturing a semiconductor device provided by the present invention includes a step of bonding a plurality of semiconductor elements provided with element-side electrode pads to a circuit board by providing a non-bonding region therebetween. Further, a step of commonly bonding the conductive member to the plurality of element-side electrode pads across the non-bonding region provided between the plurality of semiconductor elements is provided. Furthermore, a step of performing wire bonding on the connected conductive member is provided. Such a manufacturing method is suitable as a method for manufacturing any one of the semiconductor devices of the present invention.
[0009]
Although not particularly limited, according to a preferred embodiment of the semiconductor device of the present invention or the method for manufacturing the same, one or more of the following effects can be obtained.
[0010]
By using a conductive member, a region suitable for wire bonding can be secured wider than when wire bonding is performed on two or more element-side electrode pads. Therefore, the allowable range of the positional accuracy of wire bonding can be widened. This improves at least one of workability at the time of wire bonding, reliability of wire bonding (connection reliability), and productivity (workability, yield, etc.) at the time of manufacturing a semiconductor device. In addition, since a wide area suitable for wire bonding can be secured, a larger number of bonding wires can be connected to the element-side electrode. Such a connection structure is particularly preferably applied to a location where a large current flows, such as a connection between a driving electrode (emitter electrode or collector electrode) of a power semiconductor element and a circuit side electrode (substrate).
[0011]
Wire bonding is performed on the conductive member. For this reason, compared with the case where wire bonding is directly performed on the element side electrode pad, the influence (wire bond damage) exerted on the semiconductor element (particularly the element side electrode pad) by the ultrasonic wave and / or the applied pressure during bonding is reduced. Can do. Therefore, a thicker bonding wire can be used. This can improve the performance of the semiconductor device (for example, the ability to easily extract a large current from the element-side electrode). Alternatively, the number of bonding wires used can be reduced. This improves the workability at the time of wire bonding (semiconductor element productivity). Furthermore, by performing wire bonding on a conductive member that connects a plurality of element side electrode pads, it is also possible to connect the element side electrodes and circuit side electrodes with a smaller number of bonding wires than the number of element side electrode pads. is there. Such a configuration is effective, for example, when the current capacity of the semiconductor element is relatively small.
[0012]
By disposing the conductive member across the non-bonding region, it is possible to perform wire bonding on a portion corresponding to the upper portion of the non-bonding region. This increases the degree of freedom in designing the semiconductor element.
In a semiconductor element (especially a power semiconductor element) having a control electrode for controlling on / off of the element such as a power MOS, IGBT (Insulated Gate Bipolar Transistor), BJT (Bipolar Junction Transistor), and thyristor, A connected wiring (gate finger) may be provided on the element surface. This gate finger needs to be separated from the driving electrode. Therefore, conventionally, wire bonding to the drive electrode pad has been performed avoiding the location (non-bonding region) where the gate finger is provided. For this reason, it may be difficult to secure a desired gate finger density. Also, it may be difficult to use a thick bonding wire. In the semiconductor element of the present invention, the arrangement position and arrangement density of the gate fingers (non-bonding regions) and the position for wire bonding can be determined independently. Thereby, it is possible to improve at least one of breakdown tolerance, high frequency characteristics, and large current characteristics.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is also characterized by being implemented in the following forms.
[0014]
(Embodiment 1) The semiconductor device of the present invention is a power device. The connection structure of the present invention is applied to the connection between the driving electrode pad of the power semiconductor element provided in this power device and the circuit side electrode.
[0015]
(Mode 2) The conductive member is commonly connected to two or more drive electrode pads provided in a single semiconductor element. Gate fingers are arranged between the electrode pads. The first embodiment described later is an example of such a form.
[0016]
(Mode 3) The conductive member is commonly connected to one or more element-side electrode pads (preferably drive electrode pads) provided in each of the plurality of semiconductor elements. By performing wire bonding on this conductive member, a plurality of semiconductor elements and circuit side electrodes can be connected simultaneously. This improves the workability during wire bonding (semiconductor device productivity). A second embodiment to be described later is an example of such a form.
[0017]
(Mode 4) At least one bonding wire is connected to a portion of the conductive member including the upper part of the non-bonding region.
[0018]
(Mode 5) An insulating protective layer is provided on the upper surface of the semiconductor element to cover the non-bonding region and expose the element-side electrode pad.
[0019]
【Example】
Hereinafter, preferred embodiments of the present invention will be described in detail.
As the semiconductor element provided in the semiconductor device of the present invention, various semiconductor elements (bipolar transistors such as IGBT and field effect transistors such as MOS) can be used. When the semiconductor device of the present invention is a power device (typically including a power semiconductor element such as an IGBT or a power MOS), the effect of applying the present invention is particularly well exhibited.
[0020]
As a constituent material of the conductive member, a material having high conductivity and high thermal conductivity is suitable. In order to enhance the effect of suppressing wire bond damage, a material with high hardness is preferable. Furthermore, in order to make it difficult to generate thermal stress between the semiconductor element and the conductive member, it is preferable that the linear expansion coefficient of the conductive member is relatively close to Si. Specific examples of materials that can be used as the constituent material of the conductive member include copper, silver, gold, platinum, nickel, cobalt, zinc, molybdenum, iron, aluminum, titanium, tungsten, etc. (of these, copper, Examples thereof include pure materials such as molybdenum, iron, aluminum, nickel, silver, titanium, and tungsten, and metal materials such as alloys mainly composed of these metals. A joined product (for example, a laminated product) of these metal materials may be used. A conductive member in which a metal (nickel, chromium, gold, etc.) with good solder wettability is plated on the surface of such a metal material may be used. Moreover, you may use the electrically-conductive member which covered the surface of materials (ceramics etc.) other than a metal with the metal material.
[0021]
The shape of the conductive member is not particularly limited. A plate-like conductive member (such as a metal plate) whose rough shape is flat is preferably used. Such a plate-like conductive member may have a bent part or a curved part. The entire conductive member may be approximately the same thickness, or may be partially different in thickness. In order to alleviate the bonding damage, it is preferable that the thickness of the conductive member in the portion bonded to the element-side electrode pad is 50 μm or more (more preferably 100 μm or more). When the average thickness of the conductive member is relatively large (for example, 100 μm or more, preferably 200 μm or more), the load short-circuit capacity of the semiconductor element can be improved by the livestock heat effect of the conductive member. This effect is particularly well exhibited when the average thickness of the conductive member is equal to or greater than the average thickness of the semiconductor element.
[0022]
The conductive member and the element-side electrode can be joined with a conductive bonding material. Typical examples of the conductive bonding material include low melting point metals represented by solder. Alternatively, a conductive resin material in which a conductive filler is dispersed in a matrix resin made of an organic polymer or the like may be used as the conductive bonding material. As this matrix resin, an epoxy resin, a polyimide resin, a phenol resin, a silicone resin, or the like can be used. As the conductive filler, conductive fibers made of copper, silver, gold, platinum, nickel, carbon, conductive fine particles, or the like can be used.
[0023]
Hereinafter, embodiments in which the present invention is applied to a power device will be described with reference to the drawings.
(First Example)
(1) Configuration of Semiconductor Element First, the configuration of the power semiconductor element provided in the power device will be described. As shown in FIG. 1, a base layer 12, an emitter layer 13, and a gate 14 are embedded in the vicinity of the upper surface of a silicon substrate 11 constituting a power semiconductor element (trench IGBT) 10. A gate oxide film (not shown) is formed between the gate 14 and the silicon substrate 11.
[0024]
An interlayer insulating film 15 that covers the upper end of the gate 13 and exposes part of the emitter layer 14 is provided on the surface of the silicon substrate 11. . An emitter electrode 22 connected to the exposed portion of the emitter layer 14 is provided on the upper surface of the semiconductor element 10. In the cross section shown in FIG. 1, the gate 13 forms several gate groups (three are shown in FIG. 1), and interlayer insulation is provided between the gate groups and on the substrate surface located on the outer peripheral side. A membrane 16 is provided. Gate fingers 26 are provided on the interlayer insulating film 16. Further thereon, a surface protective film (insulating protective layer) 17 that covers the gate finger 26 and exposes a part of the emitter electrode 22 is provided. On the upper surface of the semiconductor element 10, a plurality of emitter electrode pads 22 a (three are shown in FIG. 1) are formed by the emitter electrode 22 exposed from the surface protective film 17.
[0025]
As shown in FIG. 2, a gate electrode 24 is provided on the surface of the semiconductor element 10. The gate electrode 24 is connected to one end of the gate finger 26 and is connected to the gate 13 (see FIG. 1) at a portion not shown. FIG. 2 is a schematic diagram showing the arrangement of the gate electrode 24 and the gate finger 26 on the upper surface of the semiconductor element 10, and other components are not shown.
[0026]
As shown in FIGS. 1 and 3, a single metal plate 30 is commonly bonded to the plurality of emitter electrode pads 22 a provided on the upper surface of the semiconductor element 10 by solder 50. The metal plate 30 connects a plurality of electrode pads 22a across a portion (non-bonding region) where the gate finger 26 and the surface protective film 17 are provided. One end of each of a plurality of bonding wires 40 is connected to the upper surface of the metal plate 30. Thus, the bonding wire 40 is electrically connected to the plurality of electrode pads 22a via the solder 50 and the metal plate 30. The overall shape of the metal plate 30 used here is a flat plate, and the thickness thereof is about 300 μm. The metal plate 30 is mainly composed of a material having a linear expansion coefficient relatively close to Si, and the surface thereof is plated with nickel. This nickel plating improves solderability and wire bonding. As shown in FIGS. 3 and 4, one end of the bonding wire 42 is directly connected to the upper surface of the gate electrode 24.
[0027]
As shown in FIG. 4, the lower surface of the semiconductor element 10 is connected by solder 52 to circuit wiring (not shown) provided on an insulating substrate 70 mainly made of ceramics (for example, aluminum nitride). The bonding wires 40 and 42 are connected to the circuit wiring at a portion not shown.
1 corresponds to a cross-sectional view taken along a line II in FIG. 3, and FIG. 4 corresponds to a cross-sectional view taken along a line IV-IV in FIG. 3 and 4, a part of the structure of the semiconductor element 10 is omitted for simplification of description.
[0028]
According to the present embodiment, as shown in FIGS. 1 and 3, the bonding wire 40 can be connected to the metal plate 30 in the portion located above the non-bonding region (for example, immediately above the gate finger 26). Accordingly, it is possible to secure a wider area suitable for wire bonding than a configuration in which wire bonding is performed directly on each electrode pad 22a. Thereby, the restriction | limiting (allowable range) of the position accuracy of wire bonding is eased. Further, the positional accuracy of the bonding position of the semiconductor element 10 with respect to the insulating substrate 70 (see FIG. 4) and / or the bonding position of the insulating substrate 70 with respect to the housing (not shown) can be relaxed. This can improve workability during wire bonding.
[0029]
Since wire bonding is performed via the solder 50 and the metal plate 30, wire bond damage to the semiconductor element 10 (particularly the electrode pad 22a) is reduced as compared with a configuration in which wire bonding is performed directly on each electrode pad 22a.
Further, the bonding wire 40 is more flexible than a general lead frame. For this reason, even when the relative position between the electrode pad 22a and the circuit wiring varies, the variation of the bonding wire 40 can be absorbed. Therefore, it is possible to relax restrictions on the accuracy of the bonding position of the semiconductor element 10 to the insulating substrate 70 and / or the bonding position of the insulating substrate 70 to the housing (not shown). This can improve the productivity (workability, yield, etc.) of the semiconductor device.
[0030]
In the semiconductor device of the above embodiment, the side of the semiconductor element on which the emitter electrode pad is provided is the upper surface, and a metal plate is bonded to the emitter electrode pad. A semiconductor device can also be configured. That is, a metal plate may be bonded to the collector electrode pad with the side of the semiconductor element on which the collector electrode pad is provided as the upper surface, and wire bonding may be performed on the metal plate.
[0031]
(Second embodiment)
The second embodiment is an example of a power device provided with two semiconductor elements. Hereinafter, members having the same functions as those according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0032]
As shown in FIGS. 5 and 6, the first semiconductor element 10 and the second semiconductor element 60 are joined to each other by solder 52 on one insulating substrate 70. Thereby, collector electrodes (not shown) provided on the lower surfaces of the semiconductor elements 10 and 60 are connected to circuit wiring 71 provided on the upper surface of the insulating substrate 70. A heat dissipation metal layer 72 is provided on the lower surface of the insulating substrate 70, and this lower surface is joined to the heat dissipation plate 74 by solder 54. In this way, the semiconductor device is configured to dissipate heat generated when the semiconductor elements 10 and 60 are operated. The lower surface of the heat sink 74 is joined to a housing 76 (not shown in FIG. 6). Circuit wirings 78 a, 78 b, 78 c are provided on the upper surface of the housing 76. The gate electrode 24 (see FIG. 5) provided on the upper surface of the semiconductor element 10 is connected to the circuit wiring 78b by a bonding wire 42 directly connected to the gate electrode 24. The circuit wiring 71 provided on the insulating substrate 70 is connected to the circuit wiring 78 c by the bonding wire 44 directly connected to the circuit wiring 71.
[0033]
At least one emitter electrode pad 22 a (six are shown in FIG. 5) is provided on the upper surface of the semiconductor element 10. Further, at least one emitter electrode pad 22b (one is shown in FIG. 5) is provided on the upper surface of the semiconductor element 60. A single metal plate 30 is commonly connected to these electrode pads 22a and 22b by solder 50 as shown in FIG. 6 (illustration of the electrode pads 22a and 22b is omitted). That is, the metal plate 30 straddles a region (non-bonding region) between the semiconductor element 10 and the semiconductor element 60, and a plurality of electrode pads 22 a provided in the semiconductor element 10 and an electrode pad 22 b provided in the semiconductor element 60. Are linked. One end of each of a plurality of bonding wires 40 is connected to the upper surface of the metal plate 30. The other end of the bonding wire 40 is connected to the circuit wiring 78a.
[0034]
With such a configuration, the electrode pads 22 a and the electrode pads 22 b provided on the plurality of semiconductor elements (semiconductor elements 10 and 60) can be connected to the circuit wiring 78 a at once by the bonding wires 40. The number of bonding wires 40 can be made smaller than the total number of electrode pads 22a and electrode pads 22b.
[0035]
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a semiconductor element according to a first embodiment.
FIG. 2 is a schematic diagram showing the arrangement of gate electrodes and gate fingers.
FIG. 3 is a view in the direction of the arrow III in FIG.
4 is a cross-sectional view showing a main part of the semiconductor device according to the first embodiment at a portion corresponding to a cross section taken along line IV-IV in FIG. 3;
FIG. 5 is a plan view showing a main part of a semiconductor device according to a second embodiment.
6 is a cross-sectional view taken along line VI-VI in FIG.
[Explanation of symbols]
10, 60: Power semiconductor element (semiconductor element)
15, 16: Interlayer insulating film 17: Surface protective film (insulating protective layer)
22: Emitter electrode (element side electrode)
22a, 22b: Emitter electrode pads (element-side electrode pads, drive electrode pads)
24: Gate electrode (element side electrode)
26: Gate finger 30: Metal plate (conductive member)
40, 42, 44: Bonding wires 50, 52, 54: Solder 70: Insulating substrate (circuit board)

Claims (3)

素子側電極パッドが設けられている半導体素子の複数個と、
その複数の半導体素子間に設けられている非ボンディング領域を跨いで、複数の素子側電極パッドに共通的に接合された導電部材と、
その導電部材に接続されたボンディングワイヤとを備える半導体装置。 A plurality of semiconductor elements provided with element-side electrode pads;
A conductive member commonly bonded to the plurality of element-side electrode pads across the non-bonding region provided between the plurality of semiconductor elements ;
A semiconductor device comprising a bonding wire connected to the conductive member. 前記素子側電極パッドは駆動用電極パッドである請求項１に記載の半導体装置。Before the semiconductor device according to claim 1 Kimoto slave electrode pad is a driving electrode pad. 素子側電極パッドが設けられている半導体素子の複数個を、間に非ボンディング領域を設けて回路基板に接合する工程と、
その複数の半導体素子間に設けられている非ボンディング領域を跨いで、複数の素子側電極パッドに導電部材を共通的に接合する工程と、
その接続された導電部材にワイヤボンディングを行う工程とを含む半導体装置の製造方法。 A plurality of semiconductor devices containing slave electrode pads are provided, and bonding to the circuit board by providing a non-bonding region between,
A step of commonly bonding a conductive member to a plurality of element-side electrode pads across a non-bonding region provided between the plurality of semiconductor elements ;
A method of manufacturing a semiconductor device including a step of performing wire bonding on the connected conductive member.
JP2002023940A 2002-01-31 2002-01-31 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3744431B2 (en)

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WO2005071733A1 (en) * 2004-01-26 2005-08-04 Hitachi, Ltd. Semiconductor device, power converter employing it, motor employing it, hybrid automobile employing it, and motor drive system employing it
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