JP3743000B2 - Signal conversion apparatus and method - Google Patents

Description

【００６８】
比較器１２４は、レジスタ１２３に保持されている値Ｓと、レジスタ１２６に保持されている閾値とを比較し、例えば、値Ｓの方が閾値より大きいとき１を、小さいとき０を、エンコーダ１２８に出力する。同様に、比較器１２５は、レジスタ１２３に保持されている値Ｓと、レジスタ１２７に保持されている閾値（レジスタ１２６に保持されている閾値より小さい値とされている）を比較し、例えば、値Ｓの方が閾値より大きいとき１を、小さいとき０を、エンコーダ１２８に出力する。エンコーダ１２８は、比較器１２４と１２５の出力がいずれも０であるとき、主に動きの程度を表すためのクラス（動きクラス）として０を出力し、比較器１２４の出力が０であり、比較器１２５の出力が１であるとき１を出力し、比較器１２４の出力が１である場合は、比較器１２５の出力が０または１のいずれであったとしても２を出力する。
【００６９】
なお、以上においては、絶対値演算回路１０１，１０７，１１５で、差の絶対値を演算するようにしたが、差の絶対値の１／２を演算するようにしてもよい。この場合、レジスタ１２６，１２７に保持される値も、１画素当たりの差の絶対値に対応する値とされる。
【００７０】
図１６は、クラス分類部３３の構成例を表している。ＡＤＲＣ(Adaptive Dynamic Range Coding)エンコーダ１４０には、ディレイレジスタ部３１から、例えば、図１１に示すＳＤ画素ｋ１乃至ｋ５（図４のＳＤ画素ｘ５，ｘ８，ｘ１３，ｘ１８，ｘ２１に対応する）が入力される。また、ＡＤＲＣエンコーダ１４０には、最大値最小値演算部３２より出力した、空間クラスの最大値と最小値が入力されている。ＡＤＲＣエンコーダ１４０は、ＳＤ画素ｋ１乃至ｋ５の、それぞれの値をＬ、ＳＤ画素ｋ１乃至ｋ５のうちの最大値をＭＡＸ、最小値をＭＩＮとするとき、次式で表される再量子化コードＱを演算する。
Ｑ＝［（Ｌ−ＭＩＮ＋０．５）×２ⁿ／ＤＲ］
なお、［ ］は、切り捨て処理を意味し、ＤＲは次式で表される。
ＤＲ＝ＭＡＸ−ＭＩＮ＋１
ｎはビット割当を意味し、例えば１ビットＡＤＲＣの場合、ｎ＝１とされる。
【００７１】
以上のようにして、５個のＳＤ画素は、それぞれ１ビットの再量子化コードＱで表され、合計５ビットのＳＤ画素とされる。
【００７２】
ＡＤＲＣエンコーダ１４０より出力された５ビットの空間クラスのデータは、アドレス縮退回路１４１に入力され、４ビットのデータに縮退される。図１７は、アドレス縮退回路１４１の構成例を表している。
【００７３】
図１７に示すように、ＳＤ画素ｋ１乃至ｋ５に対応するＡＤＲＣエンコーダ１４０の５ビットの出力をＡＤＲＣ０乃至ＡＤＲＣ４とする。ＡＤＲＣ０は、マルチプレクサ１５５乃至１５８に、その切換信号として供給される。マルチプレクサ１５５には、ＡＤＲＣ１が、直接またはインバータ１５１により反転されて、入力されている。マルチプレクサ１５６には、ＡＤＲＣ２が、直接またはインバータ１５２により反転されて、入力されている。マルチプレクサ１５７には、ＡＤＲＣ３が、直接またはインバータ１５３により反転されて、入力されている。マルチプレクサ１５８には、ＡＤＲＣ４が、直接またはインバータ１５４により反転されて、入力されている。
【００７４】
各マルチプレクサ１５５乃至１５８は、ＡＤＲＣ０が０であるとき、それぞれＡＤＲＣ１乃至ＡＤＲＣ４を選択して、４ビットのデータＳＰ０乃至ＳＰ３として出力する。これに対して、ＡＤＲＣ０が１であるとき、マルチプレクサ１５５乃至１５８は、それぞれ対応するインバータ１５１乃至１５４の出力を選択して、ＳＰ０乃至ＳＰ３として出力する。
【００７５】
このようにして、５ビットの空間クラスは４ビットに変換されて、クラス縮退回路１４２に出力される。これにより、例えば”０１１１１”のデータは、”１１１１”とされ、”１００００”のデータも”１１１１”とされ、共通のクラスとされる。
【００７６】
クラス縮退回路１４２にはまた、動き判定部３４のエンコーダ１２８より出力した、２ビットの動きクラスが供給されている。すなわち、クラス縮退回路１４２には、合計６ビットのクラスコードが入力される。
【００７７】
クラス縮退回路１４２は、この６ビットのクラスコードを５ビットに縮退し、エンコーダ１４３に出力している。エンコーダ１４３は、入力された５ビットのクラスコードをエンコードして出力するようになされている。
【００７８】
クラス縮退回路１４２は、例えば、図１８に示すように構成されている。図１８の例においては、動き判定部３４より出力された２ビットの動きクラスＭＶのＭＳＢとしてのＭＶ１と、ＬＳＢとしてのＭＢ０が、オア回路１６１に供給されている。オア回路１６１の出力は、加算器１６２の一方の入力のＭＳＢ端子に入力されている。動きクラスのＭＳＢとしてのＭＶ１は、加算器１６２の一方の入力のＭＳＢから２ビット目に入力されている。加算器１６２の一方の入力の下位３ビットは、接地され０とされている。
【００７９】
ＡＤＲＣエンコーダ１４０より出力された５ビットの空間クラスのデータであって、アドレス縮退回路１４１により４ビットに縮退されたデータＳＰ３乃至ＳＰ０のうち、ＭＳＢのＳＰ３は、シフタ１６３のＭＳＢから２番目の端子に、ＳＰ２はＭＳＢから２番目の端子に、ＳＰ１はＭＳＢから３番目の端子に、そして、ＳＰ０はＬＳＢの端子に、それぞれ入力されている。シフタ１６３のＭＳＢの端子は接地され、０とされている。
【００８０】
シフタ１６３は、動きクラスに対応して動作し、動きクラスが０である場合、入力された下位４ビットのデータを、そのまま加算器１６２の他方の入力の下位４ビットに入力させる。これに対して、動きクラスが０ではない場合（１または２である場合）、シフタ１６３は、下位４ビットのデータをＬＳＢ側に１ビットずつシフトさせる。すなわち、入力されたデータを、実質的に１／２の値とする。そして、ビットシフトした後のデータを、加算器１６２の他方の入力の下位４ビットに供給する。加算器１６２の他方の入力のＭＳＢは、接地され、常に０とされている。
【００８１】
加算器１６２は、一方の入力から供給された５ビットのデータと、他方の入力から供給された５ビットのデータとを加算し、加算結果をレジスタ１６４に出力し、保持させるようになされている。なお、この例における加算器１６２は、実質的に、図１６におけるエンコーダ１４３を構成している。
【００８２】
また、クラス分類部３３には、減算器１４４に、図１３に示す大エリアの最大値と最小値が、最大値最小値演算部３２から供給されている。減算器１４４は、入力された最大値から最小値を減算し、比較器１４５に出力している。減算器１４６には、図１２に示した小エリアの最大値と最小値が、最大値最小値演算部３２より入力されている。減算器１４６は、入力された最大値から最小値を減算し、その減算結果を乗算器１４７に出力している。レジスタ１４８には、初期状態において、予め所定の設定値が保持されている。乗算器１４７は、減算器１４６より入力された値に、レジスタ１４８に保持されている係数を乗算し、その乗算器結果を比較器１４５に出力している。比較器１４５は、減算器１４４の出力と乗算器１４７の出力の大きさを比較し、減算器１４４の出力の方が大きい場合、短タップ選択信号を出力し、減算器１４４の出力が乗算器１４７の出力より小さいとき、長タップ選択信号を出力するようになされている。
【００８３】
次に、その動作について説明する。ＡＤＲＣエンコーダ１４０は、入力された５画素のＳＤデータｋ１乃至ｋ５のそれぞれについて、上記した式に従って、再量子化コードＱを演算し、空間クラスを表すデータとして、５ビットのデータＡＤＲＣ０乃至ＡＤＲＣ４を出力する。この５ビットのデータは、アドレス縮退回路１４１により、４ビットのデータＳＰ３乃至ＳＰ０に縮退され、クラス縮退回路１４２のシフタ１６３に供給される。上述したように、クラス縮退回路１４２にはまた、動き判定部３４より動きクラスＭＶ１とＭＶ０が供給されている。
【００８４】
例えば、いま、上位２ビット（ＭＶ１，ＭＶ０）の動きクラスと、下位４ビット（ＳＰ３，ＳＰ２，ＳＰ１，ＳＰ０）の空間クラスよりなる６ビットによりクラスコードが構成されているものとすると、クラスコードが”０１００１１”である場合、オア回路１６１は、”１”を加算器１６２の一方の入力のＭＳＢに出力し、その次のビットには、動きクラスのＭＳＢである”０”が入力される。加算器１６２の一方の入力の下位３ビットは常に０とされているため、結局、加算器１６２の一方の入力には”１００００”が入力されることになる。
【００８５】
一方、いまクラスは１であり、０ではないから、シフタ１６３は、端子ＳＰ３乃至ＳＰ０に入力された”００１１”をＬＳＢ側に１ビットずつシフトして、”０００１”とする。これが、加算器１６２の他方の入力の下位４ビットに入力され、そのＭＳＢは常に０とされているため、結局、加算器１６２の他方の入力には”００００１”が供給されることになる。その結果、加算器１６２の出力は、”１０００１”となり、これがレジスタ１６４に出力され、保持される。これにより、クラスコードが１９（＝０１００１１）から、１７（＝１０００１）へ縮退される。
【００８６】
同様に、クラスコードが”１００１０１”である場合、加算器１６２の一方の入力には”１１０００”が入力され、他方の入力には”０００１０”が入力される。その結果、加算器１６２の出力は”１１０１０”となり、クラスコードが３７（＝１００１０１）から、２６（＝１１０１０）に縮退される。
【００８７】
図１９は、このようにして、クラスが縮退される様子を表している。同図に示すように、動きクラスが０，１または２である場合における縮退前のクラスが、それぞれ０乃至１５、１６乃至３１、または３２乃至４７であるとすると、合計４８個のクラスを表すために、６ビットの符号が必要となる。これに対して、クラス縮退回路１４２により、クラス縮退処理を行うことにより、動きクラスが０である場合の縮退後のクラスは０乃至１５とするが、動きクラス１である場合におけるクラスを１６乃至２３とし、動きクラスが２である場合におけるクラスを２４乃至３１とし、縮退前の１／２とすることにより、クラスの合計数は３２個となり、５ビットで表すことが可能となる。従って、後述する係数ＲＡＭ部４０において記憶しておく係数の数がそれだけ少なくなり、係数ＲＡＭ部４０の容量をそれだけ小さくすることが可能となる。
【００８８】
一方、減算器１４４は、大エリアの最大値から最小値を減算し、比較器１４５に出力している。減算器１４６は、小エリアの最大値から最小値を減算し、乗算器１４７に出力している。乗算器１４７は、減算器１４６の出力に、レジスタ１４８に保持されている係数を乗算し、比較器１４５に出力する。レジスタ１４８に設定する値は、図１２に示す小エリアの５個のＳＤ画素の最大値と最小値の差が、図１３に示す大エリアの１３個のＳＤ画素の最大値と最小値の差に対応する値になるように調整するものである。そして、比較器１４５において、減算器１４４の出力と、乗算器１４７の出力の大きさを比較し、急峻な変化の有無を判定する。
【００８９】
減算器１４４の出力の方が乗算器１４７の出力より小さいとき（急峻な変化がないとき）、比較器１４５は、長タップ選択信号を出力し、減算器１４４の出力の方が乗算器１４７の出力より大きいとき（急峻な変化があるとき）、比較器１４５は、短タップ選択信号を出力する。これにより、急峻な変化がある場合においては、予測範囲を狭くして、リンギング成分の発生を抑制するようにする。
【００９０】
詳細は後述するが、長タップ選択信号が出力された場合、後述するタップ縮退部３５，３６において、図４に示す所定のフィールドに存在するＳＤ画素ｘ１，ｘ２，ｘ４乃至ｘ６，ｘ１０乃至ｘ１６，ｘ２０乃至ｘ２２，ｘ２４の１７個（１７タップ）のＳＤ画素をタップ縮退して、７画素（７タップ）のデータを生成し、この７タップに対して、係数を積和演算することで、ＨＤ画素を演算する。これに対して、短タップが選択された場合においては、図２０に示すように、ＳＤ画素データｘ２，ｘ５，ｘ１２乃至ｘ１４，ｘ２１，ｘ２４の実在する７個のＳＤ画素（７タップ）に対して係数を積和演算することにより、ＨＤ画素を求めるようにする。いずれの場合も、最終的に係数が演算されるタップ数は７個とされているので、積和演算のための回路としての積和部３８，３９は、共通化することができる。
【００９１】
コントロールＲＯＭ部３７は、クラス分類部３３より出力されたクラスコードと、長タップまたは短タップ選択信号に対応して、タップ縮退部３５，３６を制御するようになされている。すなわち、長タップ選択信号が入力された場合には、コントロールＲＯＭ部３７は、タップ縮退部３５，３６を制御し、ディレイレジスタ部３１より、図４に示した現在のフィールドの１７タップのＳＤ画素ｘ１，ｘ２，ｘ４乃至ｘ６，ｘ１０乃至ｘ１６，ｘ２０乃至ｘ２２，ｘ２４，ｘ２５を取り込ませる。これに対して、短タップ選択信号が入力された場合においては、コントロールＲＯＭ部３７は、タップ縮退部３５，３６に対して、ディレイレジスタ部３１から、図２０に示す現在のフィールドの７個のＳＤ画素ｘ２，ｘ５，ｘ１２乃至ｘ１４，ｘ２１，ｘ２４を、タップ縮退部３５，３６に取り込ませる。
【００９２】
タップ縮退部３５，３６は、図４に示す１７個のＳＤ画素を取り込んだとき、これを７個の画素に縮退する処理を行って、対応する積和部３８，３９に出力する。１７個の画素を７個の画素に縮退する回路は、膨大な構成となるので、これを図示するのが困難である。そこで、ここでは、７個の画素を取り込んで、３個の画素に縮退する場合のタップ縮退部の構成例について、図２１を参照して説明する。
【００９３】
図２１はモード１のタップ縮退部３５の構成例を示している。図２１に示すように、マルチプレクサ１８１−１の入力には、図２２に示す７個のＳＤ画素のうち、ＳＤ画素ｘ２が、その２つの入力端子のそれぞれに供給される。マルチプレクサ１８１−２には、２つの入力のいずれにもＳＤ画素ｘ５が供給される。マルチプレクサ１８１−３の左側の入力には、ＳＤ画素ｘ１２が供給され、右側の入力には、ＳＤ画素ｘ１４が供給される。マルチプレクサ１８１−４には、２つの入力のいずれにもＳＤ画素ｘ１３が供給されている。マルチプレクサ１８１−５の左側の入力には、ＳＤ画素ｘ１４が供給され、右側の入力には、ＳＤ画素ｘ１２が供給されている。マルチプレクサ１８１−６には、その２つの入力のいずれにもＳＤ画素ｘ２１が供給され、マルチプレクサ１８１−７には、２つの入力のいずれにもＳＤ画素ｘ２４が供給されている。
【００９４】
すなわち、図２２に示すように、垂直な線に対して左右対称に対応する画素が存在する画素は、対応するマルチプレクサの一方の入力と他方の入力に供給されている。そして、一方のマルチプレクサと他方のマルチプレクサの入力の配置が対称となるようになされている。すなわち、図２１に示すように、マルチプレクサ１８１−３においては、その左側の入力にＳＤ画素ｘ１２が供給され、右側の入力にＳＤ画素ｘ１４が供給されているのに対して、マルチプレクサ１８１−５においては、その左側の入力にＳＤ画素ｘ１４が供給され、右側の入力にＳＤ画素ｘ１２が供給されている。
【００９５】
そして、線対称として対応する画素が存在しない画素に対応するマルチプレクサの２つの入力のそれぞれには、同一の画素が供給されている。
【００９６】
各マルチプレクサ１８１−１乃至１８１−７は、例えば、コントロールＲＯＭ部３７から論理０のコントロール信号が入力されたとき、左右の入力のうちの左側の入力を選択、出力し、論理１が入力されたとき、右側の入力を選択、出力する。従って、レジスタ１８２−１乃至１８２−７には、論理０のコントロール信号が、マルチプレクサ１８１−１乃至１８１−７に入力されたとき、ＳＤ画素ｘ２，ｘ５，ｘ１２，ｘ１３，ｘ１４，ｘ２１またはｘ２４が、それぞれ保持される。これに対して、論理１のコントロール信号が、マルチプレクサ１８１−１乃至１８１−７に入力された場合においては、ＳＤ画素ｘ２，ｘ５，ｘ１４，ｘ１３，ｘ１２，ｘ２１またはｘ２４が保持される。
【００９７】
なお、マルチプレクサ１８１−１乃至１８１−７の制御に対して、レジスタ１８２−１乃至１８２−７以降の制御は、倍速で行われるようになされている。
【００９８】
図２０を参照して説明したように、ＳＤ画素ｘ１３の左上のＨＤ画素ｙ１を生成する場合、マルチプレクサ１８１−１乃至１８１−７に例えば論理０が入力され、右上のＨＤ画素ｙ２を生成する場合、論理１が入力される。
【００９９】
レジスタ１８２−１に保持された画素データは、レジスタ１８６−１，１８８−１，１９０−１を介して、そのまま出力される。
【０１００】
レジスタ１８２−２に保持されたＳＤ画素は、マルチプレクサ１８３−１の右側の入力と、マルチプレクサ１８３−３の左側の入力に供給される。レジスタ１８２−３の出力は、マルチプレクサ１８３−１の左側の入力と、マルチプレクサ１８３−４の右側の入力に供給される。レジスタ１８２−４の出力は、マルチプレクサ１８３−２の一方の入力に供給されるとともに、マルチプレクサ１８３−５の右側の入力に供給される。レジスタ１８２−５の出力は、マルチプレクサ１８３−４の左側の入力に供給される。レジスタ１８２−６の出力は、マルチプレクサ１８３−３の右側の入力に供給される。レジスタ１８２−７の出力は、マルチプレクサ１８３−５の左側の入力に供給される。
【０１０１】
マルチプレクサ１８３−１乃至１８３−５は、コントロールＲＯＭ部３７より供給されるコントロールコードに対応して、左側の入力または右側の入力の一方を選択し、後段の回路に出力する。マルチプレクサ１８３−１は、選択したＳＤ画素データを２の補数回路１８４−１に供給する。２の補数回路１８４−１は、コントロールＲＯＭ部３７からのコントロール信号に対応して、マルチプレクサ１８３−１より入力されたデータを、そのままレジスタ１８６−２に出力するか、または２の補数の演算を行って、演算結果をレジスタ１８６−２に出力する。２の補数演算は、ＳＤデータのビットの１を０に反転し、０を１に反転し、さらに、ＬＳＢに１を付加（加算）することにより行われる。
【０１０２】
マルチプレクサ１８３−２は、コントロールＲＯＭ部３７からのコントロールコードに対応して、レジスタ１８２−４からのデータ、または０を選択し、レジスタ１８６−３に出力する。加算器１８７−１は、レジスタ１８６−２の出力と、レジスタ１８６−３の出力とを加算し、レジスタ１８８−２、レジスタ１９０−２を介して出力する。
【０１０３】
マルチプレクサ１８３−３は、レジスタ１８２−２の出力、またはレジスタ１８２−６の出力の一方をコントロールＲＯＭ部３７のコントロールコードに対応して選択し、２の補数回路１８４−２に供給する。２の補数回路１８４−２は、２の補数回路１８４−１における場合と同様に、コントロールＲＯＭ部３７からのコントロールコードに対応して、マルチプレクサ１８３−３より供給された画素データを、そのまま、または、２の補数演算を行って、レジスタ１８６−４に出力する。
【０１０４】
マルチプレクサ１８３−４は、レジスタ１８２−５の出力、またはレジスタ１８２−３の出力をコントロールＲＯＭ部３７からのコントロールコードに対応して選択し、選択した画素データを２の補数回路１８５に出力する。２の補数回路１８５は、マルチプレクサ１８３−４から入力された画素データに対して２の補数演算を行い、演算結果をレジスタ１８６−５に出力する。加算器１８７−２は、レジスタ１８６−４の出力と、レジスタ１８６−５の出力とを加算し、レジスタ１８８−３に出力する。
【０１０５】
マルチプレクサ１８３−５は、レジスタ１８２−７の出力と、レジスタ１８２−４の出力の一方を、コントロールＲＯＭ部３７のコントロールコードに対応して選択し、２の補数回路１８４−３に出力する。２の補数回路１８４−３は、コントロールＲＯＭ部３７からのコントロールコードに対応して、入力された画素データを、そのままレジスタ１８６−６に出力するか、または２の補数演算を行ってレジスタ１８６−６に出力する。レジスタ１８６−６の出力は、さらにレジスタ１８８−４に供給される。
【０１０６】
加算器１８９は、レジスタ１８８−３の出力と、レジスタ１８８−４の出力とを加算し、加算結果をレジスタ１９０−３に出力する。
【０１０７】
以上のようにして、図２２に示す７タップのデータが、３タップのデータに変換される。
【０１０８】
近傍の画像データは、自己相関性が強いため、中心のＳＤ画素データに対して、左右対称であることが多い。そこで、タップ縮退部３５において、水平方向に鏡像関係にあるＨＤ画素ｙ１を求める場合と、ＨＤ画素ｙ２を求める場合とで、鏡像関係にあるＳＤ画素を入れ換えるだけで、実質的に同一の回路で、ＨＤ画素ｙ１とＨＤ画素ｙ２のいずれをも求めることができる。
【０１０９】
同様に、タップ縮退部３６において、水平方向に鏡像関係にあるＨＤ画素ｙ３と、ＨＤ画素ｙ４を生成する場合においても、同様のタップ縮退処理を行うことができる。
【０１１０】
なお、タップ縮退部３５，３６において、１７タップを取り込んで、７タップを出力する場合には、鏡像関係は、図２３に示すようになる。すなわち、ＳＤ画素ｘ４とｘ６が鏡像関係となる。同様に、ＳＤ画素ｘ１０とｘ１６、ｘ１１とｘ１５、ｘ１２とｘ１４、ｘ２０とＸ２２が、それぞれ鏡像関係となる。
【０１１１】
図２１における鏡像関係にない画素データが入力されているマルチプレクサ１８１−１，１８１−２，１８１−４，１８１−６，１８１−７は、実質的には、常に同一の画素データを選択出力するので、省略することも可能である。
【０１１２】
以上のようにして、長タップモードにおいては、タップ縮退部３５，３６で、１７タップから縮退された７タップのデータが、それぞれモード１とモード２の積和部３８，３９に入力される。短タップモード時においては、タップ縮退部３５，３６で取り込まれた７タップのデータが、そのまま積和部３８，３９に入力される。
【０１１３】
図２４は、係数ＲＡＭ部４０の構成例を表している。この例は、３タップ分の係数を記憶する場合を示しているが、図６の係数ＲＡＭ部４０においては、上述したように７タップ分の係数が記憶される。
【０１１４】
初期化モード時、デコーダ２０２は、ＳＲＡＭ（Static Random Access Memory）２０５−１乃至２０５−３を書き込み状態にする。初期化カウンタ２０１は、クロックを計数し、そのカウント値を出力する。デコーダ２０２は、初期化モード時、マルチプレクサ２０３を制御し、初期化カウンタ２０１の出力を選択させる。その結果、初期化カウンタ２０１のカウント値がマルチプレクサ２０３からレジスタ２０４に供給され、保持される。そして、レジスタ２０４に保持されたカウント値が、ＳＲＡＭ２０５−１乃至２０５−３に書き込みアドレスとして供給される。また、このとき、初期化回路１０より供給される係数データが、ＳＲＡＭ２０５−１乃至２０５−３に供給される。その結果、ＳＲＡＭ２０５−１乃至２０５−３には、初期化回路１０より供給された係数が、初期化カウンタ２０１で指定したアドレスに書き込まれる。
【０１１５】
このようにして、ＳＲＡＭ２０５−１乃至２０５−３に必要な係数がすべて書き込まれたとき、初期化カウンタ２０１は、初期化回路１０より供給されるリセット信号に対応してリセットされ、デコーダ２０２は、初期化カウンタ２０１がリセットされたとき、ＳＲＡＭ２０５−１乃至２０５−３を読み出しモードに設定するとともに、マルチプレクサ２０３を制御し、クラス分類部３３のエンコーダ１４３の出力するクラスコードを選択させ、レジスタ２０４に供給させる。その結果、レジスタ２０４に保持されたクラスコードが読み出しアドレスとして、ＳＲＡＭ２０５−１乃至２０５−３に供給される。従って、ＳＲＡＭ２０５−１乃至２０５−３から、クラスコードに対応する係数が読み出され、レジスタ２０６−１乃至２０６−３を介して出力される。このようにして読み出された係数は、積和部３８，３９に供給される。
【０１１６】
ここで、係数ＲＡＭ部４０に記憶されるクラス毎の係数は、例えば、日本出願公開特許公報平９−５１５１０（１９９７年２月１８日公開）に記載されている学習方法を用いて算出することができる。すなわち、既に知られているＨＤ信号を学習データとして利用して学習を行うことで、クラス毎の係数を算出することができる。具体的には、学習データとしてのＨＤ信号を間引いて、学習用のＳＤ信号を生成する。さらに、学習データとしてのＨＤ信号を構成するあるＨＤ画素を注目ＨＤ画素とし、その注目ＨＤ画素を、その周辺に位置する、学習用のＳＤ信号を構成する幾つかのＳＤ画素と所定の係数とを用いた線形一次結合モデルによって表す。このとき用いた係数を各クラス毎に最小自乗法を用いて求める。このように、既知のＨＤ信号を学習データとして利用して係数を得る際には、１つのＨＤ信号（１画面のＨＤ画像）だけではなく、複数のＨＤ信号を用いることにより、より正確な係数を得ることができる。なお、詳細については、上記出願を参照することとして、ここでは省略する。
【０１１７】
図２５は、積和部３８の構成例を表している。上述したように、積和部３８（積和部３９も同様）は、タップ縮退部３５より供給される７タップのデータに対して、係数ＲＡＭ部４０より供給される７個の係数を乗算して、１つのＨＤ画素データを演算により求めるのであるが、説明の便宜上、図２５に４タップの積和演算を行う場合の構成例を示す。
【０１１８】
図２５においては、タップ縮退部３５より供給された４タップの画素データが、それぞれレジスタ２１１−１乃至２１１−４に保持される。また、係数ＲＡＭ部４０より供給された係数データが、レジスタ２１２−１乃至２１２−４に保持される。乗算器２１３−１は、レジスタ２１１−１に保持された画素データと、レジスタ２１２−１に保持された係数データとを乗算し、レジスタ２１４−１に出力する。乗算器２１３−２は、レジスタ２１２に保持された画素データと、レジスタ２１２−２に保持された係数データとを乗算し、乗算結果をレジスタ２１４−２に出力する。
【０１１９】
加算器２１５−１は、レジスタ２１４−１に保持された値と、レジスタ２１４−２に保持された値とを加算し、加算結果をレジスタ２１６−１に出力する。
【０１２０】
同様に、レジスタ２１１−３に保持された画素データと、レジスタ２１２−３に保持された係数データが、乗算器２１３−３により乗算され、レジスタ２１４−３に保持される。また、レジスタ２１１−４に保持された画素データと、レジスタ２１２−４に保持された係数データとが、乗算器２１３−４により乗算され、レジスタ２１４−４に保持される。
【０１２１】
加算器２１５−２は、レジスタ２１４−３に保持された値と、レジスタ２１４−４に保持された値とを加算し、レジスタ２１６−２に出力し、保持させる。
【０１２２】
加算器２１７は、レジスタ２１６−１に保持された値と、レジスタ２１６−２に保持された値とを加算し、レジスタ２１８を介して出力する。
【０１２３】
すなわち、この回路により、レジスタ２１１−１乃至２１１−４に保持される画素データを、便宜上、ｘ１乃至ｘ４とし、レジスタ２１２−１乃至２１２−４に保持される係数を、ｗ１乃至ｗ４とすると、レジスタ２１８には、次式で示す演算結果がＨＤ画素データとして保持される。
ＨＤ＝ｘ１×ｗ１＋ｘ２×ｗ２＋ｘ３×ｗ３＋ｘ４×ｗ４
【０１２４】
以上のようにして、ＨＤ画素ｙ１，ｙ２が演算され、走査線変換回路１１に出力される。
【０１２５】
同様にして、積和部３９において、タップ縮退部３６より供給された画素データと、係数ＲＡＭ部４０より供給された係数データとが積和演算されて、ＨＤ画素ｙ３，ｙ４が演算され、走査線変換回路１１に出力される。
【０１２６】
以上のようにして、輝度信号成分について、ＳＤ画素からＨＤ画素が生成される。同様の構成により、色信号成分についても、ＳＤ画素からＨＤ画素を演算し、生成するようにすることも可能であるが、そのようにすると、色信号成分用の係数ＲＡＭ部を設ける必要が生じ、解像度創造装置９が大型化し、高価となる。そこで、この実施の形態においては、色信号成分は、輝度信号成分とは異なる構成で処理されるようになされている。
【０１２７】
すなわち、図６に示すように、走査線変換回路８より入力された３ライン分の色信号成分の画素データは、ディレイレジスタ部４１に入力され、保持される。このディレイレジスタ部４１の構成は、輝度信号成分を保持するディレイレジスタ部３１と、ライン数が異なる点を除き、基本的に同様の構成とされている。ディレイレジスタ部４１には、注目画素のラインの色信号成分の画素データと、同一フィールドのその上下のラインの色信号成分の画素データの、合計３ライン分の画素データが保持されることになる。
【０１２８】
ディレイレジスタ部４１に保持された画素データは、補間画素演算部４２に入力され、補間処理が行われる。
【０１２９】
図２６は、モード１において、ＨＤ画素ｙ１，ｙ２を生成する場合における図６の補間画素演算部４２の構成例を表している。この補間画素演算部４２には、図２７に示すように、ＨＤ画素（の色信号成分）ｙ_C１，ｙ_C２の上側のラインのＳＤ画素データ（端子Ｕ１乃至Ｕ５のＳＤ画素データ）（色信号成分）と下側のラインのＳＤ画素（端子Ｊ１乃至Ｊ５のＳＤ画素データ）が入力されるようになされている。端子Ｕ１の８ビットのＳＤ画素データは、シフタ２３１によりＬＳＢ側に３ビット分シフトされ、５ビットのＳＤ画素データとして、マルチプレクサ２３３に入力されている。また、端子Ｕ３の８ビットのＳＤ画素データは、シフタ２３２により、ＬＳＢ側に３ビット分シフトされ、５ビットのＳＤ画素データとして、マルチプレクサ２３３に入力されている。マルチプレクサ２３３は、シフタ２３１またはシフタ２３２により入力されたＳＤ画素データのうち一方を、選択信号に対応して選択するようになされている。マルチプレクサ２３３の出力は、レジスタ２３４と２３５を介して、加算器２３６に供給されている。
【０１３０】
シフタ２３７は、端子Ｕ３から入力される８ビットのデータをＬＳＢ側に３ビット分シフトして、５ビットのデータとして加算器２３６に供給している。加算器２３６は、レジスタ２３５とシフタ２３７より供給された、それぞれ５ビットのデータを加算し、６ビットのデータとして、レジスタ２３８を介して加算器２３９に供給している。
【０１３１】
シフタ２４０は、端子Ｊ２の８ビットのＳＤ画素データを、２ビット分だけＬＳＢ側にシフトして、６ビットのデータとして、マルチプレクサ２４２に供給している。シフタ２４１は、端子Ｊ４の８ビットのＳＤ画素データを２ビット分だけＬＳＢ側にシフトして、６ビットのデータとしてマルチプレクサ２４２に供給している。マルチプレクサ２４２は、選択信号に対応して、２つの入力のうちの一方を選択し、レジスタ２４３を介して加算器２３９に供給している。
【０１３２】
加算器２３９は、レジスタ２３８の出力と、レジスタ２４３の出力を加算し、７ビットのデータをレジスタ２４４を介して加算器２４５に供給している。
【０１３３】
シフタ２４６は、端子Ｊ４より供給される８ビットのデータを１ビット分だけＬＳＢ側にシフトして、７ビットのデータとして加算器２４５に供給している。加算器２４５は、レジスタ２４４の出力と、シフタ２４６との出力とを加算し、８ビットのデータをレジスタ２４７を介して出力するようになされている。
【０１３４】
なお、図２６における、シフタ２３１，２３２，２３７，２４０，２４１，２４６は、実質的にはＭＳＢ側から所定のビットだけを後段に配線することで実現することができる。
【０１３５】
図２７に示すように、モード１において生成されるＨＤ画素ｙ_C１，ｙ_C２と、端子Ｊ３の注目ＳＤ画素との距離をａ１、ＨＤ画素ｙ_C１，ｙ_C２と端子Ｕ３のＳＤ画素との距離をｂ１、ＨＤ画素ｙ_C１，ｙ_C２と端子Ｕ４，Ｕ２のＳＤ画素との距離をｃ１、さらにＨＤ画素ｙ_C１，ｙ_C２と端子Ｊ４，Ｊ２のＳＤ画素との距離をｄ１とするとき、それらの逆数の比は次のようになる。
１／ａ１：１／ｂ１：１／ｃ１：１／ｄ１＝１／２：１／８：１／８：１／４
【０１３６】
同様に、モード２において生成されるＨＤ画素ｙ_C３，ｙ_C４から端子Ｊ３のＳＤ画素までの距離をａ２、端子Ｋ３のＳＤ画素までの距離をｂ２、端子Ｋ４，Ｋ２までの距離をｃ２、端子Ｊ４，Ｊ２のＳＤ画素までの距離をｄ２とするとき、その距離の逆数の比は次のようになる。
１／ａ２：１／ｂ２：１／ｃ２：１／ｄ２＝
３／８：３／１６：３／１６：１／４
【０１３７】
次に、図２８のタイミングチャートを参照して、その動作について説明する。いま、図２７に示すように、端子Ｕ１乃至Ｕ５にＳＤ画素Ａ’乃至Ｉ’が順次入力され、端子Ｊ１乃至Ｊ５にＳＤ画素Ａ乃至Ｉが、順次供給されるものとすると、図２８に示すように、各端子Ｕ１乃至Ｕ５、または各端子Ｊ１乃至Ｊ５の画素データは、隣の端子より、１クロック分ずつ、順次遅れることになる。
【０１３８】
マルチプレクサ２３３は、画素データのシフトの周期に対して、１／２の周期で、２つの入力のうちの一方の入力を交互に選択する。従って、図２８に示すように、レジスタ２３４は、所定のタイミングにおいて、シフタ２３１より供給されるＳＤ画素Ｅ’を保持したとすると、次のタイミングにおいては、シフタ２３２より供給されるＳＤ画素Ｃ’を保持する。レジスタ２３４に保持されたＳＤ画素Ｅ’，Ｃ’は、後段のレジスタ２３５に順次転送される。
【０１３９】
レジスタ２３５にＳＤ画素Ｅ’が保持され、加算器２３６の一方の入力に供給されたとき、加算器２３６の他方の入力には、シフタ２３７からＳＤ画素Ｄ’が供給される。加算器２３６は、２つの入力を加算し、レジスタ２３８に出力するので、レジスタ２３８には、データＥ’＋Ｄ’が保持される。そして、次のタイミングにおいては、加算器２３６は、レジスタ２３５に保持されているＳＤ画素Ｃ’と、シフタ２３７より供給されるＳＤ画素Ｄ’とを加算するので、レジスタ２３８にはデータＣ’＋Ｄ’が保持される。
【０１４０】
同様に、データ転送周期の１／２の周期で、２つの入力のうちの一方を交互に選択し、出力するマルチプレクサ２４２は、レジスタ２３８がデータＣ’＋Ｄ’を保持しているタイミングのとき、シフタ２４０より供給されるＳＤ画素Ｅを選択し、レジスタ２４３に保持させ、レジスタ２３８にデータＣ’＋Ｄ’が保持されているタイミングにおいては、ＳＤ画素Ｃをレジスタ２４３に保持させる。
【０１４１】
加算器２３９は、レジスタ２３８とレジスタ２４３に保持されているデータを加算し、レジスタ２４４に出力するので、レジスタ２４４は、レジスタ２３８にデータＥ’＋Ｄ’が保持され、レジスタ２４３にデータＥが保持されている状態の次のタイミングにおいては、この２つのデータを加算したデータＥ’＋Ｄ＋Ｅを保持する。そして、レジスタ２４４は、さらに次のタイミングにおいては、データＣ’＋Ｄ’＋Ｃを保持する。
【０１４２】
レジスタ２４４にデータＥ’＋Ｄ＋Ｅが保持されたタイミングにおいて、シフタ２４６は、データＤを出力する。従って、加算器２４５により、レジスタ２４４に保持されたデータＥ’＋Ｄ＋Ｅと、シフタ２４６より出力されたデータＤとが加算され、レジスタ２４７にデータＥ’＋Ｄ’＋Ｅ＋Ｄが保持される。同様に、次のタイミングにおいては、レジスタ２４４にデータＣ’＋Ｄ’＋Ｃが保持され、シフタ２４６よりデータＤが供給されるので、レジスタ２４７には、データＣ’＋Ｄ’＋Ｃ＋Ｄが保持される。
【０１４３】
図２７を参照して説明したように、データＥ’，Ｃ’，Ｄ’，Ｅ，Ｃ，Ｄは、それぞれ各端子の画素データに対し、次の関係を有している。
Ｅ’＝（１／８）Ｕ２
Ｃ’＝（１／８）Ｕ４
Ｄ’＝（１／８）Ｕ３
Ｅ＝（１／４）Ｊ２
Ｃ＝（１／４）Ｊ４
Ｄ＝（１／２）Ｊ３
【０１４４】
従って、データＥ’＋Ｄ’＋Ｅ＋Ｄは、次式で表されるＨＤ画素ｙ_C２を表している。
ｙ_C２＝（１／８）Ｕ２＋（１／８）Ｕ３＋（１／４）Ｊ２＋（１／２）Ｊ３
【０１４５】
また、データＣ’＋Ｄ’＋Ｃ＋Ｄは、次式で表されるＨＤ画素ｙ_C１を表すことになる。
ｙ_C１＝（１／８）Ｕ４＋（１／８）Ｕ３＋（１／４）Ｊ４＋（１／２）Ｊ３
【０１４６】
以上においては、モード１においてＨＤ画素ｙ_C１，ｙ_C２を求める場合を説明したが、モード２においてＨＤ画素ｙ_C３，ｙ_C４を求める場合も、上述した式に従って、通常の補間処理により演算が行われる。
【０１４７】
以上においては、ＮＴＳＣ方式のＳＤ信号を、ハイビジョンのＨＤ信号に変換する場合を例として説明したが、本発明は、このような方式に限定されるものではない。要は、低品位の画素データから高品位の画素データを生成する場合に応用することが可能である。
【０１４８】
【発明の効果】
以上の如く、本発明の信号変換装置および信号変換方法によれば、輝度信号成分については、例えば、学習などによって得られた、クラスに対応する第１の係数を用いて演算を行うようにし、色信号成分については、第１および第２のディジタル画像信号の画素どうしの位置関係に基づいて得られる第２の係数を用いて演算を行うようにしたので、係数記憶のための容量を小さくし、小型化、低コスト化を図ることが可能となる。
【図面の簡単な説明】
【図１】本発明の信号変換装置の構成例を示すブロック図である。
【図２】図１の走査線変換回路８の順方向の動作を説明する図である。
【図３】図１の走査線変換回路８の逆方向の動作を説明する図である。
【図４】図１の解像度創造装置９の処理を説明する図である。
【図５】ＳＤ画素とＨＤ画素の位置関係を説明する図である。
【図６】図１の解像度創造装置９の構成例を示すブロック図である。
【図７】図６のディレイレジスタ部３１の構成例を示すブロック図である。
【図８】図６の最大値最小値演算部３２の構成例を示すブロック図である。
【図９】図８の比較大選択回路６１の構成例を示すブロック図である。
【図１０】図８の比較小選択回路６５の構成例を示すブロック図である。
【図１１】空間クラスの画素の範囲を説明する図である。
【図１２】小エリアの画素を説明する図である。
【図１３】大エリアの画素を説明する図である。
【図１４】図６の動き判定部３４の構成例を示すブロック図である。
【図１５】図１４の絶対値演算回路１０１の処理を説明する図である。
【図１６】図６のクラス分類部３３の構成例を示すブロック図である。
【図１７】図１６のアドレス縮退回路１４１の構成例を示すブロック図である。
【図１８】図１６のクラス縮退回路１４２の構成例を示すブロック図である。
【図１９】図１６のクラス縮退回路１４２の動作を説明する図である。
【図２０】短タップモードにおける画素の範囲を説明する図である。
【図２１】図６のタップ縮退部３５の構成例を示すブロック図である。
【図２２】７タップの画素の範囲を説明する図である。
【図２３】１７タップの画素の範囲を説明する図である。
【図２４】図６の係数ＲＡＭ部４０の構成例を示すブロック図である。
【図２５】図６の積和部３８の構成例を示すブロック図である。
【図２６】図６の補間画素演算部４２の構成例を示すブロック図である。
【図２７】図２６の補間画素演算部４２の動作を説明する図である。
【図２８】図２６の補間画素演算部の動作を説明するタイミングチャートである。
【符号の説明】
４，５ フィールドメモリ， ６ ラインメモリ， ８ 走査線変換回路， ９ 解像度創造装置， １０ 初期化回路， １１ 走査線変換回路， １２，１３ ＨＤフィールドメモリ， ３１ ディレイレジスタ部， ３２ 最大値最小値演算部， ３３ クラス分類部， ３４ 動き判定部， ３５，３６ タップ縮退部， ３７ コントロールＲＡＭ部， ３８，３９ 積和部， ４０ 係数ＲＡＭ部， ４１ ディレイレジスタ部， ４２ 補間画素演算部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal conversion apparatus and method, and more particularly, to a signal conversion apparatus and method that efficiently process luminance and color signal components to generate a higher-resolution image signal.
[0002]
[Prior art]
Standard television broadcasting in Japan is NTSC (National Television System Committee) system. On the other hand, recently, higher-definition television broadcasting systems represented by high-vision have been developed and are becoming popular. In the case of the NTSC system, the number of scanning lines is 525, and the aspect ratio is 4: 3. On the other hand, in the high vision system, the number of scanning lines is 1125 and the aspect ratio is 16: 9. Therefore, in the case of the high-definition method, it is possible to enjoy a higher resolution and realistic image.
[0003]
In order to display an NTSC image on such a high-definition television receiver, an SD (Standard Definition) signal corresponding to the NTSC video signal is replaced with an HD (High Definition) signal corresponding to a higher resolution video signal. ) Needs to be converted to a signal. In the following, a signal in a state before being converted into a larger number is appropriately referred to as an SD signal, SD data, or SD pixel, and a signal in a state after being converted is referred to as an HD signal, HD data, Or, it is called an HD pixel.
[0004]
Conventionally, the conversion processing of the SD signal into the HD signal has been performed by simple interpolation processing in the horizontal direction and the vertical direction.
[0005]
However, since this interpolation processing is performed by a cascade connection type FIR filter, the resolution of the HD signal is the same as that of the original SD signal. Rather, when a normal image is to be converted, the interpolation in the vertical direction is performed by intra-field processing, and inter-field correlation is not used. Therefore, in the still image portion, the resolution is degraded compared to the SD signal due to conversion loss. There was a drawback.
[0006]
Therefore, the applicant of the present invention, as Japanese Patent Application No. 6-205934, performs class division according to the three-dimensional (spatio-temporal) distribution of the image signal level that is the input signal, and the prediction obtained by learning in advance for each class. A method of calculating an optimum estimated value as an HD signal using a coefficient value was proposed.
[0007]
[Problems to be solved by the invention]
However, if both the luminance signal and the color signal are processed by the method as proposed above, a high-resolution image can be obtained, but the capacity of the ROM for storing the coefficients becomes large, and the apparatus only becomes large. In addition, there was a problem of high costs.
[0008]
The present invention has been made in view of such a situation, and is intended to achieve downsizing and cost reduction.
[0009]
[Means for Solving the Problems]
  The signal conversion apparatus according to claim 1 stores, for each predetermined class, a first coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal. Storage means, class classification means for classifying a class based on the luminance signal component of the first digital image signal, and spatial features of the first region in the first digital image signalchange ofAnd spatial features of the second region that are larger than the first regionchange ofThe comparison means for comparing with the result of the comparison by the comparison means,If the change in the spatial characteristics of the first region is greater than the change in the spatial characteristics of the second region,Tap reduction means for reducing the number of taps of the luminance signal component of the first digital signal, and a first coefficient corresponding to the class output by the class classification means are read from the storage means, the first coefficient, The first arithmetic means for obtaining the luminance signal component of the second digital image signal by calculating the luminance signal component of the digital image signal and the positional relationship between the pixels of the first and second digital image signals Second arithmetic means for obtaining a color signal component of the second digital image signal by performing an arithmetic operation on the second coefficient obtained based on the color signal component of the first digital image signal, The first calculation means performs the calculation using the luminance signal component of the first digital image signal in which the number of taps is reduced by the tap reduction means according to the comparison result by the comparison means. To.
[0010]
  Claim13The signal conversion method described in 1) performs class classification for obtaining a class based on the luminance signal component of the first digital image signal, and spatial features of the first region in the first digital image signal.change ofAnd spatial features of the second region that are larger than the first regionchange ofAnd the result of the comparison,If the change in the spatial characteristics of the first region is greater than the change in the spatial characteristics of the second region,The first coefficient for reducing the number of taps of the luminance signal component of the first digital signal and converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal for each class The first coefficient corresponding to the obtained class is read out from the storage means stored in the first digital image signal and the luminance of the first digital image signal in which the number of taps is degenerated according to the comparison result. Calculating the luminance signal component of the second digital image signal by performing an operation with the signal component, while obtaining a second coefficient obtained based on the positional relationship between the pixels of the first and second digital image signals; The color signal component of the second digital image signal is obtained by performing an operation with the color signal component of the first digital image signal.
[0011]
  In the signal conversion device according to claim 1, the storage means has a predetermined coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal. The class classification means performs class classification for obtaining a class based on the luminance signal component of the first digital image signal. The comparing means is a spatial feature of the first region in the first digital image signal.change ofAnd spatial features of the second region that are larger than the first regionchange ofAnd the tap degeneration means is the result of the comparison by the comparison means,If the change in the spatial characteristics of the first region is greater than the change in the spatial characteristics of the second region,The number of taps of the luminance signal component of the first digital signal is degenerated. The first calculation means reads out the first coefficient corresponding to the class output from the class classification means from the storage means, and calculates the first coefficient and the luminance signal component of the first digital image signal. Thus, the luminance signal component of the second digital image signal is obtained, and the second arithmetic means obtains the second obtained based on the positional relationship between the pixels of the first and second digital image signals. The color signal component of the second digital image signal is obtained by calculating the coefficient of the above and the color signal component of the first digital image signal. The first calculation means is configured to perform calculation using the luminance signal component of the first digital image signal in which the tap number is reduced by the tap reduction means in accordance with the comparison result by the comparison means.
[0012]
  Claim13In the signal conversion method described in 1), class classification for obtaining a class is performed based on the luminance signal component of the first digital image signal, and the spatial characteristics of the first region in the first digital image signal are obtained.change ofAnd spatial features of the second region that are larger than the first regionchange ofAnd the result of the comparison,If the change in the spatial characteristics of the first region is greater than the change in the spatial characteristics of the second region,The first coefficient for reducing the number of taps of the luminance signal component of the first digital signal and converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal for each class The first coefficient corresponding to the obtained class is read out from the storage means stored in the first digital image signal and the luminance of the first digital image signal in which the number of taps is degenerated according to the comparison result. Calculating the luminance signal component of the second digital image signal by performing an operation with the signal component, while obtaining a second coefficient obtained based on the positional relationship between the pixels of the first and second digital image signals; By calculating the color signal component of the first digital image signal, the color signal component of the second digital image signal is obtained.
[0014]
  That is, the signal conversion device according to claim 1 is configured to convert the first digital image signal into the first digital image signal.Higher resolutionIn the signal conversion apparatus for converting to the second digital image signal, the first coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal is a predetermined class. A storage unit (for example, the coefficient RAM unit 40 shown in FIG. 6) for storing each class, and a class classification unit (for example, FIG. Class classification unit 33 shown in FIG.A comparison means for comparing a change in the spatial characteristics of the first area in the first digital image signal with a change in the spatial characteristics of the second area larger than the first area, and a result of the comparison by the comparison means; Tap reduction means for reducing the number of taps of the luminance signal component of the first digital signal when the change of the spatial feature of the first region is larger than the change of the spatial feature of the second region;The first coefficient corresponding to the class output from the class classification means is read out from the storage means, and the first digital and the luminance signal component of the first digital image signal are calculated, whereby the second digital Obtained based on the positional relationship between the first arithmetic means (for example, the product-sum units 38 and 39 shown in FIG. 6) for obtaining the luminance signal component of the image signal and the pixels of the first and second digital image signals. Second arithmetic means (for example, an interpolation pixel shown in FIG. 6) that obtains the color signal component of the second digital image signal by performing the calculation of the second coefficient and the color signal component of the first digital image signal. Calculation unit 42)The first calculation means performs calculation using the luminance signal component of the first digital image signal in which the tap number is reduced by the tap reduction means according to the comparison result by the comparison means.It is characterized by that.
[0015]
  Claim3When the first digital image signal is a composite signal, the signal conversion device described in 1) separates the luminance signal component and the color signal component from the first digital image signal (for example, FIG. 1). And a D1 interface 1 shown in FIG.
[0018]
  Claim6In the signal conversion apparatus described in (1), the first calculation means is the first or second mode calculation means corresponding to the first or second mode (for example, the product-sum unit 38 or 39 shown in FIG. 6). ), And the degeneration means includes first or second mode degeneration means (for example, the tap degeneration section 35 or 36 shown in FIG. 6) corresponding to the first or second mode, respectively. And
[0019]
  Claim7The signal conversion device described in (1) further includes degeneration means for degenerating the number of classes (for example, the address degeneration circuit 141 and the class degeneration circuit 142 shown in FIG. 16).
[0020]
  Claim8The signal conversion device described in 1 is a first changing unit that changes the order of the scanning lines of the first digital image signal input to the first calculating unit between the first mode and the second mode. (For example, the scanning line conversion circuit 8 shown in FIG. 1 and the like) and the order of the scanning lines of the second digital image signal output from the first arithmetic means are changed before the first changing means. And a second changing means (for example, the scanning line conversion circuit 11 shown in FIG. 1).
[0021]
  Claim13In the signal conversion method described in 1), the first digital image signal is converted into the first digital image signal.Higher resolutionIn the signal conversion method for converting into the second digital image signal, class classification for obtaining a class is performed based on the luminance signal component of the first digital image signal,The change of the spatial feature of the first region in the first digital image signal is compared with the change of the spatial feature of the second region larger than the first region. Therefore, when the change in the spatial characteristics of the first region is large, the number of taps of the luminance signal component of the first digital signal is degenerated,Storage means (for example, a coefficient RAM shown in FIG. 6) that stores, for each class, a first coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal A first coefficient corresponding to the determined class, and the first coefficient,The number of taps was reduced according to the comparison result.By calculating the luminance signal component of the first digital image signal by calculating the luminance signal component of the second digital image signal, the luminance signal component of the second digital image signal is obtained based on the positional relationship between the pixels of the first and second digital image signals. The color signal component of the second digital image signal is obtained by calculating the obtained second coefficient and the color signal component of the first digital image signal.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing a configuration example of a signal conversion apparatus of the present invention. The interface 1 receives digital image data of an image of, for example, an NTSC system or other composite signal based on D1 which is a digital VTR (Video Tape Racorder) standard. The interface 1 separates and extracts the horizontal synchronization signal H, the vertical synchronization signal V, and the frame synchronization signal F from the input image data, and outputs them to a PLL (Phase Lock Loop) clock generation control circuit 2. The PLL clock generation control circuit 2 generates a clock in synchronization with the input signal and supplies it to each circuit.
[0024]
The interface 1 also separates the luminance signal Y and the color signals U and V from the input image data and outputs them to the matrix conversion circuit 3. The matrix conversion circuit 3 generates a color difference signal Pb and a color difference signal Pr from the input signal, and outputs them to the time division circuit 7. The time division circuit 7 time-divides the input color difference signals Pb and Pr and supplies them to the line memory 6.
[0025]
The matrix conversion circuit 3 directly supplies the luminance signal Y from the interface 1 to the line memory 6 and outputs it to the line memory 6 via the cascaded field memory 4 and further via the field memory 5. Therefore, the line memory 6 is supplied with the luminance signal of the current field, the luminance signal of one field before, and the luminance signal Y of one frame (two fields) before.
[0026]
The line memory 6 stores a luminance signal Y for seven lines of the current field, a luminance signal Y for two lines before the field, and a luminance signal Y for three lines before one frame, and converts each of them into a scanning line. The circuit 8 is supplied. Further, the line memory 6 stores data Pr and Pb of the color signal C for three lines of the current field supplied from the time division circuit 7 and supplies the data Pr and Pb to the scanning line conversion circuit 8.
[0027]
In the mode 1 (described later with reference to FIG. 4), the scanning line conversion circuit 8 outputs the input luminance signal Y and color signal C to the resolution creation device 9 as they are, as shown in FIG. To do. On the other hand, in the case of mode 2 (described later with reference to FIG. 4), as shown in FIG. 3, the order of the scanning lines of the luminance signal or color signal of each field is inverted up and down. That is, the order of the scanning lines is converted and output to the resolution creation device 9 so that the upper scanning lines are arranged below.
[0028]
The resolution creation device 9 performs initialization processing corresponding to the data supplied from the initialization circuit 10, and then corresponds to the pixel data and color signal C corresponding to the luminance signal Y input from the scanning line conversion circuit 8. Pixel data (SD data) to be processed is processed separately to generate higher resolution pixel data (HD data).
[0029]
That is, as shown in FIG. 4, the resolution creation device 9 generates HD data indicated by small circles in the figure from SD data indicated by large circles in the figure. In the figure, the solid line represents pixel data of the current field, and the broken line represents pixel data of the immediately preceding field.
[0030]
The scan line of the HD signal generated by the resolution creation device 9 is returned to the original order by the scan line conversion circuit 11. That is, when the scanning line conversion circuit 11 is in the mode 1, the scanning line conversion circuit 8 does not change the order of the scanning lines in the scanning line conversion circuit 8 as shown in FIG. Output each line in the same order. On the other hand, in mode 2, since the order is changed in the scanning line conversion circuit 8 as shown in FIG. 3, processing for returning this order to the original order is performed. The luminance signal component output from the scanning line conversion circuit 11 is supplied to the HD field memory 12, and the color signal component is supplied to the HD field memory 13 and stored therein.
[0031]
In the field memories 12 and 13, processing for converting the number of scanning lines from 1050 to 1125 is performed and then supplied to the HD interface 14. The HD interface 14 processes the input HD signal, converts it into an HD signal corresponding to a high-definition format, and outputs the HD signal.
[0032]
Note that each block constituting the signal conversion apparatus of FIG. 1 is configured by one chip, for example. However, it is also possible to configure a plurality of blocks (including all of them) with one chip.
[0033]
Next, the operation will be described. The interface 1 separates the luminance signal Y and the color signals U and V from the input NTSC image data and outputs them to the matrix conversion circuit 3. The matrix conversion circuit 3 supplies the luminance signal Y directly to the line memory 6 and outputs it to the line memory 6 after being delayed by one frame (two fields) via the field memories 4 and 5. At this time, the luminance signal delayed by one field by the field memory 4 is also supplied to the line memory 6. Further, the matrix conversion circuit 3 generates the color difference signal Pb and the color difference signal Pr, and the time division circuit 7 time-divides this and supplies the color difference signal Pb or the color difference signal Pr to the line memory 6.
[0034]
The line memory 6 includes the pixel data of the luminance signal for seven lines of the input predetermined field, the pixel data of the luminance signal for three lines one frame before delayed by the field memories 4 and 5, and the field memory 4. Pixel data of the delayed luminance signal for two lines is supplied to the scanning line conversion circuit 8.
[0035]
As shown in FIG. 2, when the scanning line conversion circuit 8 is in the mode 1, the input luminance signal for 7 lines in the current field, the luminance signal for 1 frame before 3 lines, and the 2 lines before 1 field are input. Minute luminance signals are supplied to the resolution creation device 9 in the same order. Similarly, pixel data of color signals for three lines is also supplied to the resolution creation device 9 in the same order.
[0036]
On the other hand, in mode 2, as shown in FIG. 3, among the luminance signals for the seven lines of the current field, the uppermost line is the lowermost and the lowermost line is the uppermost. The order is changed so as to be supplied to the resolution creation device 9. The order of the luminance signal of the field one frame before and the luminance signal of the previous field is also arranged so that the uppermost line is arranged on the lowermost side and the lowermost line is arranged on the uppermost side. It is changed and supplied to the resolution creation device 9. Similarly, for the color difference signals for three lines, the order is changed so that the signal of the uppermost line is arranged on the uppermost side, and the signal of the lowermost line is arranged on the lowermost side. Supply to the creation device 9.
[0037]
Here, mode 1 and mode 2 will be described. As shown in FIG. 4, when the target pixel is the SD pixel x13, the upper left HD pixel y1 and the upper right HD pixel y2 of the SD pixel x13, and the lower left HD pixel y3 and the lower right The HD pixel y4 is generated, and mode 1 is the mode in which the upper two HD pixels y1 and y2 are generated. In contrast, mode 2 is a mode in which the lower HD pixels y3 and y4 are generated.
[0038]
As shown in FIG. 5, when the vertical interval between SD pixels in each field is 1, the vertical interval between HD pixels y1 and y2 and SD pixel x13 is 1/8. The interval between the HD pixels y3 and y4 and the SD pixel x13 is 3/8. Therefore, the vertical interval between the HD pixels y1 and y2 and the HD pixels y3 and y4 is 4/8 (= 1/2).
[0039]
The resolution creation device 9 generates HD pixel data from the input SD pixel data and outputs the HD pixel data to the scanning line conversion circuit 11. A more detailed operation of the resolution creation device 9 will be described later with reference to FIG.
[0040]
The scanning line conversion circuit 11 outputs the pixel data of each line of the luminance signal inputted in mode 1 and the pixel data of each line of the color signal to the field memory 12 or the field memory 13 in the same order. . In the resolution creation device 9, 525 scanning lines are converted into 1050 scanning lines which are doubled. In the field memories 12 and 13, the 1050 scanning lines are further converted into 1125 scanning lines and supplied to the interface 14. The conversion of the scanning lines from 1050 lines to 1125 lines is performed by adding 75 dummy scanning lines. This is performed, for example, by reading out 75 scanning lines that are substantially invalid from the field memories 12 and 13, respectively.
[0041]
The interface 14 outputs the luminance signal Y and the color signal C supplied from the field memories 12 and 13 as HD signals corresponding to the high-definition format.
[0042]
In the embodiment shown in FIG. 1, the field memories 12 and 13 convert 1050 scanning lines into 1125 lines. However, if the 1050 scanning lines may remain, these fields are used. The memories 12 and 13 are not necessary.
[0043]
FIG. 6 illustrates a detailed configuration example of the resolution creation device 9. The delay register unit 31 is supplied with a luminance signal for seven lines in the current field, a luminance signal for three lines before one frame, and a luminance signal for two lines before one field from the scanning line conversion circuit 8. , To be remembered.
[0044]
FIG. 7 illustrates a configuration example of the delay register unit 31. As shown in the figure, the delay register unit 31 is provided with registers 51-1 to 51-12 for 12 lines so that pixel data for 12 lines can be stored. P registers are cascaded so as to hold P pixel data. For example, the registers 51-1-1 to 51-1-P are cascaded in the uppermost line, and the registers 51-2-1 to 51-2-P are cascaded in the second line. It is connected. Then, the pixel data held in the predetermined register is read out as appropriate, and is sent to the maximum / minimum value calculation unit 32, the class classification unit 33, the motion determination unit 34, the tap reduction unit 35, or the tap reduction unit 36, respectively. It is made to be supplied. Which pixel data is supplied is different for each part.
[0045]
FIG. 8 illustrates a configuration example of the maximum value / minimum value calculation unit 32. As shown in the figure, in the maximum / minimum value calculation unit 32, two pieces of predetermined pixel data are supplied to the comparative large selection circuit 61 and the comparative small selection circuit 65, respectively. The comparison large selection circuit 61 selects the larger one of the two inputs, and supplies the selected pixel data to one input of the register 62 and the comparison large selection circuit 63 or the comparison large selection circuit 64. The output of the register 62 is supplied to the other input of the comparative large selection circuit 63, and the output of the comparative large selection circuit 63 is supplied to the other input of the comparative large selection circuit 64.
[0046]
The comparison small selection circuit 65 selects the smaller one of the two pieces of pixel data, outputs it to the register 66, and supplies it to one input of the comparison small selection circuit 67 and the comparison small selection circuit 68. The other input of the comparison small selection circuit 67 is supplied with the output of the register 66, and the other input of the comparison small selection circuit 68 is supplied with the output of the comparison small selection circuit 67. The maximum value is output from the comparative large selection circuit 64, and the minimum value is output from the comparative small selection circuit 68.
[0047]
The comparative large selection circuit 61 is configured, for example, as shown in FIG. That is, the two inputs are input to the multiplexer (MUX) 71 and the comparator 72. The comparator 72 compares the magnitudes of the two input pixel data and outputs a selection signal for selecting the larger one to the multiplexer 71. The output of the multiplexer 71 is output via a register 73. The comparative large selection circuits 63 and 64 are also configured in the same manner as the comparative large selection circuit 61.
[0048]
The comparative small selection circuit 65 is configured as shown in FIG. 10, for example. Two pieces of pixel data are input to the multiplexer 81 and the comparator 82. The comparator 82 compares the magnitudes of the two input pixel data, and outputs a selection signal so that the multiplexer 81 selects and outputs the smaller one. The output of the multiplexer 81 is output via the register 83.
[0049]
Next, the operation will be described. For example, the class classification unit 33 mainly requires the maximum value and the minimum value of pixels within a predetermined range necessary for class classification (space class) for waveform expression in space. The maximum value / minimum value calculation unit 32 calculates the maximum value and the minimum value. In this case, to generate the HD pixels y1 and y2 shown in FIG. 4, as shown in FIG. Five SD pixels k1 to k5 in the vicinity of y2 are selected, and the maximum value and the minimum value among these five pixels are calculated.
[0050]
At this time, the SD pixels k1 and k2 are first input to the comparative large selection circuit 61. In the comparative large selection circuit 61, the comparator 72 compares the sizes of the SD pixel k1 and the SD pixel k2, and outputs a selection signal so that the multiplexer 71 selects the larger one. As a result, the larger one of the SD pixels k1 and k2 is held in the register 73. This data is supplied to and held in the register 62 of FIG.
[0051]
Next, the comparison size selection circuit 61 compares the sizes of the SD pixels k3 and k4. In the same manner as described above, the larger pixel is held in the register 73. The larger one of the SD pixels k3 and k4 held in the register 73 is supplied to the other input of the comparison large selection circuit 63. The comparison large selection circuit 63 compares the larger one of the SD pixels k1 and k2 held in the register 62 with the larger one of the SD pixels k3 and k4 held in the register 73, and selects the larger one. This is selected and output to the comparative large selection circuit 64 via the register 73.
[0052]
Next, the comparison large selection circuit 61 compares the SD pixel k5 with the 0 pixel (virtual pixel). In this case, the SD pixel k5 is selected and supplied to the other input of the comparative large selection circuit 64. The comparative large selection circuit 64 compares the SD pixel supplied from the comparative large selection circuit 63 with the SD pixel k5 supplied from the comparative large selection circuit 61, selects the larger one, and outputs it. In this way, the comparative large selection circuit 64 selects and outputs the largest one of the SD pixels k1 to k5.
[0053]
On the other hand, the comparator 82 of the comparison small selection circuit 65 first compares the magnitudes of the SD pixels k1 and k2, and outputs a selection signal for causing the multiplexer 81 to select the smaller one. As a result, the smaller one of the SD pixels k 1 and k 2 is output via the register 83 and held in the register 66. Next, the comparison small selection circuit 65 compares the sizes of the SD pixels k3 and k4, selects the smaller one, and outputs the smaller one to the comparison small selection circuit 67. The comparison small selection circuit 67 compares the smaller one of the SD pixels k1 and k2 supplied from the register 66 with the smaller one of the SD pixels k3 and k4 supplied from the comparison small selection circuit 65, The smaller one is output to the comparison small selection circuit 68.
[0054]
Further, the comparison small selection circuit 65 compares the SD pixel k5 with the virtual maximum pixel data, selects the SD pixel k5 as the smaller one, and supplies it to the comparison small selection circuit 68 via the register 83. The comparison small selection circuit 68 compares the output of the comparison small selection circuit 67 with the size of the SD pixel k5, and selects and outputs the smaller one. As described above, from the small comparison comparison circuit 68, the smallest one of the SD pixels k1 to k5 is output.
[0055]
In addition, the class classification unit 33 requires the maximum value and minimum value of the small area and the maximum value and minimum value of the large area. Therefore, the maximum value / minimum value calculation unit 32 calculates the maximum value and minimum value of the small area and the maximum value and minimum value of the large area in the same manner as described above. Here, as shown in FIG. 12, the small areas are the five SD pixels x5, x12, x13, x14, and x21 in the same field, which are located on the top, bottom, left, and right of the target SD pixel x13. The maximum value / minimum value calculation unit 32 obtains the maximum value and the minimum value among the five SD pixels in the same manner as described above, and outputs it to the class classification unit 33.
[0056]
Further, as shown in FIG. 13, the large area is located on the SD pixel x13 as the target pixel, the SD pixels x11, x12, x14, and x15 located on the same line in the same field, and the upper and lower lines thereof. It means 13 pixels of SD pixels x4 to x6, x20 to x22, and SD pixels x2 and x24 located on the upper and lower lines. The maximum value / minimum value calculation unit 32 obtains the maximum value and the minimum value among the 13 pixels in the same manner as described above, and outputs it to the class classification unit 33.
[0057]
FIG. 14 illustrates a configuration example of the motion determination unit 34. This configuration example, as shown in FIG. 15, uses 3 × 3 SD pixels m1 to m9 in the current field and SD pixels n1 to n9 at spatially corresponding positions one frame before, The structural example in the case of performing motion determination is represented.
[0058]
As shown in FIG. 14, among the 3 × 3 SD pixels, the uppermost line SD pixels (SD pixels m1 to m3 and SD pixels n1 to n3 in FIG. 15) are input to the absolute value calculation circuit 101. Then, the SD pixels (SD pixels m4 to m6 and SD pixels n4 to n6 in FIG. 15) of the next line are input to the absolute value calculation circuit 107, and the lowermost line is input to the absolute value calculation circuit 115. SD pixels (SD pixels m7 to m9 and SD pixels n7 to n9 in FIG. 15) are inputted. The absolute value calculation circuit 101 calculates the absolute value of the difference between the two input SD pixels, and outputs the calculation result to the register 102, the adder 103, and the adder 105. The adder 103 adds the output of the register 102 and the output of the absolute value arithmetic circuit 101 and outputs the result to the register 104. The adder 105 adds the output of the register 104 and the output of the absolute value calculation circuit 101 and outputs the result to the register 106.
[0059]
Similarly, the absolute value of the difference between the two SD pixels output from the absolute value calculation circuit 107 is supplied to the register 107 and the adders 109 and 111. The adder 109 adds the output of the register 108 and the output of the absolute value arithmetic circuit 107 and outputs the result to the register 110. The adder 111 adds the output of the register 110 and the output of the absolute value arithmetic circuit 107 and outputs the result to the register 112. The adder 113 adds the output of the register 106 and the output of the register 112 and outputs the result to the register 114.
[0060]
The absolute value calculation circuit 115 calculates the absolute value of the difference between the two input SD pixels, and outputs the output to the register 116 and the adders 117 and 119. The adder 117 adds the output of the register 116 and the output of the absolute value calculation circuit 115 and outputs the result to the register 118. The adder 119 adds the output of the register 118 and the output of the absolute value calculation circuit 115 and outputs the result to the register 120. The output of the register 120 is supplied to the register 121. The adder 122 adds the output of the register 114 and the output of the register 121 and outputs the result to the register 123.
[0061]
In the initial state, a predetermined set value (threshold value) is input and held in the register 126 and the register 127. The comparator 124 compares the value held in the register 123 with the set value (threshold value) held in the register 126 and outputs the comparison result to the encoder 128. The comparator 125 compares the value held in the register 123 with the set value (threshold value) held in the register 127 and outputs the comparison result to the encoder 128. The encoder 128 performs an encoding process corresponding to the output of the comparator 124 and the output of the comparator 125.
[0062]
Next, the operation will be described. The absolute value calculation circuit 101 calculates the absolute value of the difference between the SD pixel m1 in the current field and the SD pixel n1 in the corresponding spatial position one frame before, and outputs the calculation result to the register 102 for holding. At the next timing, the absolute value calculation circuit 101 calculates the absolute value of the difference between the SD pixels m2 and n2, and outputs the calculation result to the adder 103. The adder 103 adds the absolute value of the difference between the SD pixels m1 and n1 output from the register 102 and the absolute value of the difference between the SD pixels m2 and n2 output from the absolute value calculation circuit 101, and registers the addition result. It outputs to 104 and makes it hold | maintain.
[0063]
Further, at the next timing, the absolute value calculation circuit 101 calculates the absolute value of the difference between the SD pixels m3 and n3 and outputs the result to the adder 105. The adder 105 calculates the sum of the absolute value of the difference between the SD pixels m3 and n3, the absolute value of the difference between the SD pixels m1 and n1 held in the register 104, and the absolute value of the difference between the SD pixels m2 and n2. Add, output to register 106 and hold.
[0064]
As described above, the register 106 stores the absolute value of the difference between the SD pixels m1 and n1 in the uppermost line shown in FIG. 15, the absolute value of the difference between the SD pixels m2 and n2, and the difference between the SD pixels m3 and n3. The sum of absolute values of is held.
[0065]
A similar process is performed for the SD pixels on the second line and the third line. The register 112 on the second line stores the absolute value of the difference between the SD pixels m4 and n4 and the SD pixels m5 and n5. And the sum of the absolute values of the differences between the SD pixels m6 and n6 are held. The register 120 on the third line holds the sum of the absolute value of the difference between the SD pixels m7 and n7, the absolute value of the difference between the SD pixels m8 and n8, and the absolute value of the difference between the SD pixels m9 and n9. The
[0066]
The adder 113 adds the value held in the register 106 and the value held in the register 112 and outputs the result to the register 114. The output of the register 114 is supplied to the adder 122. The value held in the register 120 is supplied to the adder 122 via the register 121. Therefore, the adder 122 adds the output of the register 114 and the output of the register 121, and outputs the addition result to the register 123.
[0067]
As described above, the register 123 eventually holds the sum of the absolute values of the differences between the SD pixels m1 to m9 and the SD pixels n1 to n9 shown in FIG. That is, the following equation is calculated by the above circuit.
[Expression 1]

[0068]
The comparator 124 compares the value S held in the register 123 with the threshold value held in the register 126, for example, 1 when the value S is larger than the threshold value, 0 when the value S is smaller, and 128. Output to. Similarly, the comparator 125 compares the value S held in the register 123 with the threshold value held in the register 127 (which is smaller than the threshold value held in the register 126). When the value S is larger than the threshold, 1 is output to the encoder 128, and when the value S is smaller, 0 is output. When the outputs of the comparators 124 and 125 are both 0, the encoder 128 mainly outputs 0 as a class (motion class) for representing the degree of motion, and the output of the comparator 124 is 0. When the output of the comparator 125 is 1, 1 is output, and when the output of the comparator 124 is 1, 2 is output regardless of whether the output of the comparator 125 is 0 or 1.
[0069]
In the above description, the absolute value calculation circuits 101, 107, and 115 calculate the absolute value of the difference. However, 1/2 of the absolute value of the difference may be calculated. In this case, the values held in the registers 126 and 127 are also values corresponding to the absolute value of the difference per pixel.
[0070]
FIG. 16 illustrates a configuration example of the class classification unit 33. For example, SD pixels k1 to k5 (corresponding to the SD pixels x5, x8, x13, x18, and x21 in FIG. 4) shown in FIG. 11 are input to the ADRC (Adaptive Dynamic Range Coding) encoder 140 from the delay register unit 31. Is done. Further, the maximum value and the minimum value of the space class output from the maximum value / minimum value calculation unit 32 are input to the ADRC encoder 140. The ADRC encoder 140 sets the respective values of the SD pixels k1 to k5 to L, the maximum value of the SD pixels k1 to k5 to MAX, and the minimum value to MIN. Is calculated.
Q = [(L−MIN + 0.5) × 2ⁿ/ DR]
[] Means a truncation process, and DR is expressed by the following equation.
DR = MAX-MIN + 1
n means bit allocation. For example, in the case of 1-bit ADRC, n = 1.
[0071]
As described above, each of the five SD pixels is represented by a 1-bit requantization code Q, which is a total of 5 bits of SD pixels.
[0072]
The 5-bit space class data output from the ADRC encoder 140 is input to the address degeneration circuit 141 and degenerated into 4-bit data. FIG. 17 shows a configuration example of the address degeneration circuit 141.
[0073]
As shown in FIG. 17, the 5-bit outputs of the ADRC encoder 140 corresponding to the SD pixels k1 to k5 are assumed to be ADRC0 to ADRC4. ADRC0 is supplied to the multiplexers 155 to 158 as its switching signal. ADRC1 is input to the multiplexer 155 directly or inverted by the inverter 151. ADRC 2 is input to the multiplexer 156 directly or inverted by the inverter 152. The ADRC 3 is input to the multiplexer 157 either directly or inverted by the inverter 153. The ADRC 4 is input to the multiplexer 158 either directly or inverted by the inverter 154.
[0074]
When ADRC0 is 0, each of the multiplexers 155 to 158 selects ADRC1 to ADRC4 and outputs them as 4-bit data SP0 to SP3. On the other hand, when ADRC0 is 1, the multiplexers 155 to 158 select the outputs of the corresponding inverters 151 to 154 and output them as SP0 to SP3.
[0075]
In this way, the 5-bit space class is converted to 4 bits and output to the class degeneration circuit 142. Thus, for example, data “01111” is “1111”, data “10000” is also “1111”, and a common class.
[0076]
The class degeneration circuit 142 is also supplied with a 2-bit motion class output from the encoder 128 of the motion determination unit 34. That is, a class code of a total of 6 bits is input to the class degeneration circuit 142.
[0077]
The class degeneration circuit 142 degenerates this 6-bit class code to 5 bits and outputs it to the encoder 143. The encoder 143 encodes the input 5-bit class code and outputs it.
[0078]
The class degeneration circuit 142 is configured, for example, as shown in FIG. In the example of FIG. 18, MV1 as the MSB of the 2-bit motion class MV output from the motion determination unit 34 and MB0 as the LSB are supplied to the OR circuit 161. The output of the OR circuit 161 is input to the MSB terminal of one input of the adder 162. MV1 as the MSB of the motion class is input to the second bit from the MSB of one input of the adder 162. The lower 3 bits of one input of the adder 162 are grounded and set to 0.
[0079]
Of the data SP3 to SP0, which is 5-bit space class data output from the ADRC encoder 140 and has been reduced to 4 bits by the address reduction circuit 141, the SP3 of the MSB is the second terminal from the MSB of the shifter 163 SP2 is input to the second terminal from the MSB, SP1 is input to the third terminal from the MSB, and SP0 is input to the LSB terminal. The MSB terminal of the shifter 163 is grounded and set to zero.
[0080]
The shifter 163 operates corresponding to the motion class. When the motion class is 0, the lower 4 bits of the input data are input as they are to the lower 4 bits of the other input of the adder 162. On the other hand, when the motion class is not 0 (1 or 2), the shifter 163 shifts the lower 4 bits of data to the LSB side bit by bit. That is, the input data is substantially ½ value. Then, the data after the bit shift is supplied to the lower 4 bits of the other input of the adder 162. The MSB of the other input of the adder 162 is grounded and is always set to zero.
[0081]
The adder 162 adds the 5-bit data supplied from one input and the 5-bit data supplied from the other input, outputs the addition result to the register 164, and holds it. . Note that the adder 162 in this example substantially constitutes the encoder 143 in FIG.
[0082]
Further, the maximum value and the minimum value of the large area shown in FIG. 13 are supplied from the maximum value / minimum value calculation unit 32 to the classifier 33 to the subtractor 144. The subtractor 144 subtracts the minimum value from the input maximum value and outputs the result to the comparator 145. The maximum value and minimum value of the small area shown in FIG. 12 are input to the subtracter 146 from the maximum value / minimum value calculation unit 32. The subtractor 146 subtracts the minimum value from the input maximum value and outputs the subtraction result to the multiplier 147. The register 148 holds a predetermined set value in advance in an initial state. The multiplier 147 multiplies the value input from the subtracter 146 by the coefficient held in the register 148, and outputs the multiplier result to the comparator 145. The comparator 145 compares the output of the subtractor 144 and the output of the multiplier 147. When the output of the subtracter 144 is larger, the comparator 145 outputs a short tap selection signal, and the output of the subtracter 144 is the multiplier. When the output is smaller than 147, a long tap selection signal is output.
[0083]
Next, the operation will be described. The ADRC encoder 140 calculates the re-quantization code Q for each of the input 5-pixel SD data k1 to k5 according to the above-described formula, and outputs 5-bit data ADRC0 to ADRC4 as data representing the space class. To do. The 5-bit data is degenerated into 4-bit data SP3 to SP0 by the address degeneration circuit 141 and supplied to the shifter 163 of the class degeneration circuit 142. As described above, the class degeneration circuit 142 is also supplied with the motion classes MV1 and MV0 from the motion determination unit 34.
[0084]
For example, suppose that a class code is composed of 6 bits consisting of a motion class of upper 2 bits (MV1, MV0) and a space class of lower 4 bits (SP3, SP2, SP1, SP0). Is “010011”, the OR circuit 161 outputs “1” to the MSB of one input of the adder 162, and “0” that is the MSB of the motion class is input to the next bit. . Since the lower 3 bits of one input of the adder 162 are always 0, eventually, “10000” is input to one input of the adder 162.
[0085]
On the other hand, since the class is 1 and not 0, the shifter 163 shifts “0011” input to the terminals SP3 to SP0 bit by bit to the LSB side to “0001”. This is input to the lower 4 bits of the other input of the adder 162, and its MSB is always 0, so that “00001” is eventually supplied to the other input of the adder 162. As a result, the output of the adder 162 becomes “10001”, which is output to the register 164 and held. As a result, the class code is degenerated from 19 (= 000111) to 17 (= 10001).
[0086]
Similarly, when the class code is “100101”, “11000” is input to one input of the adder 162 and “00010” is input to the other input. As a result, the output of the adder 162 becomes “11010”, and the class code is degenerated from 37 (= 100101) to 26 (= 111010).
[0087]
FIG. 19 shows how a class is degenerated in this way. As shown in the figure, assuming that the classes before degeneration when the motion class is 0, 1 or 2 are 0 to 15, 16 to 31, or 32 to 47, respectively, a total of 48 classes are represented. Therefore, a 6-bit code is required. On the other hand, by performing class degeneration processing by the class degeneration circuit 142, the degenerated classes when the motion class is 0 are set to 0 to 15, but the classes when the motion class is 1 are set to 16 to 23, when the motion class is 2, the classes are 24 to 31 and ½ before degeneration, so that the total number of classes is 32 and can be represented by 5 bits. Therefore, the number of coefficients stored in the coefficient RAM section 40 to be described later is reduced accordingly, and the capacity of the coefficient RAM section 40 can be reduced accordingly.
[0088]
On the other hand, the subtracter 144 subtracts the minimum value from the maximum value of the large area and outputs the result to the comparator 145. The subtracter 146 subtracts the minimum value from the maximum value of the small area and outputs the result to the multiplier 147. Multiplier 147 multiplies the output of subtractor 146 by the coefficient held in register 148 and outputs the result to comparator 145. The value set in the register 148 is the difference between the maximum value and the minimum value of the five SD pixels in the small area shown in FIG. 12, and the difference between the maximum value and the minimum value of the 13 SD pixels in the large area shown in FIG. It adjusts so that it may become a value corresponding to. The comparator 145 compares the output of the subtractor 144 and the output of the multiplier 147 to determine whether there is a steep change.
[0089]
When the output of the subtractor 144 is smaller than the output of the multiplier 147 (when there is no steep change), the comparator 145 outputs a long tap selection signal, and the output of the subtractor 144 is the output of the multiplier 147. When larger than the output (when there is a steep change), the comparator 145 outputs a short tap selection signal. Thereby, when there is a steep change, the prediction range is narrowed to suppress the generation of ringing components.
[0090]
As will be described in detail later, when a long tap selection signal is output, SD pixels x1, x2, x4 to x6, x10 to x16, which are present in a predetermined field shown in FIG. Seventeen (17 taps) SD pixels of x20 to x22, x24 are subjected to tap degeneration to generate data of 7 pixels (7 taps). Calculate the pixel. On the other hand, when the short tap is selected, as shown in FIG. 20, for the seven existing SD pixels (7 taps) of the SD pixel data x2, x5, x12 to x14, x21, x24, Thus, the HD pixel is obtained by calculating the product sum. In any case, since the number of taps in which the coefficient is finally calculated is seven, the product-sum units 38 and 39 as circuits for product-sum calculation can be shared.
[0091]
The control ROM unit 37 controls the tap degeneration units 35 and 36 in accordance with the class code output from the class classification unit 33 and the long tap or short tap selection signal. That is, when a long tap selection signal is input, the control ROM unit 37 controls the tap degeneration units 35 and 36, and the delay register unit 31 performs 17-tap SD pixels in the current field shown in FIG. x1, x2, x4 to x6, x10 to x16, x20 to x22, x24, x25 are taken in. On the other hand, when a short tap selection signal is input, the control ROM unit 37 sends seven taps in the current field shown in FIG. 20 from the delay register unit 31 to the tap degeneration units 35 and 36. The SD pixels x2, x5, x12 to x14, x21, x24 are taken into the tap degeneration units 35, 36.
[0092]
When the tap reduction units 35 and 36 take in the 17 SD pixels shown in FIG. 4, the tap reduction units 35 and 36 perform a process of reducing them to 7 pixels, and output them to the corresponding product-sum units 38 and 39. A circuit that degenerates 17 pixels to 7 pixels has an enormous configuration and is difficult to illustrate. Therefore, here, a configuration example of the tap degeneration unit in a case where seven pixels are taken in and degenerated into three pixels will be described with reference to FIG.
[0093]
FIG. 21 shows a configuration example of the mode 1 tap degeneration section 35. As shown in FIG. 21, among the seven SD pixels shown in FIG. 22, the SD pixel x2 is supplied to each of the two input terminals at the input of the multiplexer 181-1. The multiplexer 181-2 is supplied with the SD pixel x5 at either of the two inputs. The SD pixel x12 is supplied to the left input of the multiplexer 181-3, and the SD pixel x14 is supplied to the right input. The multiplexer 181-4 is supplied with the SD pixel x13 for both of the two inputs. The SD pixel x14 is supplied to the left input of the multiplexer 181-5, and the SD pixel x12 is supplied to the right input. The multiplexer 181-6 is supplied with the SD pixel x21 at both of its two inputs, and the multiplexer 181-7 is supplied with the SD pixel x24 at both of its two inputs.
[0094]
That is, as shown in FIG. 22, a pixel in which there is a pixel corresponding to left-right symmetry with respect to a vertical line is supplied to one input and the other input of the corresponding multiplexer. The arrangement of the inputs of one multiplexer and the other multiplexer is made symmetric. That is, as shown in FIG. 21, in the multiplexer 181-3, the SD pixel x12 is supplied to the left input and the SD pixel x14 is supplied to the right input, whereas in the multiplexer 181-5 The SD pixel x14 is supplied to the left input, and the SD pixel x12 is supplied to the right input.
[0095]
The same pixel is supplied to each of the two inputs of the multiplexer corresponding to the pixel in which no corresponding pixel exists as line symmetry.
[0096]
For example, when a logic 0 control signal is input from the control ROM unit 37, each multiplexer 181-1 to 181-7 selects and outputs the left input of the left and right inputs, and the logic 1 is input. When the right input is selected and output. Therefore, when a control signal of logic 0 is input to the registers 182-1 to 182-7 to the multiplexers 181-1 to 181-7, the SD pixels x2, x5, x12, x13, x14, x21 or x24 are stored. Respectively. On the other hand, when a logic 1 control signal is input to the multiplexers 181-1 to 181-7, the SD pixels x2, x5, x14, x13, x12, x21 or x24 are held.
[0097]
In contrast to the control of the multiplexers 181-1 to 181-7, the control after the registers 182-1 to 182-7 is performed at double speed.
[0098]
As described with reference to FIG. 20, when generating the upper left HD pixel y1 of the SD pixel x13, for example, logic 0 is input to the multiplexers 181-1 to 181-7, and the upper right HD pixel y2 is generated. , Logic 1 is input.
[0099]
The pixel data held in the register 182-1 is output as it is through the registers 186-1, 188-1, and 190-1.
[0100]
The SD pixel held in the register 182-2 is supplied to the right input of the multiplexer 183-1 and the left input of the multiplexer 183-3. The output of the register 182-2 is supplied to the left input of the multiplexer 183-1 and the right input of the multiplexer 183-4. The output of the register 182-4 is supplied to one input of the multiplexer 183-2 and also supplied to the right input of the multiplexer 183-5. The output of the register 182-5 is supplied to the left input of the multiplexer 183-4. The output of the register 182-6 is supplied to the right input of the multiplexer 183-3. The output of the register 182-7 is supplied to the left input of the multiplexer 183-5.
[0101]
The multiplexers 183-1 to 183-5 select one of the left input and the right input corresponding to the control code supplied from the control ROM unit 37, and outputs the selected input to the subsequent circuit. The multiplexer 183-1 supplies the selected SD pixel data to the 2's complement circuit 184-1. The 2's complement circuit 184-1 outputs the data input from the multiplexer 183-1 as it is to the register 186-2 in response to the control signal from the control ROM section 37, or performs the 2's complement operation. The operation result is output to the register 186-2. The 2's complement operation is performed by inverting 1 of bits of SD data to 0, inverting 0 to 1, and adding (adding) 1 to LSB.
[0102]
The multiplexer 183-2 selects data from the register 182-4 or 0 corresponding to the control code from the control ROM unit 37 and outputs it to the register 186-3. The adder 187-1 adds the output of the register 186-2 and the output of the register 186-3, and outputs the result via the register 188-2 and the register 190-2.
[0103]
The multiplexer 183-3 selects one of the output of the register 182-2 or the output of the register 182-6 in accordance with the control code of the control ROM unit 37 and supplies the selected one to the two's complement circuit 184-2. Similarly to the case of the 2's complement circuit 184-1, the 2's complement circuit 184-2 accepts the pixel data supplied from the multiplexer 183-3 as it is or in response to the control code from the control ROM unit 37, or 2's complement operation is performed and output to the register 186-4.
[0104]
The multiplexer 183-4 selects the output of the register 182-5 or the output of the register 182-3 corresponding to the control code from the control ROM unit 37, and outputs the selected pixel data to the 2's complement circuit 185. The 2's complement circuit 185 performs a 2's complement operation on the pixel data input from the multiplexer 183-4, and outputs the operation result to the register 186-5. The adder 187-2 adds the output of the register 186-4 and the output of the register 186-5, and outputs the result to the register 188-3.
[0105]
The multiplexer 183-5 selects one of the output of the register 182-7 and the output of the register 182-4 according to the control code of the control ROM unit 37 and outputs it to the 2's complement circuit 184-3. The two's complement circuit 184-3 outputs the input pixel data as it is to the register 186-6 corresponding to the control code from the control ROM section 37, or performs a two's complement operation to register 186- 6 is output. The output of the register 186-6 is further supplied to the register 188-4.
[0106]
The adder 189 adds the output of the register 188-3 and the output of the register 188-4, and outputs the addition result to the register 190-3.
[0107]
As described above, the 7-tap data shown in FIG. 22 is converted into 3-tap data.
[0108]
Since neighboring image data has strong autocorrelation, it is often left-right symmetric with respect to the central SD pixel data. Therefore, in the tap degeneracy unit 35, when the HD pixel y1 having a mirror image relationship in the horizontal direction is obtained and when the HD pixel y2 is obtained, the SD pixel having the mirror image relationship is simply replaced, and the substantially same circuit is obtained. Both the HD pixel y1 and the HD pixel y2 can be obtained.
[0109]
Similarly, when the tap reduction unit 36 generates the HD pixel y3 and the HD pixel y4 that are mirror images in the horizontal direction, the same tap reduction process can be performed.
[0110]
In addition, when 17 taps are taken in tap degeneration sections 35 and 36 and 7 taps are output, the mirror image relationship is as shown in FIG. That is, SD pixels x4 and x6 are mirror images. Similarly, SD pixels x10 and x16, x11 and x15, x12 and x14, and x20 and X22 are mirror images.
[0111]
The multiplexers 181-1, 181-2, 181-4, 181-6, and 181-7 to which pixel data not in the mirror image relation in FIG. 21 are input substantially always select and output the same pixel data. Therefore, it can be omitted.
[0112]
As described above, in the long tap mode, the data of 7 taps reduced from 17 taps by the tap reduction units 35 and 36 are input to the product-sum units 38 and 39 of mode 1 and mode 2, respectively. In the short tap mode, the 7-tap data captured by the tap degeneration units 35 and 36 is input to the product-sum units 38 and 39 as they are.
[0113]
FIG. 24 illustrates a configuration example of the coefficient RAM unit 40. Although this example shows a case where the coefficients for 3 taps are stored, the coefficient RAM unit 40 in FIG. 6 stores the coefficients for 7 taps as described above.
[0114]
In the initialization mode, the decoder 202 puts SRAMs (Static Random Access Memory) 205-1 to 205-3 into a write state. The initialization counter 201 counts the clock and outputs the count value. In the initialization mode, the decoder 202 controls the multiplexer 203 and causes the output of the initialization counter 201 to be selected. As a result, the count value of the initialization counter 201 is supplied from the multiplexer 203 to the register 204 and held. Then, the count value held in the register 204 is supplied to the SRAMs 205-1 to 205-3 as a write address. At this time, the coefficient data supplied from the initialization circuit 10 is supplied to the SRAMs 205-1 to 205-3. As a result, the coefficients supplied from the initialization circuit 10 are written in the SRAMs 205-1 to 205-3 at the address specified by the initialization counter 201.
[0115]
Thus, when all the necessary coefficients are written in the SRAMs 205-1 to 205-3, the initialization counter 201 is reset in response to the reset signal supplied from the initialization circuit 10, and the decoder 202 When the initialization counter 201 is reset, the SRAMs 205-1 to 205-3 are set to the read mode, the multiplexer 203 is controlled, the class code output from the encoder 143 of the class classification unit 33 is selected, and the register 204 is selected. Supply. As a result, the class code held in the register 204 is supplied to the SRAMs 205-1 to 205-3 as a read address. Accordingly, the coefficient corresponding to the class code is read from the SRAMs 205-1 to 205-3 and output via the registers 206-1 to 206-3. The coefficients read out in this way are supplied to the product-sum units 38 and 39.
[0116]
Here, the coefficient for each class stored in the coefficient RAM unit 40 is calculated by using, for example, a learning method described in Japanese Patent Application Publication No. 9-51510 (published on February 18, 1997). Can do. That is, a coefficient for each class can be calculated by performing learning using an already known HD signal as learning data. Specifically, the SD signal for learning is generated by thinning out the HD signal as the learning data. Further, a certain HD pixel constituting the HD signal as the learning data is set as the target HD pixel, and the target HD pixel is located in the vicinity thereof, and several SD pixels constituting the learning SD signal and a predetermined coefficient It is expressed by a linear linear combination model using The coefficient used at this time is obtained for each class using the least square method. As described above, when a coefficient is obtained by using a known HD signal as learning data, a more accurate coefficient can be obtained by using not only one HD signal (one-screen HD image) but also a plurality of HD signals. Can be obtained. For details, reference is made to the above application, and the description is omitted here.
[0117]
FIG. 25 illustrates a configuration example of the product-sum unit 38. As described above, the product-sum unit 38 (same for the product-sum unit 39) multiplies the 7-tap data supplied from the tap degeneration unit 35 by 7 coefficients supplied from the coefficient RAM unit 40. One HD pixel data is obtained by calculation. For convenience of explanation, FIG. 25 shows a configuration example in the case of performing a 4-tap product-sum operation.
[0118]
In FIG. 25, the 4-tap pixel data supplied from the tap degeneration unit 35 is held in the registers 211-1 to 211-4, respectively. Further, the coefficient data supplied from the coefficient RAM unit 40 is held in the registers 212-1 to 212-4. The multiplier 213-1 multiplies the pixel data held in the register 211-1 by the coefficient data held in the register 212-1 and outputs the result to the register 214-1. The multiplier 213-2 multiplies the pixel data held in the register 212 and the coefficient data held in the register 212-2, and outputs the multiplication result to the register 214-2.
[0119]
Adder 215-1 adds the value held in register 214-1 and the value held in register 214-2, and outputs the addition result to register 216-1.
[0120]
Similarly, the pixel data held in the register 211-3 and the coefficient data held in the register 212-3 are multiplied by the multiplier 213-3 and held in the register 214-3. Further, the pixel data held in the register 211-4 and the coefficient data held in the register 212-4 are multiplied by the multiplier 213-4 and held in the register 214-4.
[0121]
The adder 215-2 adds the value held in the register 214-3 and the value held in the register 214-4, and outputs the result to the register 216-2 for holding.
[0122]
The adder 217 adds the value held in the register 216-1 and the value held in the register 216-2, and outputs the result via the register 218.
[0123]
That is, by this circuit, pixel data held in the registers 211-1 to 211-4 are x1 to x4 for convenience, and coefficients held in the registers 212-1 to 212-4 are w1 to w4. The register 218 holds the calculation result represented by the following expression as HD pixel data.
HD = x1 * w1 + x2 * w2 + x3 * w3 + x4 * w4
[0124]
As described above, the HD pixels y1 and y2 are calculated and output to the scanning line conversion circuit 11.
[0125]
Similarly, the product-sum unit 39 multiplies the pixel data supplied from the tap reduction unit 36 and the coefficient data supplied from the coefficient RAM unit 40 to calculate HD pixels y3 and y4, and scans them. It is output to the line conversion circuit 11.
[0126]
As described above, HD pixels are generated from SD pixels for the luminance signal component. With the same configuration, it is also possible to calculate and generate HD pixels from SD pixels for the color signal components, but in this case, it is necessary to provide a coefficient RAM unit for the color signal components. The resolution creation device 9 becomes large and expensive. Therefore, in this embodiment, the color signal component is processed with a configuration different from the luminance signal component.
[0127]
That is, as shown in FIG. 6, the pixel data of the color signal components for three lines input from the scanning line conversion circuit 8 are input to the delay register unit 41 and held. The configuration of the delay register unit 41 is basically the same as that of the delay register unit 31 that holds the luminance signal component except that the number of lines is different. The delay register unit 41 holds pixel data for a total of three lines, the pixel data of the color signal component of the line of the target pixel and the pixel data of the color signal component of the upper and lower lines of the same field. .
[0128]
The pixel data held in the delay register unit 41 is input to the interpolation pixel calculation unit 42 and subjected to interpolation processing.
[0129]
FIG. 26 illustrates a configuration example of the interpolation pixel calculation unit 42 in FIG. 6 when generating HD pixels y1 and y2 in mode 1. As shown in FIG. 27, the interpolation pixel calculation unit 42 includes HD pixels (color signal components) y_C1, y_CSD pixel data of the upper line of 2 (SD pixel data of terminals U1 to U5) (color signal component) and SD pixel of the lower line (SD pixel data of terminals J1 to J5) are input. Yes. The 8-bit SD pixel data at the terminal U1 is shifted by 3 bits to the LSB side by the shifter 231 and input to the multiplexer 233 as 5-bit SD pixel data. The 8-bit SD pixel data at the terminal U3 is shifted by 3 bits to the LSB side by the shifter 232 and input to the multiplexer 233 as 5-bit SD pixel data. The multiplexer 233 selects one of the SD pixel data input by the shifter 231 or the shifter 232 according to the selection signal. The output of the multiplexer 233 is supplied to the adder 236 via the registers 234 and 235.
[0130]
The shifter 237 shifts 8-bit data input from the terminal U3 by 3 bits to the LSB side, and supplies the shifted data to the adder 236 as 5-bit data. The adder 236 adds 5-bit data supplied from the register 235 and the shifter 237, and supplies the result to the adder 239 via the register 238 as 6-bit data.
[0131]
The shifter 240 shifts the 8-bit SD pixel data at the terminal J2 to the LSB side by 2 bits, and supplies it to the multiplexer 242 as 6-bit data. The shifter 241 shifts the 8-bit SD pixel data at the terminal J4 to the LSB side by 2 bits and supplies it to the multiplexer 242 as 6-bit data. The multiplexer 242 selects one of the two inputs corresponding to the selection signal, and supplies the selected input to the adder 239 via the register 243.
[0132]
The adder 239 adds the output of the register 238 and the output of the register 243, and supplies 7-bit data to the adder 245 via the register 244.
[0133]
The shifter 246 shifts the 8-bit data supplied from the terminal J4 to the LSB side by one bit and supplies it to the adder 245 as 7-bit data. The adder 245 adds the output of the register 244 and the output of the shifter 246 and outputs 8-bit data via the register 247.
[0134]
Note that the shifters 231, 232, 237, 240, 241, and 246 in FIG. 26 can be realized by wiring only predetermined bits from the MSB side to the subsequent stage.
[0135]
As shown in FIG. 27, the HD pixel y generated in mode 1_C1, y_C2 and the SD pixel of interest at the terminal J3 are a1, HD pixel y_C1, y_C2 and the SD pixel of the terminal U3 is b1, HD pixel y_C1, y_C2 and the SD pixel of the terminals U4 and U2 is c1, and the HD pixel y_C1, y_CWhen the distance between 2 and the SD pixel at the terminals J4 and J2 is d1, the reciprocal ratio is as follows.
1 / a1: 1 / b1: 1 / c1: 1 / d1 = 1/2: 1/8: 1/8: 1/4
[0136]
Similarly, HD pixel y generated in mode 2_C3, y_C4 to the SD pixel at the terminal J3 is a2, the distance to the SD pixel at the terminal K3 is b2, the distance to the terminals K4 and K2 is c2, and the distance to the SD pixel at the terminals J4 and J2 is d2. The ratio of the reciprocal of the distance is as follows.
1 / a2: 1 / b2: 1 / c2: 1 / d2 =
3/8: 3/16: 3/16: 1/4
[0137]
Next, the operation will be described with reference to the timing chart of FIG. 27, assuming that SD pixels A ′ to I ′ are sequentially input to terminals U1 to U5 and SD pixels A to I are sequentially supplied to terminals J1 to J5, as shown in FIG. As described above, the pixel data of each of the terminals U1 to U5 or each of the terminals J1 to J5 is sequentially delayed by one clock from the adjacent terminal.
[0138]
The multiplexer 233 alternately selects one of the two inputs with a period of 1/2 with respect to the period of shift of the pixel data. Accordingly, as shown in FIG. 28, if the register 234 holds the SD pixel E ′ supplied from the shifter 231 at a predetermined timing, the SD pixel C ′ supplied from the shifter 232 at the next timing. Hold. The SD pixels E ′ and C ′ held in the register 234 are sequentially transferred to the subsequent register 235.
[0139]
When the SD pixel E ′ is held in the register 235 and supplied to one input of the adder 236, the SD pixel D ′ is supplied from the shifter 237 to the other input of the adder 236. The adder 236 adds the two inputs and outputs the result to the register 238, so that the data E ′ + D ′ is held in the register 238. At the next timing, the adder 236 adds the SD pixel C ′ held in the register 235 and the SD pixel D ′ supplied from the shifter 237, so that the data C ′ + D is stored in the register 238. 'Is retained.
[0140]
Similarly, the multiplexer 242 that alternately selects and outputs one of the two inputs in a period that is a half of the data transfer period is the timing when the register 238 holds the data C ′ + D ′. The SD pixel E supplied from the shifter 240 is selected and held in the register 243, and the SD pixel C is held in the register 243 at the timing when the data C ′ + D ′ is held in the register 238.
[0141]
The adder 239 adds the data held in the register 238 and the register 243 and outputs the result to the register 244. Therefore, the register 244 holds the data E ′ + D ′ in the register 238 and the data E in the register 243. At the next timing after the current state, the data E ′ + D + E obtained by adding the two data is held. The register 244 holds data C ′ + D ′ + C at the next timing.
[0142]
At the timing when the data E ′ + D + E is held in the register 244, the shifter 246 outputs the data D. Therefore, the adder 245 adds the data E ′ + D + E held in the register 244 and the data D output from the shifter 246, and holds the data E ′ + D ′ + E + D in the register 247. Similarly, at the next timing, data C ′ + D ′ + C is held in the register 244 and data D is supplied from the shifter 246, so that data C ′ + D ′ + C + D is held in the register 247.
[0143]
As described with reference to FIG. 27, the data E ′, C ′, D ′, E, C, and D have the following relationships with the pixel data of the respective terminals.
E '= (1/8) U2
C '= (1/8) U4
D '= (1/8) U3
E = (1/4) J2
C = (1/4) J4
D = (1/2) J3
[0144]
Therefore, the data E ′ + D ′ + E + D is an HD pixel y expressed by the following equation:_C2 is represented.
y_C2 = (1/8) U2 + (1/8) U3 + (1/4) J2 + (1/2) J3
[0145]
Further, the data C ′ + D ′ + C + D is an HD pixel y expressed by the following equation:_C1 will be represented.
y_C1 = (1/8) U4 + (1/8) U3 + (1/4) J4 + (1/2) J3
[0146]
In the above, in mode 1, the HD pixel y_C1, y_C2 has been explained, the HD pixel y in mode 2_C3, y_CAlso in the case of obtaining 4, calculation is performed by normal interpolation processing according to the above-described equation.
[0147]
In the above description, the case where the NTSC SD signal is converted into the HD signal of the high vision has been described as an example. However, the present invention is not limited to such a method. In short, the present invention can be applied when generating high-quality pixel data from low-quality pixel data.
[0148]
【The invention's effect】
As described above, according to the signal conversion device and the signal conversion method of the present invention, for the luminance signal component, for example, the first coefficient corresponding to the class obtained by learning or the like is used.CalculationFor the color signal component, the second coefficient obtained based on the positional relationship between the pixels of the first and second digital image signals is used.CalculationTherefore, it is possible to reduce the capacity for coefficient storage, and to reduce the size and cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a signal conversion apparatus of the present invention.
2 is a diagram for explaining a forward operation of the scanning line conversion circuit 8 of FIG. 1; FIG.
FIG. 3 is a diagram illustrating an operation in the reverse direction of the scanning line conversion circuit 8 of FIG. 1;
FIG. 4 is a diagram for explaining processing of the resolution creation device 9 of FIG. 1;
FIG. 5 is a diagram illustrating a positional relationship between SD pixels and HD pixels.
6 is a block diagram illustrating a configuration example of the resolution creation device 9 in FIG. 1;
7 is a block diagram illustrating a configuration example of a delay register unit 31 in FIG. 6. FIG.
8 is a block diagram illustrating a configuration example of a maximum value / minimum value calculation unit 32 in FIG. 6;
9 is a block diagram illustrating a configuration example of a comparative large selection circuit 61 in FIG. 8;
10 is a block diagram illustrating a configuration example of a small comparison selection circuit 65 in FIG. 8;
FIG. 11 is a diagram illustrating a range of pixels of a space class.
FIG. 12 is a diagram illustrating pixels in a small area.
FIG. 13 is a diagram illustrating pixels in a large area.
14 is a block diagram illustrating a configuration example of a motion determination unit 34 in FIG. 6;
15 is a diagram for explaining processing of the absolute value calculation circuit 101 in FIG. 14; FIG.
16 is a block diagram illustrating a configuration example of a class classification unit 33 in FIG. 6;
17 is a block diagram showing a configuration example of an address degeneration circuit 141 in FIG.
18 is a block diagram illustrating a configuration example of a class degeneration circuit 142 in FIG. 16. FIG.
FIG. 19 is a diagram for explaining the operation of the class degeneration circuit 142 in FIG. 16;
FIG. 20 is a diagram illustrating a pixel range in a short tap mode.
21 is a block diagram illustrating a configuration example of a tap degeneration unit 35 in FIG. 6. FIG.
FIG. 22 is a diagram illustrating a 7-tap pixel range.
FIG. 23 is a diagram illustrating a 17-tap pixel range.
24 is a block diagram illustrating a configuration example of a coefficient RAM unit 40 in FIG. 6;
25 is a block diagram illustrating a configuration example of a product-sum unit 38 in FIG. 6;
26 is a block diagram illustrating a configuration example of an interpolation pixel calculation unit 42 in FIG. 6;
27 is a diagram for explaining the operation of the interpolated pixel calculation unit 42 in FIG. 26;
FIG. 28 is a timing chart for explaining the operation of the interpolated pixel calculation unit of FIG.
[Explanation of symbols]
4, 5 field memory, 6 line memory, 8 scanning line conversion circuit, 9 resolution creation device, 10 initialization circuit, 11 scanning line conversion circuit, 12, 13 HD field memory, 31 delay register section, 32 maximum value minimum value calculation Unit, 33 class classification unit, 34 motion determination unit, 35, 36 tap reduction unit, 37 control RAM unit, 38, 39 product sum unit, 40 coefficient RAM unit, 41 delay register unit, 42 interpolation pixel calculation unit

Claims (13)

In a signal converter for converting a first digital image signal into a second digital image signal having a higher resolution than the first digital image signal,
Storage means for storing, for each predetermined class, a first coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal;
Class classification means for classifying the class based on a luminance signal component of the first digital image signal;
Comparing means for comparing a change in spatial characteristics of a first region in the first digital image signal with a change in spatial features of a second region larger than the first region;
As a result of the comparison by the comparison means, if the change in the spatial feature of the first region is larger than the change in the spatial feature of the second region, the number of taps of the luminance signal component of the first digital signal Tap reduction means to reduce,
The first coefficient corresponding to the class output by the class classification unit is read from the storage unit, and the first coefficient and the luminance signal component of the first digital image signal are calculated, First computing means for determining a luminance signal component of the second digital image signal;
By calculating the second coefficient obtained based on the positional relationship between the pixels of the first and second digital image signals and the color signal component of the first digital image signal, the second coefficient A second computing means for obtaining a color signal component of the digital image signal,
The first calculation means performs calculation using a luminance signal component of the first digital image signal in which the number of taps is reduced by the tap reduction means according to a result of comparison by the comparison means. A signal converter. 2. The signal conversion apparatus according to claim 1, wherein the calculation by the first calculation means is a product-sum calculation of the first coefficient and the tap reduced by the tap reduction means. 2. The apparatus according to claim 1, further comprising separation means for separating the luminance signal component and the color signal component from the first digital image signal when the first digital image signal is a composite signal. The signal converter described. The second calculation means includes:
By bit-shifting the color signal component of the first digital image signal, a multiplication result obtained by multiplying the color signal component by the second coefficient is obtained,
2. The signal conversion apparatus according to claim 1, wherein the multiplication result is added to calculate the second coefficient and the color signal component of the first digital image signal. The signal conversion apparatus according to claim 1, wherein the class classification unit obtains the class based on a spatial characteristic and a motion amount of a luminance signal component of the first digital image signal. The first computing means includes first or second mode computing means corresponding to the first or second mode, respectively.
The signal conversion apparatus according to claim 1, wherein the degeneration unit includes a first or second mode degeneration unit corresponding to the first or second mode, respectively. The signal conversion apparatus according to claim 1, further comprising a reduction unit that reduces the number of classes. First changing means for changing the order of the scanning lines of the first digital image signal inputted to the first calculating means in the case of the first mode and the second mode;
And a second changing means for changing the order of the scanning lines of the second digital image signal output from the first calculating means to the order before being changed by the first changing means. The signal conversion apparatus according to claim 1. The first coefficient for each class stored in the storage means is generated by performing learning using an image signal having the same resolution as the second digital image signal as learning data. 2. The signal conversion apparatus according to 1. 2. The signal conversion apparatus according to claim 1, wherein each of the storage unit, the class classification unit, and the first or second calculation unit is configured by one chip. The tap reduction means has at least a plurality of input means and reduction processing means,
In each of the input means, two luminance signal components of the first digital image signal are input,
As a result of the positional relationship between the pixels of the first and second digital image signals and the comparison from the comparison means , the change in the spatial characteristics of the first area is determined from the change in the spatial characteristics of the second area. Is large,
Each of the input means selects one of the two luminance signal components of the first digital image signal and outputs the selected one to the degeneration processing means.
The signal conversion apparatus according to claim 1, wherein the degeneration processing unit degenerates the number of taps. Each of the input means receives the luminance signal component of the first digital image signal to be input as a tap, and has a mirror image relationship in the horizontal direction with respect to the vertical direction passing through the center of the tap. The signal conversion apparatus according to claim 12, wherein a pixel in which a pixel exists is input to one input unit, and the other pixels are input to one different input unit. In a signal conversion method for converting a first digital image signal into a second digital image signal having a higher resolution than the first digital image signal,
Classifying the class based on the luminance signal component of the first digital image signal,
Comparing a change in spatial characteristics of a first region in the first digital image signal with a change in spatial features of a second region that is larger than the first region;
When the change in the spatial feature of the first region is larger than the change in the spatial feature of the second region, the number of taps of the luminance signal component of the first digital signal is degenerated,
The storage unit storing the first coefficient for converting the luminance signal component of the first digital image signal into the luminance signal component of the second digital image signal for each class. By reading the first coefficient corresponding to the class, and calculating the first coefficient and the luminance signal component of the first digital image signal in which the number of taps is degenerated according to the result of the comparison, Obtaining a luminance signal component of the second digital image signal;
By calculating the second coefficient obtained based on the positional relationship between the pixels of the first and second digital image signals and the color signal component of the first digital image signal, the second coefficient A signal conversion method characterized by obtaining a color signal component of a digital image signal.

Images