JP3308005B2 - Image conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. BACKGROUND OF THE INVENTION Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Function (FIGS. 4 and 5) Example (FIGS. 1 to 7) (1) Implementation Overall Configuration of Example (1-1) Configuration of Progressive Scan Converter 1 (FIGS. 1 and 4) (1-2) Configuration of Progressive Scan Image Synthesis Circuit 3 (FIGS. 2 and 4 to 7) (1-3) ) Configuration of Image Discrimination Circuit 2 (FIG. 3) (2) Operation of Embodiment (FIGS. 4 and 5) (3) Effects of Embodiment (4) Other Embodiments Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image conversion apparatus, and more particularly to an image conversion apparatus suitable for converting an input image signal into an original progressively scanned image when the input image signal is a computer graphic image or the like.

[0003]

2. Description of the Related Art Conventionally, computer graphic images and animation images (hereinafter referred to as computer images, etc.).
Is composed of images at 30 frames per second.
Each image is displayed on the screen by sequential scanning.

When it is desired to display a computer image or the like displayed by progressive scanning in a standard television system, the image is converted into a standard television system composed of images at 30 frames per second and 60 fields. The image signal of each frame is interlaced and divided into image signals corresponding to an odd field and an even field of the standard television system.

[0005]

However, when a computer image or the like is displayed by a standard television receiver, a progressively scanned image transmitted at 30 frames per second is used as a television signal transmission system. In addition, since the image is converted into an interlaced scan image of 60 fields per second, almost the same image is continued by two fields at a time, deteriorating the vertical resolution and causing interference by a double image.

Therefore, IDTV (Improved Television)
), EDTV (Enhanced Television or Extened Def
In the inition Television system, such a deterioration in vertical resolution is converted by converting a computer image converted into an image of a standard television system into an image signal of a progressive scanning system by motion adaptive scanning line interpolation. It has been made to eliminate.

However, in general, the image signal does not include a code for distinguishing between a computer image or the like (sequential scanning) and a standard television system image (interlaced scanning).
In motion-adaptive scanning line interpolation, a still image (for example, an image that does not appear to change with respect to the time axis like an image of a still object) is synthesized into a continuous field screen regardless of the process of generating the original image. The moving image is displayed by interpolating the pixels of the scanning line dropped by the pixels in the same field. However, at this time, if motion detection omission or erroneous detection occurs, the image may not be correctly interpolated.

In the case of an image obtained by converting a computer image or the like originally displayed by sequential scanning into an image signal by interlaced scanning, it is better to combine and display two continuous field images even for a moving image. There is no deterioration. For this reason, if it is possible to determine whether the image signal of the standard television system to be converted by the scanning system is originally a computer image or the like and convert the scanning system, the image signal by the interlaced scanning is converted into an image signal of the sequential scanning. It is considered that the possibility that the image quality will be degraded when the image is converted into the image can be effectively avoided.

The present invention has been made in consideration of the above points, and when an image signal obtained by converting a computer image or the like into the interlaced scanning method is input, this is reliably detected and the original progressively scanned image is converted. It is intended to propose an image conversion device for converting and outputting.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, according to the present invention, among the input image signals S1 of the interlaced scanning system input from the outside, a converted image obtained by converting from a progressive scanning system to an interlaced scanning system is used. A determination means 2 for determining a signal; and 2 for the read speed of the input image signal S1.
A first double-speed image signal S7 having a double-speed reading speed is generated, and the first double-speed image signal S7 is delayed by one field from the first double-speed image signal S7 and has the same speed as the double-speed reading speed of the first double-speed image signal S7. And a first double-speed image signal S7 and a second double-speed image signal S8 corresponding to two continuous fields among the first double-speed image signal S7 and the second double-speed image signal S8. Sequential scanning image generating means 9, 10, 11 for generating a progressive scanning image signal S2 by sequentially combining the double speed image signal S7 and the second double speed image signal S8 at a double speed reading speed for each scanning line; 2
And an image switching means 4 for switching the external output of the input image signal S1 to the external output of the scanning image signal S2 when the converted image signal is determined by the following.

[0011]

[0012]

According to an aspect of the present invention, an interlaced scan converted image signal is determined from an input image signal by an image determining unit, and a detection signal is output.
The image signal S2 of the progressive scanning method generated by the progressive scanning image generation means 3 from the input image signal S1 is switched by the image switching means 4 to the input image signal S1 in accordance with the detection signal S4 and output. When the image signal is an interlaced scan converted image signal, the interlaced scan converted image signal can be detected with high accuracy and an image signal based on the original progressive scanning method can be output.

By alternately combining the scanning line signals S7 and S8 between successive fields of the input image signal S1 at twice the readout speed of the input image signal S1 by the scanning method, the input image signal S1 is interlaced. When the input image signal is an image signal, the input image signal S1 can be surely reconverted into an image signal by the original sequential scanning method.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Overall Configuration of Embodiment (1-1) Configuration of Progressive Scan Converter 1 In FIG. 1, reference numeral 1 denotes a progressive scan converter as a whole, and an input image input by a standard television system. A moving image (hereinafter, referred to as a scanning-system-converted moving image) which is converted from the image originally displayed by the sequential scanning method (hereinafter, referred to as an original progressive scanning image) to the interlaced scanning method and displayed is detected from the signal S1. The detected scanning-system-converted moving image is reconverted into an original progressively scanned image and output.

That is, the progressive scan conversion device 1 detects whether or not the input image signal S1 is a scanning format conversion moving image in the image discrimination circuit 2, and if the input image signal S1 is a scanning format conversion moving image, the progressive scanning image synthesis circuit 3 The output double speed frame signal S2 is output via the image switching circuit 4.

On the other hand, the progressive scanning converter 1 outputs the delayed input image signal S3 output from the field memory 5 via the image switching circuit 4 when the moving image is not a scanning system converted moving image.

Here, the image discriminating circuit 2 receives the input image signal S1.
Is input to detect a scanning format conversion moving image from the input image signal S1, a detection signal S4 of logic "1" is supplied to the image switching circuit 4, and the image switching circuit 4 reconverts the image into the original sequential scanning image. The double-speed frame signal S2 (FIG. 4 (F)) is switched and output as the output image signal S5. In other cases, the detection signal S4 of logic "0" is supplied to the image switching circuit 4, and the image switching circuit 4 The delayed input image signal S3 (FIG. 4)
(B)) is switched and output as the output image signal S5.

The progressive scanning image synthesizing circuit 3 receives the input image signal S
1 (FIG. 4 (A)) are alternately combined at twice the standard readout speed (hereinafter referred to as double-speed readout speed) to generate scanning image signals sequentially by successively combining scanning lines in two field periods, and generating a double-speed frame signal. S2 (FIG. 4 (F))
Is output to the image switching circuit 4 every two consecutive field periods at the standard read speed.

The field memory 5 stores the input image signal S1 in the current field period at a standard read speed in accordance with the input order, and also stores the input image signal S1 stored one field period before the delayed input image signal. The signals are output to the image switching circuit 4 in the order input as the signal S3 (FIG. 4B). Thus, the input image signal S1 is delayed in accordance with the delay time of the processing in the sequential scanning image synthesizing circuit 3.

(1-2) Configuration of the progressively scanned image synthesizing circuit 3 In FIG. 2, the progressively scanned image synthesizing circuit 3 inputs the input image signal S1 (FIG. 4A) in the current field period to the field memory 6. The input image signal S1 stored one field before is stored as the delay signal S6 (FIG. 4B) in accordance with the standard read speed, and is stored at the standard read speed in accordance with the order. The data is supplied to the line memory 7.

The line memory 7 stores the delay signal S6 (FIG. 5A) of the current scanning period at a standard read speed in accordance with the input order, and stores the delay signal S6 stored one scanning period before. Are read once at the double reading speed in accordance with the input order, and this is read as the delay line signal S.
7 (FIG. 5C), and sequentially output to the scanning signal synthesizing circuit 9. Subsequently, the same delay signal S6 is read out again by the same procedure, and is sequentially output to the scanning signal synthesizing circuit 9 as a delay line signal S7. As a result, the same delay line signal S7 is output twice consecutively during one scanning period.

The line memory 8 stores an input image signal S1 (FIG. 5).
(B)) is processed in the same manner as in the line memory 7, and this is sequentially output to the scanning signal synthesizing circuit 9 as a delay line signal S8. As a result, the same delay line signal S8
Is output twice consecutively.

In the first half of the scanning period at the standard reading speed, the sequential scanning signal synthesizing circuit 9 outputs the odd / even signal S9 (FIG. 5) of the sequential scanning line at the double reading speed.
Since the logic value of (E) becomes logic "0", the signal is switched to the delay line signal S7 (FIG. 5C), and the logic value of the odd / even signal S9 becomes logic "1" in the latter half of the scanning period. Therefore, the signal is switched to the delay line signal S8 (FIG. 5D).

In this manner, the sequential scanning signal synthesizing circuit 9 alternately combines the image signals of the input image signal S1 in each of two consecutive field periods in units of one scanning line at the double-speed readout speed, thereby forming one frame at each double-speed readout speed. An image signal is synthesized, and this is synthesized with a double speed synthesized signal S10 (FIG. 5).
(F)) is output to the frame memory 10 and the double-speed frame image duplication generation circuit 11.

The operation of the progressive scanning signal synthesizing circuit 9 at this time is shown by comparing the scanning line structure before and after the progressive scanning conversion. As shown in FIG. 6, the (K) and (K + 2) -th image signals on the scanning line of a certain frame of the original progressively scanned image
(B1), □ (B3)... And (K + 1), (K +
3) Image signal on scanning line □ (B2), □ (B4)
.. Are assumed to have been subjected to interlaced scan conversion as the (N) th and (N + 1) th field image signals of the input image signal S1, respectively.

As shown in FIG. 7, two consecutive field image signals are first delayed field image signals,
Next, the scanning lines are alternately synthesized in units of one scanning line at the double reading speed in the order of the image signals of the current field.
As a result, the (N) th and (N +) th of the input image signal S1 are obtained.
1) The image signal of the field is the (K) of the progressively scanned image,
(K + 1), (K + 2), (K + 3)... Image signals □ (B1), □ (B2), □ (B3), □ on the scanning line
(B4)... Of the double-speed synthesized signal S10 having the (N +
1) It is converted into a field image signal.

The frame memory 10 stores the double-speed synthesized signal S10 (FIG. 4C) in the current field period at a double-speed reading speed in accordance with the input order, and stores one field at the standard reading speed (ie, double-speed reading). The speed-doubled synthesized signal S10 stored before the period (one frame in the speed) is replaced with the delayed double-speed synthesized signal S11 (FIG. 4).
(D)) is output to the double speed frame image duplication generation circuit 11 at the double speed readout speed in accordance with the input order.

The double-speed frame image duplication generation circuit 11 generates a field odd / even signal S at a standard read speed.
12 (FIG. 4 (E)), in the odd field where the logical value becomes logical "1", the delayed double speed composite signal S11 (FIG.
(D)), and switches to the double-speed synthesized signal S10 (FIG. 4 (C)) in the even field where the logic becomes "0".

Thus, the double-speed frame image duplication generating circuit 11 has the same scanning line structure as the original progressively scanned image when the scanning system converted moving image is input, and is synthesized so as to be reconverted. The image signal at the speed is output to the image switching circuit 4 as a double-speed frame signal S2 (FIG. 4 (F)) for each two consecutive field periods at the standard read speed.

In FIG. 4, V [N] and V [N +
1] correspond to the (N) th and (N + 1) th fields respectively corresponding to the odd field and the even field of the input image signal S1.
... Represents a field image signal, and V ｛[N−1] +
[N]}, V {[N] + [N + 1]}... Represent the (N) th, (N + 1) th... Field image signals corresponding to the odd field and the even field of the double-speed synthesized signal S10, respectively. "1" and "0" represent the logical values of the odd / even signal S12 of the field of the input image signal S1.

In FIG. 5, (L), (L + 1)...
.. Represent line signals of (L) and (L + 1)... Scanning lines corresponding to the odd-numbered scanning line and the even-numbered scanning line of the delay signal S6, respectively, and (M) and (M + 1). The line signals of (M), (M + 1)... Corresponding to the odd-numbered scanning line and the even-numbered scanning line in S1 are represented. Further, "0" and "1" represent the logical values of the odd / even signal S9 of the sequential scanning line at the double speed reading speed.

(1-3) Configuration of Image Discriminating Circuit 2 In FIG. 3, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals, the image discriminating circuit 2 includes a field signal difference circuit 1
2. It is composed of a field image contour coincidence detection circuit section 13 and a judgment circuit 14, and detects a scanning format conversion moving image from an input image signal S1.

When the input image signal S1 is input, the field signal difference circuit 12 stores the input image signal S1 in the current field period in the frame memory 15 in the order of input, and stores the input image signal S1 two fields before. The input image signal S1 is supplied to the subtracter 16 in the order in which the input image signal S1 is input as the delay signal S13.

The subtractor 16 sequentially calculates the difference between the input image signal S1 and the delay signal S13 in the current field period, and outputs the difference to the vertical interpolation filter 17 as a difference signal S14.

The vertical interpolation filter 17 outputs the difference signal S14
The field image paired with the field image transmitted as above is vertically interpolated by pixels in the same field, and a vertical interpolation signal S15 constituted by the pixels of the interpolated scanning line is supplied to a field memory 18. The difference signal S14 is band-limited so as to have the same band as the vertical interpolation signal S15, and is supplied to the subtracter 19 as a difference line signal S16.

The field memory 18 stores the vertical interpolation signal S15 for the current field period in the order in which it was input, and also stores the vertical interpolation signal S15 stored one field period before as the interpolation line signal S17. Then, it is supplied to a subtractor 19.

The subtractor 19 sequentially obtains the difference between the pixels on the same scanning line between the difference line signal S16 and the interpolation line signal S17 interpolated so as to have the same scanning line in the vertical interpolation filter 17, and calculates the difference. Difference signal S1
8 is output to the determination circuit 14.

A field image contour coincidence detection circuit 1
3 is horizontal (or vertical) when the input image signal S1 is input.
The edge detection circuit 20 (or 21) detects a horizontal (or vertical) component of the outline of the image of the input image signal S1, and converts each detected component to the edge signal S19 (or S2).
0) to the field memory 22 (or 23) and the pattern matching circuit 24 (or 25).

The field memories 22 and 23 store the edge signals S19 and S20 of the current field period in the order in which they were input, respectively, and store the signals stored one field period ago before the delayed edge signals S21 and S20.
The data is output to the pattern matching circuits 24 and 25 according to the input order as 22.

The pattern matching circuits 24 and 25 sequentially compare the edge signals S19 and S20 and the delayed edge signals S21 and S22, respectively, to confirm pattern coincidence and non-coincidence, and use them as coincidence determination signals S23 and S24. Output to

The judgment circuit 14 calculates the field difference signal S1
8, the match determination signals S23 and S24 are sequentially input, and the field difference signal S18 and the match determination signals S23 and S24 are input.
When the logic value of “1” and “0” are alternately repeated for each field, it is determined that the input image signal S1 is a scanning format conversion moving image, and a detection signal S4 of logic “1” is output. In other cases, a detection signal S4 of logic "0" is output.

Thus, the image discriminating circuit 2 vertically interpolates the field image forming a pair with the difference signal S14 obtained by calculating the difference between the input image signal S1 and the delay signal S13 obtained by delaying the input image signal S1 by one frame. The interpolation line signal S17 delayed by one field and the difference signal S
14 is a field difference signal S18 that outputs a difference value from a difference line signal S16 whose band is limited according to the interpolation line signal S17, and a match determination that confirms a mismatch between contours of images in two consecutive field periods of the input image signal S1. The signals S23 and S24 are input to the determination circuit 14, and in the scanning method conversion moving image, utilizing the fact that the correlation between the image signal and the image contour of the odd and even fields belonging to the same frame before the interlaced scan conversion is large, By detecting a regular signal pattern of logic "1" and "0" generated when the input image signal S1 is a scanning system conversion moving image, the scanning system conversion moving image is detected with high accuracy. .

(2) Operation of Embodiment In the above configuration, the progressive scan converter 1 processes the input image signal S1 based on the timing charts shown in FIGS. 4 and 5, and converts the input image signal S1 into a scanning system as the input image signal S1. When a moving image is input, a double-speed frame signal S2 (FIG. 4 (F)) obtained by sequentially scanning-converting the input image signal S1 is output, and in other cases, a delayed input image signal S3 obtained by delaying the input image signal S1 (FIG. 4B) is output.

The progressive scan converter 1 receives the input image signal S1
The image signal V of the (N + 1) th field (FIG. 4A)
When [N + 1] is input to the sequential scanning image synthesizing circuit 3, the (N + 1) th field image signal V [N + 1] is stored in the field memory 6 and the (N) th field image signal V [one field period before. N] to the line memory 7 as a delay signal S6 (FIG. 4B).

Subsequently, the line memory 7 scans the (L + 1) th, (L + 2)... Scanning lines (FIG. 5 (N)) of the (N) th field image signal V [N] of the delay signal S6 (FIG. 4B). A))
, And (L), (L + 1),... The line signals (L), (L + 1),. The signal is output to the scanning signal synthesizing circuit 9 twice in succession as a signal S7 (FIG. 5C).

On the other hand, the line memory 8 stores the input image signal S1.
The image signal V of the (N + 1) th field (FIG. 4A)
(N + 1) -th (M + 1), (M + 2)... Line signals (M + 1), (M + 2) of the scanning lines (FIG. 5B)
, And (M) and (M) one scanning period before.
+1)... Line signals of scanning lines (M), (M + 1).
Are successively output twice to the scanning signal synthesizing circuit 9 successively as a delay line signal S8 (FIG. 5D).

The sequential scanning signal synthesizing circuit 9 outputs the first line signal (L) of the (L), (L + 1)... Of the delay line signal S7 for each scanning period at the standard read speed. (L + 1)... And (M), (M + 1)... Of the delay line signal S8 to the second line signal (M), (M + 1).

Accordingly, the sequential scanning signal synthesizing circuit 9 synthesizes the (N) th and (N + 1) th field image signals of the input image signal S1 at double reading speed, and outputs the line signals (L), (M), The image signal V of the (N + 1) th field of the double-speed synthesized signal S10 (FIGS. 5 (F) and 4 (C)) of one frame having (L + 1), (M + 1).
{[N] + [N + 1]} is output to the frame memory 10 and the double-speed frame image duplication generation circuit 11.

The frame memory 10 stores the double-speed synthesized signal S10
The image signal V of the (N + 1) th field in FIG.
{[N] + [N + 1]} is stored, and the image signal V {[N−
1] + [N]} is combined with the delayed double-speed synthesized signal S11 (FIG. 4).
(D)) is output to the double-speed frame image duplication generation circuit 11.

The double-speed frame image duplication generation circuit 11 generates the double-speed synthesized signal S in the even-numbered (N + 1) th field.
The tenth (N + 1) th field image signal V ｛[N] +
[N + 1]}, and in the next odd (N + 2) th field, the delayed double-speed synthesized signal S11 (FIG. 4)
(D)) The image signal V of the (N + 2) th field
The signal is switched to {[N] + [N + 1]} and output to the image switching circuit 4 as the double-speed frame signal S2 (FIG. 4 (F)).

The field memory 5 stores the input image signal S1
The image signal V of the (N + 1) th field (FIG. 4A)
[N + 1] is stored at the standard readout speed, and the image signal V [N] of the (N) th field one field before is used as the delayed input image signal S3 (FIG. 4B) at the standard readout speed. Then, it outputs to the image switching circuit 4.

As a result, when the scanning system converted moving image is input as the input image signal S1, the image discriminating circuit 2 sets the logic "1".
Is output to the image switching circuit 4, the image switching circuit 4 outputs the (N + 1) th, (N + 2)... Field image signal V {[N] + [N] of the double-speed frame signal S2.
+1]}, V {[N] + [N + 1]}... Are output as output image signals S5.

On the other hand, when an image other than the scanning method conversion moving image is input as the input image signal S1, the image discriminating circuit 2
Outputs the detection signal S4 of logic "0" to the image switching circuit 4, and the image switching circuit 4 outputs the (N + 1) th, (N + 2)... Field image signal V of the delayed input image signal S3.
[N], V [N + 1],... Are switched and output as output image signals S5.

(3) Effects of the Embodiment According to the above configuration, when the scanning method conversion moving image is input as the input image signal S1, the continuation of the input image signal S1 is converted again to the original progressively scanned image. By switching the output of the image switching circuit 4 in accordance with the detection signal S4 output from the image discriminating circuit 2, the double-speed frame signal S2 obtained by alternately combining the scanning lines between the two fields at the double-speed readout speed is scanned. Can be detected with high accuracy and can be reliably converted to the original progressively scanned image.

(4) Other Embodiments In the above embodiment, the field memory 5 and the field memory 6 are used, respectively. However, the present invention is not limited to this, and the field memory 5 is omitted and the field memory 6 is omitted. The output delay signal S6 may be input to the image switching circuit 4 instead of the delay input image signal S3. In this case, a memory for finely adjusting the delay timing of the input image signal S1 may be provided in the sequential scanning image synthesizing circuit 3 or the image switching circuit 4.

Further, in the above-described embodiment, the sequential scanning signal synthesizing circuit 9 switches to the delay line signal S7 (FIG. 5C) in the first half of the scanning period at the standard read speed in any field, and switches to the delay line signal S7 (FIG. 5C). In the latter half, the image signal of each one frame is synthesized by switching to the delay line signal S8 (FIG. 5D). However, the present invention is not limited to this, and the sequential scanning signal synthesizing circuit 9 is not limited to this. Are odd-numbered (N), (N + 2)... In the field, switching to the delay line signal S8 in the first half of the scanning period, and switching to the delay line signal S7 in the second half of the scanning period, thereby forming one frame of the image signal. May be combined.

[0058]

As described above, according to the present invention, a discriminating means for discriminating a converted image signal obtained by converting from a progressive scanning method to an interlaced scanning method among input image signals of an interlaced scanning method inputted from the outside. And generating a first double-speed image signal having a double-speed reading speed that is twice as high as the reading speed of the input image signal, and delaying the first double-speed image signal by one field. Double speed image signal generating means for generating a second double speed image signal having the same speed as the double speed reading speed, and a first speed corresponding to two continuous fields among the first double speed image signal and the second double speed image signal. A double-speed image signal and a second double-speed image signal are alternately combined for each scanning line at a double-speed reading speed to generate a sequential scanning image signal of a sequential scanning method; There When it is determined, an external output of the input image signal, is provided an image switching means for switching to the external output progressive scan image signal. Thus, only when the converted image signal is originally the progressive scanning method, the original progressive scanning image signal of the original sequential scanning method with less image quality deterioration than the converted image signal is externally output and temporarily converted to the interlaced scanning method. It is possible to effectively prevent image quality degradation in the image signal that has been obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image conversion apparatus according to the present invention.

FIG. 2 is a block diagram showing a progressive scan image synthesizing circuit in the progressive scan converter.

FIG. 3 is a block diagram showing an image discriminating circuit in the progressive scan converter.

FIG. 4 is a timing chart of a field cycle for explaining each signal processing in the present invention.

FIG. 5 is a timing chart of a horizontal scanning cycle for explaining each signal processing in the present invention.

FIG. 6 is a schematic diagram illustrating a scanning line structure of an interlaced scanning converted image at a conventional standard reading speed.

FIG. 7 is a schematic diagram showing a scanning line structure of a progressive scan conversion image for explaining a scanning line synthesizing operation in the present invention.

[Explanation of symbols]

1.... Progressive scan conversion device, 2.... Image discriminating circuit, 3..
... Progressive scanning image synthesis circuit, 4... Image switching circuit, 5, 6.
... Field memory, 7, 8 ... Line memory, 9 ...
Progressive scanning signal synthesis circuit, 10 ... frame memory, 11
... Double speed frame image duplication generation circuit.

Claims (1)

(57) [Claims] (1)Use of interlaced scanning input from outside
Interlaced scanning from progressive scanning based on the force image signal
Discriminating means for discriminating a converted image signal converted into a system
When, Double reading speed twice as high as the reading speed of the input image signal
And generating a first double-speed image signal of the
Delayed by one field from the double-speed image signal,
The second double-speed image having the same speed as the double-speed reading speed of the double-speed image signal
Double-speed image signal generating means for generating an image signal; The first double-speed image signal and the second double-speed image signal
The first one corresponding to two consecutive fields
The double speed image signal and the second double speed image signal are read at the double speed.
The above sequential scanning method by combining the scanning lines alternately at the output speed
Scanning image generating means for generating a progressive scanning image signal
When, When the conversion image signal is determined by the determination unit
Externally outputs the input image signal to the progressive scan image.
Image switching means for switching to an external output of an image signal; Equipped with
An image conversion device, characterized in that: